248 lines
9.3 KiB
Plaintext
248 lines
9.3 KiB
Plaintext
/*
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* Device Tree Generator version: 1.3
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*
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* (C) Copyright 2007-2008 Xilinx, Inc.
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* (C) Copyright 2007-2009 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* CAUTION: This file is automatically generated by libgen.
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* Version: Xilinx EDK 13.2 EDK_O.61xd
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*
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* XPS project directory: device-tree_bsp_230-orig
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,microblaze";
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model = "testing";
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MCB3_LPDDR: memory@80000000 {
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device_type = "memory";
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reg = < 0x80000000 0x4000000 >;
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} ;
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aliases {
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ethernet0 = &Ethernet_MAC;
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serial0 = &USB_Uart;
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} ;
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chosen {
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bootargs = "console=ttyUL0";
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linux,stdout-path = "/axi@0/serial@40600000";
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} ;
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cpus {
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#address-cells = <1>;
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#cpus = <0x1>;
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#size-cells = <0>;
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microblaze_0: cpu@0 {
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clock-frequency = <66666667>;
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compatible = "xlnx,microblaze-8.20.a";
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d-cache-baseaddr = <0x80000000>;
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d-cache-highaddr = <0x83ffffff>;
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d-cache-line-size = <0x10>;
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d-cache-size = <0x2000>;
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device_type = "cpu";
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i-cache-baseaddr = <0x80000000>;
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i-cache-highaddr = <0x83ffffff>;
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i-cache-line-size = <0x10>;
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i-cache-size = <0x2000>;
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model = "microblaze,8.20.a";
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reg = <0>;
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timebase-frequency = <66666667>;
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xlnx,addr-tag-bits = <0xd>;
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xlnx,allow-dcache-wr = <0x1>;
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xlnx,allow-icache-wr = <0x1>;
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xlnx,area-optimized = <0x0>;
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xlnx,avoid-primitives = <0x0>;
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xlnx,branch-target-cache-size = <0x0>;
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xlnx,cache-byte-size = <0x2000>;
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xlnx,d-axi = <0x1>;
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xlnx,d-lmb = <0x1>;
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xlnx,d-plb = <0x0>;
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xlnx,data-size = <0x20>;
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xlnx,dcache-addr-tag = <0xd>;
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xlnx,dcache-always-used = <0x1>;
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xlnx,dcache-byte-size = <0x2000>;
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xlnx,dcache-data-width = <0x0>;
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xlnx,dcache-force-tag-lutram = <0x0>;
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xlnx,dcache-interface = <0x0>;
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xlnx,dcache-line-len = <0x4>;
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xlnx,dcache-use-fsl = <0x0>;
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xlnx,dcache-use-writeback = <0x0>;
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xlnx,dcache-victims = <0x0>;
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xlnx,debug-enabled = <0x1>;
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xlnx,div-zero-exception = <0x0>;
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xlnx,dynamic-bus-sizing = <0x1>;
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xlnx,ecc-use-ce-exception = <0x0>;
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xlnx,edge-is-positive = <0x1>;
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xlnx,endianness = <0x1>;
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xlnx,family = "spartan6";
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xlnx,fault-tolerant = <0x0>;
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xlnx,fpu-exception = <0x0>;
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xlnx,freq = <0x3f940ab>;
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xlnx,fsl-data-size = <0x20>;
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xlnx,fsl-exception = <0x0>;
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xlnx,fsl-links = <0x0>;
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xlnx,i-axi = <0x0>;
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xlnx,i-lmb = <0x1>;
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xlnx,i-plb = <0x0>;
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xlnx,icache-always-used = <0x1>;
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xlnx,icache-data-width = <0x0>;
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xlnx,icache-force-tag-lutram = <0x0>;
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xlnx,icache-interface = <0x0>;
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xlnx,icache-line-len = <0x4>;
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xlnx,icache-streams = <0x0>;
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xlnx,icache-use-fsl = <0x0>;
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xlnx,icache-victims = <0x0>;
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xlnx,ill-opcode-exception = <0x0>;
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xlnx,instance = "microblaze_0";
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xlnx,interconnect = <0x2>;
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xlnx,interconnect-m-axi-dc-aw-register = <0x0>;
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xlnx,interconnect-m-axi-dc-read-issuing = <0x2>;
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xlnx,interconnect-m-axi-dc-w-register = <0x0>;
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xlnx,interconnect-m-axi-dc-write-issuing = <0x20>;
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xlnx,interconnect-m-axi-dp-read-issuing = <0x1>;
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xlnx,interconnect-m-axi-dp-write-issuing = <0x1>;
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xlnx,interconnect-m-axi-ic-read-issuing = <0x2>;
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xlnx,interconnect-m-axi-ip-read-issuing = <0x1>;
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xlnx,interrupt-is-edge = <0x0>;
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xlnx,lockstep-slave = <0x0>;
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xlnx,mmu-dtlb-size = <0x1>;
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xlnx,mmu-itlb-size = <0x1>;
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xlnx,mmu-privileged-instr = <0x0>;
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xlnx,mmu-tlb-access = <0x3>;
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xlnx,mmu-zones = <0x2>;
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xlnx,number-of-pc-brk = <0x1>;
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xlnx,number-of-rd-addr-brk = <0x0>;
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xlnx,number-of-wr-addr-brk = <0x0>;
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xlnx,opcode-0x0-illegal = <0x0>;
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xlnx,optimization = <0x0>;
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xlnx,pvr = <0x0>;
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xlnx,pvr-user1 = <0x0>;
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xlnx,pvr-user2 = <0x0>;
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xlnx,reset-msr = <0x0>;
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xlnx,sco = <0x0>;
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xlnx,stream-interconnect = <0x0>;
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xlnx,unaligned-exceptions = <0x0>;
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xlnx,use-barrel = <0x1>;
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xlnx,use-branch-target-cache = <0x0>;
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xlnx,use-dcache = <0x1>;
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xlnx,use-div = <0x0>;
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xlnx,use-ext-brk = <0x1>;
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xlnx,use-ext-nm-brk = <0x1>;
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xlnx,use-extended-fsl-instr = <0x0>;
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xlnx,use-fpu = <0x0>;
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xlnx,use-hw-mul = <0x1>;
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xlnx,use-icache = <0x1>;
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xlnx,use-interrupt = <0x1>;
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xlnx,use-mmu = <0x3>;
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xlnx,use-msr-instr = <0x1>;
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xlnx,use-pcmp-instr = <0x0>;
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xlnx,use-stack-protection = <0x0>;
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} ;
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} ;
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axi4lite_0: axi@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,axi-interconnect-1.03.a", "simple-bus";
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ranges ;
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Ethernet_MAC: ethernet@40e00000 {
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compatible = "xlnx,axi-ethernetlite-1.00.a", "xlnx,xps-ethernetlite-1.00.a";
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device_type = "network";
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interrupt-parent = <µblaze_0_intc>;
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interrupts = < 2 0 >;
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local-mac-address = [ 00 0a 35 aa de 00 ];
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// phy-handle = <&phy0>;
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reg = < 0x40e00000 0x10000 >;
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xlnx,duplex = <0x1>;
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xlnx,family = "spartan6";
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xlnx,include-global-buffers = <0x0>;
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xlnx,include-internal-loopback = <0x0>;
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xlnx,include-mdio = <0x1>;
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xlnx,include-phy-constraints = <0x1>;
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xlnx,interconnect-s-axi-read-acceptance = <0x1>;
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xlnx,interconnect-s-axi-write-acceptance = <0x1>;
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xlnx,rx-ping-pong = <0x0>;
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xlnx,s-axi-aclk-period-ps = <0x3a98>;
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xlnx,s-axi-id-width = <0x1>;
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xlnx,s-axi-supports-narrow-burst = <0x0>;
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xlnx,tx-ping-pong = <0x0>;
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/*
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: phy@7 {
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compatible = "marvell,88e1111";
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device_type = "ethernet-phy";
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reg = <7>;
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} ;
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} ;
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*/
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} ;
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SPI_FLASH: spi@40a00000 {
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compatible = "xlnx,axi-spi-1.01.a", "xlnx,xps-spi-2.00.a";
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interrupt-parent = <µblaze_0_intc>;
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interrupts = < 1 2 >;
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reg = < 0x40a00000 0x10000 >;
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xlnx,family = "spartan6";
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xlnx,fifo-exist = <0x1>;
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xlnx,num-ss-bits = <0x1>;
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xlnx,num-transfer-bits = <0x8>;
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xlnx,sck-ratio = <0x4>;
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} ;
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USB_Uart: serial@40600000 {
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clock-frequency = <66666667>;
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compatible = "xlnx,axi-uartlite-1.02.a", "xlnx,xps-uartlite-1.00.a";
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current-speed = <115200>;
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device_type = "serial";
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interrupt-parent = <µblaze_0_intc>;
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interrupts = < 3 0 >;
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port-number = <0>;
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reg = < 0x40600000 0x10000 >;
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xlnx,baudrate = <0x1c200>;
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xlnx,data-bits = <0x8>;
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xlnx,family = "spartan6";
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xlnx,odd-parity = <0x1>;
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xlnx,s-axi-aclk-freq-hz = <0x3f940ab>;
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xlnx,use-parity = <0x0>;
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} ;
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microblaze_0_intc: interrupt-controller@41200000 {
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#interrupt-cells = <0x2>;
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compatible = "xlnx,axi-intc-1.01.a", "xlnx,xps-intc-1.00.a";
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interrupt-controller ;
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reg = < 0x41200000 0x10000 >;
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xlnx,kind-of-intr = <0xc>;
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xlnx,num-intr-inputs = <0x4>;
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} ;
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system_timer: timer@41c00000 {
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clock-frequency = <66666667>;
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compatible = "xlnx,axi-timer-1.02.a", "xlnx,xps-timer-1.00.a";
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interrupt-parent = <µblaze_0_intc>;
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interrupts = < 0 2 >;
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reg = < 0x41c00000 0x10000 >;
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xlnx,count-width = <0x20>;
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xlnx,family = "spartan6";
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xlnx,gen0-assert = <0x1>;
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xlnx,gen1-assert = <0x1>;
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xlnx,one-timer-only = <0x0>;
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xlnx,trig0-assert = <0x1>;
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xlnx,trig1-assert = <0x1>;
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} ;
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} ;
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} ;
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