buildroot

History

Julien Olivain fd988ac2b8 board/spike/riscv64/readme.txt: update riscv-openocd URL The URL https://github.com/riscv/riscv-openocd is now redirecting to: https://github.com/riscv-collab/riscv-openocd This commit updates the URL to this new location. Signed-off-by: Julien Olivain <ju.o@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>		2024-07-13 16:21:45 +02:00
..
patches	configs/spike_riscv64: bump kernel to 6.6.35 and add hashes	2024-07-12 22:39:45 +02:00
readme.txt	board/spike/riscv64/readme.txt: update riscv-openocd URL	2024-07-13 16:21:45 +02:00
start.sh	board/spike/riscv64/start.sh: add buildroot host dir in PATH	2022-01-13 20:38:49 +01:00

readme.txt

Linux on Spike RISC-V ISA simulator
===================================

This configuration provides a minimal working setup to run a Linux
kernel in the Spike RISC-V ISA simulator.

The Spike ISA simulator can be an interresting alternative to Qemu, in
some specific cases. For example: simulating new instructions (see [1]),
simulating riscv-openocd/gdb debug sessions (see [2], [3]), or
generating an accurate per-instruction log of execution (see
riscv-isa-sim spike -l option)...

To run Buildroot Linux in Spike, use the commands:

    make spike_riscv64_defconfig
    make
    ./board/spike/riscv64/start.sh

The boot is made with the standard RISC-V OpenSBI boot loader. In
order to keep the simulation simple, the rootfs is passed as an initrd
ramfs.


[1].
https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#simulating-a-new-instruction

[2].
https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#debugging-with-gdb

[3].
https://github.com/riscv-collab/riscv-openocd