ghidra/Ghidra/Processors/8048/data/languages/8048.pspec

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XML

<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<default_symbols>
<symbol name="BANK0_R0" address="INTMEM:00"/>
<symbol name="BANK0_R1" address="INTMEM:01"/>
<symbol name="BANK0_R2" address="INTMEM:02"/>
<symbol name="BANK0_R3" address="INTMEM:03"/>
<symbol name="BANK0_R4" address="INTMEM:04"/>
<symbol name="BANK0_R5" address="INTMEM:05"/>
<symbol name="BANK0_R6" address="INTMEM:06"/>
<symbol name="BANK0_R7" address="INTMEM:07"/>
<symbol name="BANK1_R0" address="INTMEM:18"/>
<symbol name="BANK1_R1" address="INTMEM:19"/>
<symbol name="BANK1_R2" address="INTMEM:1a"/>
<symbol name="BANK1_R3" address="INTMEM:1b"/>
<symbol name="BANK1_R4" address="INTMEM:1c"/>
<symbol name="BANK1_R5" address="INTMEM:1d"/>
<symbol name="BANK1_R6" address="INTMEM:1e"/>
<symbol name="BANK1_R7" address="INTMEM:1f"/>
<symbol name="BUS" address="PORT:0"/>
<symbol name="P1" address="PORT:1"/>
<symbol name="P2" address="PORT:2"/>
<symbol name="P4" address="PORT:4"/>
<symbol name="P5" address="PORT:5"/>
<symbol name="P6" address="PORT:6"/>
<symbol name="P7" address="PORT:7"/>
<symbol name="RESET" address="CODE:0" entry="true"/>
<symbol name="EXTIRQ" address="CODE:3" entry="true"/>
<symbol name="TIMIRQ" address="CODE:7" entry="true"/>
</default_symbols>
<default_memory_blocks>
<memory_block name="REG_BANK_0" start_address="INTMEM:0" length="0x8" initialized="false"/>
<memory_block name="STACK" start_address="INTMEM:8" length="0x10" initialized="false"/>
<memory_block name="REG_BANK_1" start_address="INTMEM:18" length="0x8" initialized="false"/>
<memory_block name="INTMEM" start_address="INTMEM:20" length="0xe0" initialized="false"/>
<memory_block name="PORT" start_address="PORT:0" length="0x8" initialized="false"/>
</default_memory_blocks>
</processor_spec>