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ghidra/Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc

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# C7.2.1 ABS page C7-1009 line 58362 KEEPWITH
#
# The semantics in this file are auto-generated with armit.py script
# in the andre directory (capture output and replace file):
#
# python ../../../ProcessorTest/test/andre/scrape/armit.py --arch a64 --sort --refurb --smacro primitive --sinc languages/AARCH64neon.sinc
#
# The AUNIT tests are run using the command line options from the
# comment with the python script aunit.py in the cunit directory:
#
# (cd ../../../ProcessorTest/test/cunit; python aunit.py OPTIONS)
#
# (aunit.py may require a local copy of a current andre exhaust).
# C7.2.1 ABS page C7-1399 line 77427 MATCH x5e20b800/mask=xff3ffc00
# CONSTRUCT x5ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =abs
# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1
# AUNIT --inst x5ee0b800/mask=xfffffc00 --status pass
# ABS Scalar
:abs Rd_FPR64, Rn_FPR64
is b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000101110 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = MP_INT_ABS(Rn_FPR64);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.1 ABS page C7-1399 line 77427 MATCH x0e20b800/mask=xbf3ffc00
# CONSTRUCT x0e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@1
# AUNIT --inst x0e20b800/mask=xfffffc00 --status pass
# ABS Vector 8B when size = 00 , Q = 0
:abs Rd_VPR64.8B, Rn_VPR64.8B
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000101110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
{
# simd unary Rd_VPR64.8B = MP_INT_ABS(Rn_VPR64.8B) on lane size 1
Rd_VPR64.8B[0,8] = MP_INT_ABS(Rn_VPR64.8B[0,8]);
Rd_VPR64.8B[8,8] = MP_INT_ABS(Rn_VPR64.8B[8,8]);
Rd_VPR64.8B[16,8] = MP_INT_ABS(Rn_VPR64.8B[16,8]);
Rd_VPR64.8B[24,8] = MP_INT_ABS(Rn_VPR64.8B[24,8]);
Rd_VPR64.8B[32,8] = MP_INT_ABS(Rn_VPR64.8B[32,8]);
Rd_VPR64.8B[40,8] = MP_INT_ABS(Rn_VPR64.8B[40,8]);
Rd_VPR64.8B[48,8] = MP_INT_ABS(Rn_VPR64.8B[48,8]);
Rd_VPR64.8B[56,8] = MP_INT_ABS(Rn_VPR64.8B[56,8]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.1 ABS page C7-1399 line 77427 MATCH x0e20b800/mask=xbf3ffc00
# CONSTRUCT x4e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@1
# AUNIT --inst x4e20b800/mask=xfffffc00 --status pass
# ABS Vector SIMD 16B when size = 00 , Q = 1
:abs Rd_VPR128.16B, Rn_VPR128.16B
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000101110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
{
# simd unary Rd_VPR128.16B = MP_INT_ABS(Rn_VPR128.16B) on lane size 1
Rd_VPR128.16B[0,8] = MP_INT_ABS(Rn_VPR128.16B[0,8]);
Rd_VPR128.16B[8,8] = MP_INT_ABS(Rn_VPR128.16B[8,8]);
Rd_VPR128.16B[16,8] = MP_INT_ABS(Rn_VPR128.16B[16,8]);
Rd_VPR128.16B[24,8] = MP_INT_ABS(Rn_VPR128.16B[24,8]);
Rd_VPR128.16B[32,8] = MP_INT_ABS(Rn_VPR128.16B[32,8]);
Rd_VPR128.16B[40,8] = MP_INT_ABS(Rn_VPR128.16B[40,8]);
Rd_VPR128.16B[48,8] = MP_INT_ABS(Rn_VPR128.16B[48,8]);
Rd_VPR128.16B[56,8] = MP_INT_ABS(Rn_VPR128.16B[56,8]);
Rd_VPR128.16B[64,8] = MP_INT_ABS(Rn_VPR128.16B[64,8]);
Rd_VPR128.16B[72,8] = MP_INT_ABS(Rn_VPR128.16B[72,8]);
Rd_VPR128.16B[80,8] = MP_INT_ABS(Rn_VPR128.16B[80,8]);
Rd_VPR128.16B[88,8] = MP_INT_ABS(Rn_VPR128.16B[88,8]);
Rd_VPR128.16B[96,8] = MP_INT_ABS(Rn_VPR128.16B[96,8]);
Rd_VPR128.16B[104,8] = MP_INT_ABS(Rn_VPR128.16B[104,8]);
Rd_VPR128.16B[112,8] = MP_INT_ABS(Rn_VPR128.16B[112,8]);
Rd_VPR128.16B[120,8] = MP_INT_ABS(Rn_VPR128.16B[120,8]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.1 ABS page C7-1399 line 77427 MATCH x0e20b800/mask=xbf3ffc00
# CONSTRUCT x0e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@2
# AUNIT --inst x0e60b800/mask=xfffffc00 --status pass
# ABS Vector SIMD 4H when size = 01 , Q = 0
:abs Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000101110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
# simd unary Rd_VPR64.4H = MP_INT_ABS(Rn_VPR64.4H) on lane size 2
Rd_VPR64.4H[0,16] = MP_INT_ABS(Rn_VPR64.4H[0,16]);
Rd_VPR64.4H[16,16] = MP_INT_ABS(Rn_VPR64.4H[16,16]);
Rd_VPR64.4H[32,16] = MP_INT_ABS(Rn_VPR64.4H[32,16]);
Rd_VPR64.4H[48,16] = MP_INT_ABS(Rn_VPR64.4H[48,16]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.1 ABS page C7-1399 line 77427 MATCH x0e20b800/mask=xbf3ffc00
# CONSTRUCT x4e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@2
# AUNIT --inst x4e60b800/mask=xfffffc00 --status pass
# ABS Vector SIMD 8H when size = 01 , Q = 1
:abs Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000101110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
# simd unary Rd_VPR128.8H = MP_INT_ABS(Rn_VPR128.8H) on lane size 2
Rd_VPR128.8H[0,16] = MP_INT_ABS(Rn_VPR128.8H[0,16]);
Rd_VPR128.8H[16,16] = MP_INT_ABS(Rn_VPR128.8H[16,16]);
Rd_VPR128.8H[32,16] = MP_INT_ABS(Rn_VPR128.8H[32,16]);
Rd_VPR128.8H[48,16] = MP_INT_ABS(Rn_VPR128.8H[48,16]);
Rd_VPR128.8H[64,16] = MP_INT_ABS(Rn_VPR128.8H[64,16]);
Rd_VPR128.8H[80,16] = MP_INT_ABS(Rn_VPR128.8H[80,16]);
Rd_VPR128.8H[96,16] = MP_INT_ABS(Rn_VPR128.8H[96,16]);
Rd_VPR128.8H[112,16] = MP_INT_ABS(Rn_VPR128.8H[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.1 ABS page C7-1399 line 77427 MATCH x0e20b800/mask=xbf3ffc00
# CONSTRUCT x0ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@4
# AUNIT --inst x0ea0b800/mask=xfffffc00 --status pass
# ABS Vector SIMD 2S when size = 10 , Q = 0
:abs Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000101110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
# simd unary Rd_VPR64.2S = MP_INT_ABS(Rn_VPR64.2S) on lane size 4
Rd_VPR64.2S[0,32] = MP_INT_ABS(Rn_VPR64.2S[0,32]);
Rd_VPR64.2S[32,32] = MP_INT_ABS(Rn_VPR64.2S[32,32]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.1 ABS page C7-1399 line 77427 MATCH x0e20b800/mask=xbf3ffc00
# CONSTRUCT x4ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@4
# AUNIT --inst x4ea0b800/mask=xfffffc00 --status pass
# ABS Vector SIMD 4S when size = 10 , Q = 1
:abs Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000101110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
# simd unary Rd_VPR128.4S = MP_INT_ABS(Rn_VPR128.4S) on lane size 4
Rd_VPR128.4S[0,32] = MP_INT_ABS(Rn_VPR128.4S[0,32]);
Rd_VPR128.4S[32,32] = MP_INT_ABS(Rn_VPR128.4S[32,32]);
Rd_VPR128.4S[64,32] = MP_INT_ABS(Rn_VPR128.4S[64,32]);
Rd_VPR128.4S[96,32] = MP_INT_ABS(Rn_VPR128.4S[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.1 ABS page C7-1399 line 77427 MATCH x0e20b800/mask=xbf3ffc00
# CONSTRUCT x4ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@8
# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@8
# AUNIT --inst x4ee0b800/mask=xfffffc00 --status pass
# ABS Vector SIMD 2D when size = 11 , Q = 1
:abs Rd_VPR128.2D, Rn_VPR128.2D
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b11 & b_1021=0b100000101110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
{
# simd unary Rd_VPR128.2D = MP_INT_ABS(Rn_VPR128.2D) on lane size 8
Rd_VPR128.2D[0,64] = MP_INT_ABS(Rn_VPR128.2D[0,64]);
Rd_VPR128.2D[64,64] = MP_INT_ABS(Rn_VPR128.2D[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.2 ADD (vector) page C7-1401 line 77555 MATCH x5e208400/mask=xff20fc00
# CONSTRUCT x5ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =+
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2
# AUNIT --inst x5ee08400/mask=xffe0fc00 --status pass
:add Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x10 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = Rn_FPR64 + Rm_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.2 ADD (vector) page C7-1401 line 77555 MATCH x0e208400/mask=xbf20fc00
# CONSTRUCT x4e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$+@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@1
# AUNIT --inst x4e208400/mask=xffe0fc00 --status pass
:add Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x10 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix Rd_VPR128.16B = Rn_VPR128.16B + Rm_VPR128.16B on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] + Rm_VPR128.16B[0,8];
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] + Rm_VPR128.16B[8,8];
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] + Rm_VPR128.16B[16,8];
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] + Rm_VPR128.16B[24,8];
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] + Rm_VPR128.16B[32,8];
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] + Rm_VPR128.16B[40,8];
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] + Rm_VPR128.16B[48,8];
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] + Rm_VPR128.16B[56,8];
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] + Rm_VPR128.16B[64,8];
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] + Rm_VPR128.16B[72,8];
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] + Rm_VPR128.16B[80,8];
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] + Rm_VPR128.16B[88,8];
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] + Rm_VPR128.16B[96,8];
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] + Rm_VPR128.16B[104,8];
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] + Rm_VPR128.16B[112,8];
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] + Rm_VPR128.16B[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.2 ADD (vector) page C7-1401 line 77555 MATCH x0e208400/mask=xbf20fc00
# CONSTRUCT x4e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@2
# AUNIT --inst x4e608400/mask=xffe0fc00 --status pass
:add Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd infix Rd_VPR128.8H = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.2 ADD (vector) page C7-1401 line 77555 MATCH x0e208400/mask=xbf20fc00
# CONSTRUCT x4ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@4
# AUNIT --inst x4ea08400/mask=xffe0fc00 --status pass
:add Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd infix Rd_VPR128.4S = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.2 ADD (vector) page C7-1401 line 77555 MATCH x0e208400/mask=xbf20fc00
# CONSTRUCT x4ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@8
# AUNIT --inst x4ee08400/mask=xffe0fc00 --status pass
:add Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd infix Rd_VPR128.2D = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.2 ADD (vector) page C7-1401 line 77555 MATCH x0e208400/mask=xbf20fc00
# CONSTRUCT x0e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$+@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@1
# AUNIT --inst x0e208400/mask=xffe0fc00 --status pass
:add Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x10 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix Rd_VPR64.8B = Rn_VPR64.8B + Rm_VPR64.8B on lane size 1
Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] + Rm_VPR64.8B[0,8];
Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] + Rm_VPR64.8B[8,8];
Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] + Rm_VPR64.8B[16,8];
Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] + Rm_VPR64.8B[24,8];
Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] + Rm_VPR64.8B[32,8];
Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] + Rm_VPR64.8B[40,8];
Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] + Rm_VPR64.8B[48,8];
Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] + Rm_VPR64.8B[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.2 ADD (vector) page C7-1401 line 77555 MATCH x0e208400/mask=xbf20fc00
# CONSTRUCT x0e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@2
# AUNIT --inst x0e608400/mask=xffe0fc00 --status pass
:add Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x10 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd infix Rd_VPR64.4H = Rn_VPR64.4H + Rm_VPR64.4H on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] + Rm_VPR64.4H[0,16];
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] + Rm_VPR64.4H[16,16];
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] + Rm_VPR64.4H[32,16];
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] + Rm_VPR64.4H[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.2 ADD (vector) page C7-1401 line 77555 MATCH x0e208400/mask=xbf20fc00
# CONSTRUCT x0ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@4
# AUNIT --inst x0ea08400/mask=xffe0fc00 --status pass
:add Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x10 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix Rd_VPR64.2S = Rn_VPR64.2S + Rm_VPR64.2S on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] + Rm_VPR64.2S[0,32];
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] + Rm_VPR64.2S[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.3 ADDHN, ADDHN2 page C7-1403 line 77689 MATCH x0e204000/mask=xbf20fc00
# CONSTRUCT x0ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $+@8 &=$shuffle@1-0@3-1:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn/3@8
# AUNIT --inst x0ea04000/mask=xffe0fc00 --status pass
:addhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Rd_VPR128 & Zd
{
# simd infix TMPQ1 = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64];
TMPQ1[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64];
# simd shuffle Rd_VPR64.2S = TMPQ1 (@1-0@3-1) lane size 4
Rd_VPR64.2S[0,32] = TMPQ1[32,32];
Rd_VPR64.2S[32,32] = TMPQ1[96,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.3 ADDHN, ADDHN2 page C7-1403 line 77689 MATCH x0e204000/mask=xbf20fc00
# CONSTRUCT x0e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $+@4 &=$shuffle@1-0@3-1@5-2@7-3:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn/3@4
# AUNIT --inst x0e604000/mask=xffe0fc00 --status pass
:addhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Rd_VPR128 & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32];
TMPQ1[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32];
TMPQ1[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32];
TMPQ1[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32];
# simd shuffle Rd_VPR64.4H = TMPQ1 (@1-0@3-1@5-2@7-3) lane size 2
Rd_VPR64.4H[0,16] = TMPQ1[16,16];
Rd_VPR64.4H[16,16] = TMPQ1[48,16];
Rd_VPR64.4H[32,16] = TMPQ1[80,16];
Rd_VPR64.4H[48,16] = TMPQ1[112,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.3 ADDHN, ADDHN2 page C7-1403 line 77689 MATCH x0e204000/mask=xbf20fc00
# CONSTRUCT x0e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $+@2 &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn/3@2
# AUNIT --inst x0e204000/mask=xffe0fc00 --status pass
:addhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Rd_VPR128 & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16];
TMPQ1[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16];
TMPQ1[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16];
TMPQ1[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16];
TMPQ1[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16];
TMPQ1[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16];
TMPQ1[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16];
TMPQ1[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16];
# simd shuffle Rd_VPR64.8B = TMPQ1 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 1
Rd_VPR64.8B[0,8] = TMPQ1[8,8];
Rd_VPR64.8B[8,8] = TMPQ1[24,8];
Rd_VPR64.8B[16,8] = TMPQ1[40,8];
Rd_VPR64.8B[24,8] = TMPQ1[56,8];
Rd_VPR64.8B[32,8] = TMPQ1[72,8];
Rd_VPR64.8B[40,8] = TMPQ1[88,8];
Rd_VPR64.8B[48,8] = TMPQ1[104,8];
Rd_VPR64.8B[56,8] = TMPQ1[120,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.3 ADDHN, ADDHN2 page C7-1403 line 77689 MATCH x0e204000/mask=xbf20fc00
# CONSTRUCT x4e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $+@2 &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn2/3@2
# AUNIT --inst x4e204000/mask=xffe0fc00 --status pass
:addhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Rd_VPR128 & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16];
TMPQ1[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16];
TMPQ1[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16];
TMPQ1[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16];
TMPQ1[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16];
TMPQ1[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16];
TMPQ1[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16];
TMPQ1[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16];
# simd shuffle Rd_VPR128.16B = TMPQ1 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1
Rd_VPR128.16B[64,8] = TMPQ1[8,8];
Rd_VPR128.16B[72,8] = TMPQ1[24,8];
Rd_VPR128.16B[80,8] = TMPQ1[40,8];
Rd_VPR128.16B[88,8] = TMPQ1[56,8];
Rd_VPR128.16B[96,8] = TMPQ1[72,8];
Rd_VPR128.16B[104,8] = TMPQ1[88,8];
Rd_VPR128.16B[112,8] = TMPQ1[104,8];
Rd_VPR128.16B[120,8] = TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.3 ADDHN, ADDHN2 page C7-1403 line 77689 MATCH x0e204000/mask=xbf20fc00
# CONSTRUCT x4ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $+@8 &=$shuffle@1-2@3-3:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn2/3@8
# AUNIT --inst x4ea04000/mask=xffe0fc00 --status pass
:addhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Rd_VPR128 & Zd
{
# simd infix TMPQ1 = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64];
TMPQ1[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64];
# simd shuffle Rd_VPR128.4S = TMPQ1 (@1-2@3-3) lane size 4
Rd_VPR128.4S[64,32] = TMPQ1[32,32];
Rd_VPR128.4S[96,32] = TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.3 ADDHN, ADDHN2 page C7-1403 line 77689 MATCH x0e204000/mask=xbf20fc00
# CONSTRUCT x4e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $+@4 &=$shuffle@1-4@3-5@5-6@7-7:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn2/3@4
# AUNIT --inst x4e604000/mask=xffe0fc00 --status pass
:addhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Rd_VPR128 & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32];
TMPQ1[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32];
TMPQ1[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32];
TMPQ1[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32];
# simd shuffle Rd_VPR128.8H = TMPQ1 (@1-4@3-5@5-6@7-7) lane size 2
Rd_VPR128.8H[64,16] = TMPQ1[16,16];
Rd_VPR128.8H[80,16] = TMPQ1[48,16];
Rd_VPR128.8H[96,16] = TMPQ1[80,16];
Rd_VPR128.8H[112,16] = TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.4 ADDP (scalar) page C7-1405 line 77812 MATCH x5e31b800/mask=xff3ffc00
# CONSTRUCT x5ef1b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =#+
# SMACRO(pseudo) ARG1 ARG2 =NEON_addp/1@8
# AUNIT --inst x5ef1b800/mask=xfffffc00 --status pass
:addp Rd_FPR64, Rn_VPR128.2D
is b_3031=1 & u=0 & b_2428=0x1e & b_23=1 & b_1722=0x38 & b_1216=0x1b & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd
{
# sipd infix Rd_FPR64 = +(Rn_VPR128.2D) on pairs lane size (8 to 8)
tmp1 = Rn_VPR128.2D[0,64];
tmp2 = Rn_VPR128.2D[64,64];
Rd_FPR64[0,64] = tmp1 + tmp2;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.5 ADDP (vector) page C7-1407 line 77897 MATCH x0e20bc00/mask=xbf20fc00
# CONSTRUCT x4e20bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@1
# AUNIT --inst x4e20bc00/mask=xffe0fc00 --status pass
:addp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x17 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = +(Rn_VPR128.16B,Rm_VPR128.16B) on pairs lane size (1 to 1)
tmp2 = Rn_VPR128.16B[0,8];
tmp3 = Rn_VPR128.16B[8,8];
TMPQ1[0,8] = tmp2 + tmp3;
tmp2 = Rn_VPR128.16B[16,8];
tmp3 = Rn_VPR128.16B[24,8];
TMPQ1[8,8] = tmp2 + tmp3;
tmp2 = Rn_VPR128.16B[32,8];
tmp3 = Rn_VPR128.16B[40,8];
TMPQ1[16,8] = tmp2 + tmp3;
tmp2 = Rn_VPR128.16B[48,8];
tmp3 = Rn_VPR128.16B[56,8];
TMPQ1[24,8] = tmp2 + tmp3;
tmp2 = Rn_VPR128.16B[64,8];
tmp3 = Rn_VPR128.16B[72,8];
TMPQ1[32,8] = tmp2 + tmp3;
tmp2 = Rn_VPR128.16B[80,8];
tmp3 = Rn_VPR128.16B[88,8];
TMPQ1[40,8] = tmp2 + tmp3;
tmp2 = Rn_VPR128.16B[96,8];
tmp3 = Rn_VPR128.16B[104,8];
TMPQ1[48,8] = tmp2 + tmp3;
tmp2 = Rn_VPR128.16B[112,8];
tmp3 = Rn_VPR128.16B[120,8];
TMPQ1[56,8] = tmp2 + tmp3;
tmp2 = Rm_VPR128.16B[0,8];
tmp3 = Rm_VPR128.16B[8,8];
TMPQ1[64,8] = tmp2 + tmp3;
tmp2 = Rm_VPR128.16B[16,8];
tmp3 = Rm_VPR128.16B[24,8];
TMPQ1[72,8] = tmp2 + tmp3;
tmp2 = Rm_VPR128.16B[32,8];
tmp3 = Rm_VPR128.16B[40,8];
TMPQ1[80,8] = tmp2 + tmp3;
tmp2 = Rm_VPR128.16B[48,8];
tmp3 = Rm_VPR128.16B[56,8];
TMPQ1[88,8] = tmp2 + tmp3;
tmp2 = Rm_VPR128.16B[64,8];
tmp3 = Rm_VPR128.16B[72,8];
TMPQ1[96,8] = tmp2 + tmp3;
tmp2 = Rm_VPR128.16B[80,8];
tmp3 = Rm_VPR128.16B[88,8];
TMPQ1[104,8] = tmp2 + tmp3;
tmp2 = Rm_VPR128.16B[96,8];
tmp3 = Rm_VPR128.16B[104,8];
TMPQ1[112,8] = tmp2 + tmp3;
tmp2 = Rm_VPR128.16B[112,8];
tmp3 = Rm_VPR128.16B[120,8];
TMPQ1[120,8] = tmp2 + tmp3;
Rd_VPR128.16B = TMPQ1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.5 ADDP (vector) page C7-1407 line 77897 MATCH x0e20bc00/mask=xbf20fc00
# CONSTRUCT x4ee0bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@8
# AUNIT --inst x4ee0bc00/mask=xffe0fc00 --status pass
:addp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x17 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = +(Rn_VPR128.2D,Rm_VPR128.2D) on pairs lane size (8 to 8)
tmp2 = Rn_VPR128.2D[0,64];
tmp3 = Rn_VPR128.2D[64,64];
TMPQ1[0,64] = tmp2 + tmp3;
tmp2 = Rm_VPR128.2D[0,64];
tmp3 = Rm_VPR128.2D[64,64];
TMPQ1[64,64] = tmp2 + tmp3;
Rd_VPR128.2D = TMPQ1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.5 ADDP (vector) page C7-1407 line 77897 MATCH x0e20bc00/mask=xbf20fc00
# CONSTRUCT x0ea0bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:8 ARG2 ARG3 =#+/2 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@4
# AUNIT --inst x0ea0bc00/mask=xffe0fc00 --status pass
:addp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x17 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
TMPD1 = 0;
# sipd infix TMPD1 = +(Rn_VPR64.2S,Rm_VPR64.2S) on pairs lane size (4 to 4)
tmp2 = Rn_VPR64.2S[0,32];
tmp3 = Rn_VPR64.2S[32,32];
TMPD1[0,32] = tmp2 + tmp3;
tmp2 = Rm_VPR64.2S[0,32];
tmp3 = Rm_VPR64.2S[32,32];
TMPD1[32,32] = tmp2 + tmp3;
Rd_VPR64.2S = TMPD1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.5 ADDP (vector) page C7-1407 line 77897 MATCH x0e20bc00/mask=xbf20fc00
# CONSTRUCT x0e60bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:8 ARG2 ARG3 =#+/2 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@2
# AUNIT --inst x0e60bc00/mask=xffe0fc00 --status pass
:addp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x17 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
TMPD1 = 0;
# sipd infix TMPD1 = +(Rn_VPR64.4H,Rm_VPR64.4H) on pairs lane size (2 to 2)
tmp2 = Rn_VPR64.4H[0,16];
tmp3 = Rn_VPR64.4H[16,16];
TMPD1[0,16] = tmp2 + tmp3;
tmp2 = Rn_VPR64.4H[32,16];
tmp3 = Rn_VPR64.4H[48,16];
TMPD1[16,16] = tmp2 + tmp3;
tmp2 = Rm_VPR64.4H[0,16];
tmp3 = Rm_VPR64.4H[16,16];
TMPD1[32,16] = tmp2 + tmp3;
tmp2 = Rm_VPR64.4H[32,16];
tmp3 = Rm_VPR64.4H[48,16];
TMPD1[48,16] = tmp2 + tmp3;
Rd_VPR64.4H = TMPD1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.5 ADDP (vector) page C7-1407 line 77897 MATCH x0e20bc00/mask=xbf20fc00
# CONSTRUCT x4ea0bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@4
# AUNIT --inst x4ea0bc00/mask=xffe0fc00 --status pass
:addp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x17 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = +(Rn_VPR128.4S,Rm_VPR128.4S) on pairs lane size (4 to 4)
tmp2 = Rn_VPR128.4S[0,32];
tmp3 = Rn_VPR128.4S[32,32];
TMPQ1[0,32] = tmp2 + tmp3;
tmp2 = Rn_VPR128.4S[64,32];
tmp3 = Rn_VPR128.4S[96,32];
TMPQ1[32,32] = tmp2 + tmp3;
tmp2 = Rm_VPR128.4S[0,32];
tmp3 = Rm_VPR128.4S[32,32];
TMPQ1[64,32] = tmp2 + tmp3;
tmp2 = Rm_VPR128.4S[64,32];
tmp3 = Rm_VPR128.4S[96,32];
TMPQ1[96,32] = tmp2 + tmp3;
Rd_VPR128.4S = TMPQ1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.5 ADDP (vector) page C7-1407 line 77897 MATCH x0e20bc00/mask=xbf20fc00
# CONSTRUCT x0e20bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:8 ARG2 ARG3 =#+/2 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@1
# AUNIT --inst x0e20bc00/mask=xffe0fc00 --status pass
:addp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x17 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
TMPD1 = 0;
# sipd infix TMPD1 = +(Rn_VPR64.8B,Rm_VPR64.8B) on pairs lane size (1 to 1)
tmp2 = Rn_VPR64.8B[0,8];
tmp3 = Rn_VPR64.8B[8,8];
TMPD1[0,8] = tmp2 + tmp3;
tmp2 = Rn_VPR64.8B[16,8];
tmp3 = Rn_VPR64.8B[24,8];
TMPD1[8,8] = tmp2 + tmp3;
tmp2 = Rn_VPR64.8B[32,8];
tmp3 = Rn_VPR64.8B[40,8];
TMPD1[16,8] = tmp2 + tmp3;
tmp2 = Rn_VPR64.8B[48,8];
tmp3 = Rn_VPR64.8B[56,8];
TMPD1[24,8] = tmp2 + tmp3;
tmp2 = Rm_VPR64.8B[0,8];
tmp3 = Rm_VPR64.8B[8,8];
TMPD1[32,8] = tmp2 + tmp3;
tmp2 = Rm_VPR64.8B[16,8];
tmp3 = Rm_VPR64.8B[24,8];
TMPD1[40,8] = tmp2 + tmp3;
tmp2 = Rm_VPR64.8B[32,8];
tmp3 = Rm_VPR64.8B[40,8];
TMPD1[48,8] = tmp2 + tmp3;
tmp2 = Rm_VPR64.8B[48,8];
tmp3 = Rm_VPR64.8B[56,8];
TMPD1[56,8] = tmp2 + tmp3;
Rd_VPR64.8B = TMPD1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.5 ADDP (vector) page C7-1407 line 77897 MATCH x0e20bc00/mask=xbf20fc00
# CONSTRUCT x4e60bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@2
# AUNIT --inst x4e60bc00/mask=xffe0fc00 --status pass
:addp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x17 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = +(Rn_VPR128.8H,Rm_VPR128.8H) on pairs lane size (2 to 2)
tmp2 = Rn_VPR128.8H[0,16];
tmp3 = Rn_VPR128.8H[16,16];
TMPQ1[0,16] = tmp2 + tmp3;
tmp2 = Rn_VPR128.8H[32,16];
tmp3 = Rn_VPR128.8H[48,16];
TMPQ1[16,16] = tmp2 + tmp3;
tmp2 = Rn_VPR128.8H[64,16];
tmp3 = Rn_VPR128.8H[80,16];
TMPQ1[32,16] = tmp2 + tmp3;
tmp2 = Rn_VPR128.8H[96,16];
tmp3 = Rn_VPR128.8H[112,16];
TMPQ1[48,16] = tmp2 + tmp3;
tmp2 = Rm_VPR128.8H[0,16];
tmp3 = Rm_VPR128.8H[16,16];
TMPQ1[64,16] = tmp2 + tmp3;
tmp2 = Rm_VPR128.8H[32,16];
tmp3 = Rm_VPR128.8H[48,16];
TMPQ1[80,16] = tmp2 + tmp3;
tmp2 = Rm_VPR128.8H[64,16];
tmp3 = Rm_VPR128.8H[80,16];
TMPQ1[96,16] = tmp2 + tmp3;
tmp2 = Rm_VPR128.8H[96,16];
tmp3 = Rm_VPR128.8H[112,16];
TMPQ1[112,16] = tmp2 + tmp3;
Rd_VPR128.8H = TMPQ1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.6 ADDV page C7-1409 line 77996 MATCH x0e31b800/mask=xbf3ffc00
# CONSTRUCT x4e31b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@1
# AUNIT --inst x4e31b800/mask=xfffffc00 --status nopcodeop
:addv Rd_FPR8, Rn_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_addv(Rn_VPR128.16B, 1:1);
}
# C7.2.6 ADDV page C7-1409 line 77996 MATCH x0e31b800/mask=xbf3ffc00
# CONSTRUCT x0e31b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@1
# AUNIT --inst x0e31b800/mask=xfffffc00 --status nopcodeop
:addv Rd_FPR8, Rn_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_addv(Rn_VPR64.8B, 1:1);
}
# C7.2.6 ADDV page C7-1409 line 77996 MATCH x0e31b800/mask=xbf3ffc00
# CONSTRUCT x0e71b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@2
# AUNIT --inst x0e71b800/mask=xfffffc00 --status nopcodeop
:addv Rd_FPR16, Rn_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_addv(Rn_VPR64.4H, 2:1);
}
# C7.2.6 ADDV page C7-1409 line 77996 MATCH x0e31b800/mask=xbf3ffc00
# CONSTRUCT x4e71b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@2
# AUNIT --inst x4e71b800/mask=xfffffc00 --status nopcodeop
:addv Rd_FPR16, Rn_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_addv(Rn_VPR128.8H, 2:1);
}
# C7.2.6 ADDV page C7-1409 line 77996 MATCH x0e31b800/mask=xbf3ffc00
# CONSTRUCT x4eb1b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(force-primitive) ARG1 ARG2[0]:4 ARG2[1]:4 + ARG2[2]:4 ARG2[3]:4 + =+
# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@4
# AUNIT --inst x4eb1b800/mask=xfffffc00 --status pass
:addv Rd_FPR32, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
{
local tmp1:4 = Rn_VPR128.4S[0,32];
local tmp2:4 = Rn_VPR128.4S[32,32];
local tmp3:4 = tmp1 + tmp2;
local tmp4:4 = Rn_VPR128.4S[64,32];
local tmp5:4 = Rn_VPR128.4S[96,32];
local tmp6:4 = tmp4 + tmp5;
Rd_FPR32 = tmp3 + tmp6;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.7 AESD page C7-1411 line 78085 MATCH x4e285800/mask=xfffffc00
# CONSTRUCT x4e285800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_aesd/2
# AUNIT --inst x4e285800/mask=xfffffc00 --status noqemu
:aesd Rd_VPR128.16B, Rn_VPR128.16B
is b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_aesd(Rd_VPR128.16B, Rn_VPR128.16B);
}
# C7.2.8 AESE page C7-1412 line 78145 MATCH x4e284800/mask=xfffffc00
# CONSTRUCT x4e284800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_aese/2
# AUNIT --inst x4e284800/mask=xfffffc00 --status noqemu
:aese Rd_VPR128.16B, Rn_VPR128.16B
is b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=4 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_aese(Rd_VPR128.16B, Rn_VPR128.16B);
}
# C7.2.9 AESIMC page C7-1413 line 78206 MATCH x4e287800/mask=xfffffc00
# CONSTRUCT x4e287800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_aesimc/2
# AUNIT --inst x4e287800/mask=xfffffc00 --status noqemu
:aesimc Rd_VPR128.16B, Rn_VPR128.16B
is b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=7 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Rd_VPR128 & Zd
{
Rd_VPR128.16B = NEON_aesimc(Rd_VPR128.16B, Rn_VPR128.16B);
}
# C7.2.10 AESMC page C7-1414 line 78264 MATCH x4e286800/mask=xfffffc00
# CONSTRUCT x4e286800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_aesmc/2
# AUNIT --inst x4e286800/mask=xfffffc00 --status noqemu
:aesmc Rd_VPR128.16B, Rn_VPR128.16B
is b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=6 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Rd_VPR128 & Zd
{
Rd_VPR128.16B = NEON_aesmc(Rd_VPR128.16B, Rn_VPR128.16B);
}
# C7.2.11 AND (vector) page C7-1415 line 78322 MATCH x0e201c00/mask=xbfe0fc00
# CONSTRUCT x4e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$&@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_and/2@1
# AUNIT --inst x4e201c00/mask=xffe0fc00 --status pass
:and Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix Rd_VPR128.16B = Rn_VPR128.16B & Rm_VPR128.16B on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] & Rm_VPR128.16B[0,8];
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] & Rm_VPR128.16B[8,8];
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] & Rm_VPR128.16B[16,8];
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] & Rm_VPR128.16B[24,8];
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] & Rm_VPR128.16B[32,8];
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] & Rm_VPR128.16B[40,8];
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] & Rm_VPR128.16B[48,8];
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] & Rm_VPR128.16B[56,8];
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] & Rm_VPR128.16B[64,8];
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] & Rm_VPR128.16B[72,8];
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] & Rm_VPR128.16B[80,8];
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] & Rm_VPR128.16B[88,8];
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] & Rm_VPR128.16B[96,8];
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] & Rm_VPR128.16B[104,8];
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] & Rm_VPR128.16B[112,8];
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] & Rm_VPR128.16B[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.11 AND (vector) page C7-1415 line 78322 MATCH x0e201c00/mask=xbfe0fc00
# CONSTRUCT x0e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =&
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_and/2@1
# AUNIT --inst x0e201c00/mask=xffe0fc00 --status pass
:and Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = Rn_VPR64.8B & Rm_VPR64.8B;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.12 BCAX page C7-1416 line 78391 MATCH xce200000/mask=xffe08000
# CONSTRUCT xce200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 ARG4 $~@1 $&@1 =$|@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG3 =NEON_bcax/3@1
# AUNIT --inst xce200000/mask=xffe08000 --status noqemu
:bcax Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, Ra_VPR128.16B
is b_2131=0b11001110001 & b_15=0 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Ra_VPR128.16B & Zd
{
# simd unary TMPQ1 = ~(Ra_VPR128.16B) on lane size 1
TMPQ1[0,8] = ~(Ra_VPR128.16B[0,8]);
TMPQ1[8,8] = ~(Ra_VPR128.16B[8,8]);
TMPQ1[16,8] = ~(Ra_VPR128.16B[16,8]);
TMPQ1[24,8] = ~(Ra_VPR128.16B[24,8]);
TMPQ1[32,8] = ~(Ra_VPR128.16B[32,8]);
TMPQ1[40,8] = ~(Ra_VPR128.16B[40,8]);
TMPQ1[48,8] = ~(Ra_VPR128.16B[48,8]);
TMPQ1[56,8] = ~(Ra_VPR128.16B[56,8]);
TMPQ1[64,8] = ~(Ra_VPR128.16B[64,8]);
TMPQ1[72,8] = ~(Ra_VPR128.16B[72,8]);
TMPQ1[80,8] = ~(Ra_VPR128.16B[80,8]);
TMPQ1[88,8] = ~(Ra_VPR128.16B[88,8]);
TMPQ1[96,8] = ~(Ra_VPR128.16B[96,8]);
TMPQ1[104,8] = ~(Ra_VPR128.16B[104,8]);
TMPQ1[112,8] = ~(Ra_VPR128.16B[112,8]);
TMPQ1[120,8] = ~(Ra_VPR128.16B[120,8]);
# simd infix TMPQ2 = Rm_VPR128.16B & TMPQ1 on lane size 1
TMPQ2[0,8] = Rm_VPR128.16B[0,8] & TMPQ1[0,8];
TMPQ2[8,8] = Rm_VPR128.16B[8,8] & TMPQ1[8,8];
TMPQ2[16,8] = Rm_VPR128.16B[16,8] & TMPQ1[16,8];
TMPQ2[24,8] = Rm_VPR128.16B[24,8] & TMPQ1[24,8];
TMPQ2[32,8] = Rm_VPR128.16B[32,8] & TMPQ1[32,8];
TMPQ2[40,8] = Rm_VPR128.16B[40,8] & TMPQ1[40,8];
TMPQ2[48,8] = Rm_VPR128.16B[48,8] & TMPQ1[48,8];
TMPQ2[56,8] = Rm_VPR128.16B[56,8] & TMPQ1[56,8];
TMPQ2[64,8] = Rm_VPR128.16B[64,8] & TMPQ1[64,8];
TMPQ2[72,8] = Rm_VPR128.16B[72,8] & TMPQ1[72,8];
TMPQ2[80,8] = Rm_VPR128.16B[80,8] & TMPQ1[80,8];
TMPQ2[88,8] = Rm_VPR128.16B[88,8] & TMPQ1[88,8];
TMPQ2[96,8] = Rm_VPR128.16B[96,8] & TMPQ1[96,8];
TMPQ2[104,8] = Rm_VPR128.16B[104,8] & TMPQ1[104,8];
TMPQ2[112,8] = Rm_VPR128.16B[112,8] & TMPQ1[112,8];
TMPQ2[120,8] = Rm_VPR128.16B[120,8] & TMPQ1[120,8];
# simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ2 on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ2[0,8];
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ2[8,8];
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ2[16,8];
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ2[24,8];
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ2[32,8];
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ2[40,8];
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ2[48,8];
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ2[56,8];
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ2[64,8];
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ2[72,8];
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ2[80,8];
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ2[88,8];
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ2[96,8];
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ2[104,8];
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ2[112,8];
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ2[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.20 BIC (vector, immediate) page C7-1428 line 79003 MATCH x2f001400/mask=xbff81c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# C7.2.258 SLI page C7-1963 line 110042 MATCH x2f005400/mask=xbf80fc00
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x2f007400/mask=xbf80fc00
# C7.2.387 URSRA page C7-2271 line 127788 MATCH x2f003400/mask=xbf80fc00
# C7.2.395 USRA page C7-2288 line 128723 MATCH x2f001400/mask=xbf80fc00
# CONSTRUCT x2f001400/mask=xfff89c00 MATCHED 7 DOCUMENTED OPCODES
# SMACRO ARG1 Imm_neon_uimm8Shift:4 ~ &=$&
# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:4 &=NEON_bic/2@4
# AUNIT --inst x2f001400/mask=xfff89c00 --status pass
:bic Rd_VPR64.2S, abcdefgh
is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & b_1515=0 & abcdefgh & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR64.2S & Zd
{
local tmp1:4 = ~ Imm_neon_uimm8Shift:4;
# simd infix Rd_VPR64.2S = Rd_VPR64.2S & tmp1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] & tmp1;
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] & tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.20 BIC (vector, immediate) page C7-1428 line 79003 MATCH x2f001400/mask=xbff81c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# C7.2.379 UQSHRN, UQSHRN2 page C7-2255 line 126838 MATCH x2f009400/mask=xbf80fc00
# CONSTRUCT x2f009400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES
# SMACRO ARG1 Imm_neon_uimm8Shift:2 ~ &=$&
# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:2 &=NEON_bic/2@2
# AUNIT --inst x2f009400/mask=xfff8dc00 --status pass
:bic Rd_VPR64.4H, abcdefgh
is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & abcdefgh & b_1923=0x0 & b_1415=2 & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR64.4H & Zd
{
local tmp1:2 = ~ Imm_neon_uimm8Shift:2;
# simd infix Rd_VPR64.4H = Rd_VPR64.4H & tmp1 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] & tmp1;
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] & tmp1;
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] & tmp1;
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] & tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.20 BIC (vector, immediate) page C7-1428 line 79003 MATCH x2f001400/mask=xbff81c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# C7.2.258 SLI page C7-1963 line 110042 MATCH x2f005400/mask=xbf80fc00
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x2f007400/mask=xbf80fc00
# C7.2.387 URSRA page C7-2271 line 127788 MATCH x2f003400/mask=xbf80fc00
# C7.2.395 USRA page C7-2288 line 128723 MATCH x2f001400/mask=xbf80fc00
# CONSTRUCT x6f001400/mask=xfff89c00 MATCHED 7 DOCUMENTED OPCODES
# SMACRO ARG1 Imm_neon_uimm8Shift:4 ~ &=$&
# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:4 &=NEON_bic/2@4
# AUNIT --inst x6f001400/mask=xfff89c00 --status pass
:bic Rd_VPR128.4S, abcdefgh
is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & b_1515=0 & abcdefgh & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR128.4S & Zd
{
local tmp1:4 = ~ Imm_neon_uimm8Shift:4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S & tmp1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] & tmp1;
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] & tmp1;
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] & tmp1;
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] & tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.20 BIC (vector, immediate) page C7-1428 line 79003 MATCH x2f001400/mask=xbff81c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# C7.2.379 UQSHRN, UQSHRN2 page C7-2255 line 126838 MATCH x2f009400/mask=xbf80fc00
# CONSTRUCT x6f009400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES
# SMACRO ARG1 Imm_neon_uimm8Shift:2 ~ &=$&
# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:2 &=NEON_bic/2@2
# AUNIT --inst x6f009400/mask=xfff8dc00 --status pass
:bic Rd_VPR128.8H, abcdefgh
is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & abcdefgh & b_1415=2 & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR128.8H & Zd
{
local tmp1:2 = ~ Imm_neon_uimm8Shift:2;
# simd infix Rd_VPR128.8H = Rd_VPR128.8H & tmp1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] & tmp1;
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] & tmp1;
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] & tmp1;
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] & tmp1;
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] & tmp1;
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] & tmp1;
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] & tmp1;
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] & tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.21 BIC (vector, register) page C7-1430 line 79136 MATCH x0e601c00/mask=xbfe0fc00
# CONSTRUCT x4e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $~@1 =$&@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_bic/2@1
# AUNIT --inst x4e601c00/mask=xffe0fc00 --status pass
:bic Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd unary TMPQ1 = ~(Rm_VPR128.16B) on lane size 1
TMPQ1[0,8] = ~(Rm_VPR128.16B[0,8]);
TMPQ1[8,8] = ~(Rm_VPR128.16B[8,8]);
TMPQ1[16,8] = ~(Rm_VPR128.16B[16,8]);
TMPQ1[24,8] = ~(Rm_VPR128.16B[24,8]);
TMPQ1[32,8] = ~(Rm_VPR128.16B[32,8]);
TMPQ1[40,8] = ~(Rm_VPR128.16B[40,8]);
TMPQ1[48,8] = ~(Rm_VPR128.16B[48,8]);
TMPQ1[56,8] = ~(Rm_VPR128.16B[56,8]);
TMPQ1[64,8] = ~(Rm_VPR128.16B[64,8]);
TMPQ1[72,8] = ~(Rm_VPR128.16B[72,8]);
TMPQ1[80,8] = ~(Rm_VPR128.16B[80,8]);
TMPQ1[88,8] = ~(Rm_VPR128.16B[88,8]);
TMPQ1[96,8] = ~(Rm_VPR128.16B[96,8]);
TMPQ1[104,8] = ~(Rm_VPR128.16B[104,8]);
TMPQ1[112,8] = ~(Rm_VPR128.16B[112,8]);
TMPQ1[120,8] = ~(Rm_VPR128.16B[120,8]);
# simd infix Rd_VPR128.16B = Rn_VPR128.16B & TMPQ1 on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] & TMPQ1[0,8];
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] & TMPQ1[8,8];
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] & TMPQ1[16,8];
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] & TMPQ1[24,8];
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] & TMPQ1[32,8];
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] & TMPQ1[40,8];
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] & TMPQ1[48,8];
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] & TMPQ1[56,8];
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] & TMPQ1[64,8];
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] & TMPQ1[72,8];
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] & TMPQ1[80,8];
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] & TMPQ1[88,8];
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] & TMPQ1[96,8];
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] & TMPQ1[104,8];
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] & TMPQ1[112,8];
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] & TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.21 BIC (vector, register) page C7-1430 line 79136 MATCH x0e601c00/mask=xbfe0fc00
# CONSTRUCT x0e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $~@1 =$&@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_bic/2@1
# AUNIT --inst x0e601c00/mask=xffe0fc00 --status pass
:bic Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd unary TMPD1 = ~(Rm_VPR64.8B) on lane size 1
TMPD1[0,8] = ~(Rm_VPR64.8B[0,8]);
TMPD1[8,8] = ~(Rm_VPR64.8B[8,8]);
TMPD1[16,8] = ~(Rm_VPR64.8B[16,8]);
TMPD1[24,8] = ~(Rm_VPR64.8B[24,8]);
TMPD1[32,8] = ~(Rm_VPR64.8B[32,8]);
TMPD1[40,8] = ~(Rm_VPR64.8B[40,8]);
TMPD1[48,8] = ~(Rm_VPR64.8B[48,8]);
TMPD1[56,8] = ~(Rm_VPR64.8B[56,8]);
# simd infix Rd_VPR64.8B = Rn_VPR64.8B & TMPD1 on lane size 1
Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] & TMPD1[0,8];
Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] & TMPD1[8,8];
Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] & TMPD1[16,8];
Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] & TMPD1[24,8];
Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] & TMPD1[32,8];
Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] & TMPD1[40,8];
Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] & TMPD1[48,8];
Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] & TMPD1[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.22 BIF page C7-1432 line 79219 MATCH x2ee01c00/mask=xbfe0fc00
# CONSTRUCT x6ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bif/3@1
# AUNIT --inst x6ee01c00/mask=xffe0fc00 --status nopcodeop
:bif Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_bif(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.22 BIF page C7-1432 line 79219 MATCH x2ee01c00/mask=xbfe0fc00
# CONSTRUCT x2ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bif/3@1
# AUNIT --inst x2ee01c00/mask=xffe0fc00 --status nopcodeop
:bif Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_bif(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.23 BIT page C7-1434 line 79302 MATCH x2ea01c00/mask=xbfe0fc00
# CONSTRUCT x6ea01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bit/3@1
# AUNIT --inst x6ea01c00/mask=xffe0fc00 --status nopcodeop
:bit Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_bit(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.23 BIT page C7-1434 line 79302 MATCH x2ea01c00/mask=xbfe0fc00
# CONSTRUCT x2ea01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bit/3@1
# AUNIT --inst x2ea01c00/mask=xffe0fc00 --status nopcodeop
:bit Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_bit(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.24 BSL page C7-1436 line 79384 MATCH x2e601c00/mask=xbfe0fc00
# CONSTRUCT x6e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bsl/3@1
# AUNIT --inst x6e601c00/mask=xffe0fc00 --status nopcodeop
:bsl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_bsl(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.24 BSL page C7-1436 line 79384 MATCH x2e601c00/mask=xbfe0fc00
# CONSTRUCT x2e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bsl/3@1
# AUNIT --inst x2e601c00/mask=xffe0fc00 --status nopcodeop
:bsl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_bsl(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.25 CLS (vector) page C7-1438 line 79466 MATCH x0e204800/mask=xbf3ffc00
# CONSTRUCT x0e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@1
# AUNIT --inst x0e204800/mask=xfffffc00 --status nopcodeop
# CLS (vector) SIMD 8B when size = 00 , Q = 0
:cls Rd_VPR64.8B, Rn_VPR64.8B
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cls(Rn_VPR64.8B, 1:1);
}
# C7.2.25 CLS (vector) page C7-1438 line 79466 MATCH x0e204800/mask=xbf3ffc00
# CONSTRUCT x4e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@1
# AUNIT --inst x4e204800/mask=xfffffc00 --status nopcodeop
# CLS (vector) SIMD 16B when size = 00 , Q = 1
:cls Rd_VPR128.16B, Rn_VPR128.16B
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cls(Rn_VPR128.16B, 1:1);
}
# C7.2.25 CLS (vector) page C7-1438 line 79466 MATCH x0e204800/mask=xbf3ffc00
# CONSTRUCT x0e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@2
# AUNIT --inst x0e604800/mask=xfffffc00 --status nopcodeop
# CLS (vector) SIMD 4H when size = 01 , Q = 0
:cls Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_cls(Rn_VPR64.4H, 2:1);
}
# C7.2.25 CLS (vector) page C7-1438 line 79466 MATCH x0e204800/mask=xbf3ffc00
# CONSTRUCT x4e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@2
# AUNIT --inst x4e604800/mask=xfffffc00 --status nopcodeop
# CLS (vector) SIMD 8H when size = 01 , Q = 1
:cls Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_cls(Rn_VPR128.8H, 2:1);
}
# C7.2.25 CLS (vector) page C7-1438 line 79466 MATCH x0e204800/mask=xbf3ffc00
# CONSTRUCT x0ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@4
# AUNIT --inst x0ea04800/mask=xfffffc00 --status nopcodeop
# CLS (vector) SIMD 2S when size = 10 , Q = 0
:cls Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_cls(Rn_VPR64.2S, 4:1);
}
# C7.2.25 CLS (vector) page C7-1438 line 79466 MATCH x0e204800/mask=xbf3ffc00
# CONSTRUCT x4ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@4
# AUNIT --inst x4ea04800/mask=xfffffc00 --status nopcodeop
# CLS (vector) SIMD 4S when size = 10 , Q = 1
:cls Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_cls(Rn_VPR128.4S, 4:1);
}
# C7.2.26 CLZ (vector) page C7-1440 line 79562 MATCH x2e204800/mask=xbf3ffc00
# CONSTRUCT x2e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@1
# AUNIT --inst x2e204800/mask=xfffffc00 --status nopcodeop
# CLZ (vector) SIMD 8B when size = 00 , Q = 0
:clz Rd_VPR64.8B, Rn_VPR64.8B
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_clz(Rn_VPR64.8B, 1:1);
}
# C7.2.26 CLZ (vector) page C7-1440 line 79562 MATCH x2e204800/mask=xbf3ffc00
# CONSTRUCT x6e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@1
# AUNIT --inst x6e204800/mask=xfffffc00 --status nopcodeop
# CLZ (vector) SIMD 16B when size = 00 , Q = 1
:clz Rd_VPR128.16B, Rn_VPR128.16B
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_clz(Rn_VPR128.16B, 1:1);
}
# C7.2.26 CLZ (vector) page C7-1440 line 79562 MATCH x2e204800/mask=xbf3ffc00
# CONSTRUCT x2e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@2
# AUNIT --inst x2e604800/mask=xfffffc00 --status nopcodeop
# CLZ (vector) SIMD 4H when size = 01 , Q = 0
:clz Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_clz(Rn_VPR64.4H, 2:1);
}
# C7.2.26 CLZ (vector) page C7-1440 line 79562 MATCH x2e204800/mask=xbf3ffc00
# CONSTRUCT x6e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@2
# AUNIT --inst x6e604800/mask=xfffffc00 --status nopcodeop
# CLZ (vector) SIMD 8H when size = 01 , Q = 1
:clz Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_clz(Rn_VPR128.8H, 2:1);
}
# C7.2.26 CLZ (vector) page C7-1440 line 79562 MATCH x2e204800/mask=xbf3ffc00
# CONSTRUCT x2ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@4
# AUNIT --inst x2ea04800/mask=xfffffc00 --status nopcodeop
# CLZ (vector) SIMD 2S when size = 10 , Q = 0
:clz Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_clz(Rn_VPR64.2S, 4:1);
}
# C7.2.26 CLZ (vector) page C7-1440 line 79562 MATCH x2e204800/mask=xbf3ffc00
# CONSTRUCT x6ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@4
# AUNIT --inst x6ea04800/mask=xfffffc00 --status nopcodeop
# CLZ (vector) SIMD 4S when size = 10 , Q = 1
:clz Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_clz(Rn_VPR128.4S, 4:1);
}
# C7.2.27 CMEQ (register) page C7-1442 line 79657 MATCH x7e208c00/mask=xff20fc00
# CONSTRUCT x7ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 dup dup dup ARG2 ARG3 equal:1 zext:8 0:8 ~ =*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2
# AUNIT --inst x7ee08c00/mask=xffe0fc00 --status pass
# CMEQ (register) Scalar
:cmeq Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_2431=0b01111110 & b_2223=0b11 & b_21=1 & b_1015=0b100011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
local tmp1:1 = Rn_FPR64 == Rm_FPR64;
local tmp2:8 = zext(tmp1);
local tmp3:8 = ~ 0:8;
Rd_FPR64 = tmp2 * tmp3;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.27 CMEQ (register) page C7-1442 line 79657 MATCH x2e208c00/mask=xbf20fc00
# CONSTRUCT x2e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@1
# AUNIT --inst x2e208c00/mask=xffe0fc00 --status nopcodeop
# CMEQ (register) SIMD 8B when size = 00 , Q = 0
:cmeq Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_21=1 & b_1015=0b100011 & Rd_VPR64.8B & Rn_VPR64.8B & Rm_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cmeq(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.27 CMEQ (register) page C7-1442 line 79657 MATCH x2e208c00/mask=xbf20fc00
# CONSTRUCT x6e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@1
# AUNIT --inst x6e208c00/mask=xffe0fc00 --status nopcodeop
# CMEQ (register) SIMD 16B when size = 00 , Q = 1
:cmeq Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_21=1 & b_1015=0b100011 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cmeq(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.27 CMEQ (register) page C7-1442 line 79657 MATCH x2e208c00/mask=xbf20fc00
# CONSTRUCT x2e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@2
# AUNIT --inst x2e608c00/mask=xffe0fc00 --status nopcodeop
# CMEQ (register) SIMD 4H when size = 01 , Q = 0
:cmeq Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_21=1 & b_1015=0b100011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_cmeq(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.27 CMEQ (register) page C7-1442 line 79657 MATCH x2e208c00/mask=xbf20fc00
# CONSTRUCT x6e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@2
# AUNIT --inst x6e608c00/mask=xffe0fc00 --status nopcodeop
# CMEQ (register) SIMD 8H when size = 01 , Q = 1
:cmeq Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_21=1 & b_1015=0b100011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_cmeq(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.27 CMEQ (register) page C7-1442 line 79657 MATCH x2e208c00/mask=xbf20fc00
# CONSTRUCT x2ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@4
# AUNIT --inst x2ea08c00/mask=xffe0fc00 --status nopcodeop
# CMEQ (register) SIMD 2S when size = 10 , Q = 0
:cmeq Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=1 & b_1015=0b100011 & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_cmeq(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.27 CMEQ (register) page C7-1442 line 79657 MATCH x2e208c00/mask=xbf20fc00
# CONSTRUCT x6ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@4
# AUNIT --inst x6ea08c00/mask=xffe0fc00 --status nopcodeop
# CMEQ (register) SIMD 4S when size = 10 , Q = 1
:cmeq Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=1 & b_1015=0b100011 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_cmeq(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.27 CMEQ (register) page C7-1442 line 79657 MATCH x2e208c00/mask=xbf20fc00
# CONSTRUCT x6ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@8
# AUNIT --inst x6ee08c00/mask=xffe0fc00 --status nopcodeop
# CMEQ (register) SIMD 2D when size = 11 , Q = 1
:cmeq Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_21=1 & b_1015=0b100011 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_cmeq(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.28 CMEQ (zero) page C7-1444 line 79796 MATCH x0e209800/mask=xbf3ffc00
# CONSTRUCT x4e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmeq/2@1
# AUNIT --inst x4e209800/mask=xfffffc00 --status nopcodeop
:cmeq Rd_VPR128.16B, Rn_VPR128.16B, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cmeq(Rn_VPR128.16B, 0:1, 1:1);
}
# C7.2.28 CMEQ (zero) page C7-1444 line 79796 MATCH x0e209800/mask=xbf3ffc00
# CONSTRUCT x4ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmeq/2@8
# AUNIT --inst x4ee09800/mask=xfffffc00 --status nopcodeop
:cmeq Rd_VPR128.2D, Rn_VPR128.2D, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_cmeq(Rn_VPR128.2D, 0:8, 8:1);
}
# C7.2.28 CMEQ (zero) page C7-1444 line 79796 MATCH x0e209800/mask=xbf3ffc00
# CONSTRUCT x0ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmeq/2@4
# AUNIT --inst x0ea09800/mask=xfffffc00 --status nopcodeop
:cmeq Rd_VPR64.2S, Rn_VPR64.2S, "#0"
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_cmeq(Rn_VPR64.2S, 0:4, 4:1);
}
# C7.2.28 CMEQ (zero) page C7-1444 line 79796 MATCH x0e209800/mask=xbf3ffc00
# CONSTRUCT x0e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmeq/2@2
# AUNIT --inst x0e609800/mask=xfffffc00 --status nopcodeop
:cmeq Rd_VPR64.4H, Rn_VPR64.4H, "#0"
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_cmeq(Rn_VPR64.4H, 0:2, 2:1);
}
# C7.2.28 CMEQ (zero) page C7-1444 line 79796 MATCH x0e209800/mask=xbf3ffc00
# CONSTRUCT x4ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmeq/2@2
# AUNIT --inst x4ea09800/mask=xfffffc00 --status nopcodeop
:cmeq Rd_VPR128.4S, Rn_VPR128.4S, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_cmeq(Rn_VPR128.4S, 0:4, 2:1);
}
# C7.2.28 CMEQ (zero) page C7-1444 line 79796 MATCH x0e209800/mask=xbf3ffc00
# CONSTRUCT x0e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmeq/2@1
# AUNIT --inst x0e209800/mask=xfffffc00 --status nopcodeop
:cmeq Rd_VPR64.8B, Rn_VPR64.8B, "#0"
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cmeq(Rn_VPR64.8B, 0:1, 1:1);
}
# C7.2.28 CMEQ (zero) page C7-1444 line 79796 MATCH x0e209800/mask=xbf3ffc00
# CONSTRUCT x4e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmeq/2@2
# AUNIT --inst x4e609800/mask=xfffffc00 --status nopcodeop
:cmeq Rd_VPR128.8H, Rn_VPR128.8H, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_cmeq(Rn_VPR128.8H, 0:2, 2:1);
}
# C7.2.28 CMEQ (zero) page C7-1444 line 79796 MATCH x5e209800/mask=xff3ffc00
# CONSTRUCT x5ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmeq/2
# AUNIT --inst x5ee09800/mask=xfffffc00 --status nopcodeop
:cmeq Rd_FPR64, Rn_FPR64, "#0"
is b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000100110 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_cmeq(Rn_FPR64, 0:4);
}
# C7.2.29 CMGE (register) page C7-1447 line 79951 MATCH x0e203c00/mask=xbf20fc00
# CONSTRUCT x4e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@1
# AUNIT --inst x4e203c00/mask=xffe0fc00 --status nopcodeop
:cmge Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x7 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cmge(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.29 CMGE (register) page C7-1447 line 79951 MATCH x0e203c00/mask=xbf20fc00
# CONSTRUCT x4ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@8
# AUNIT --inst x4ee03c00/mask=xffe0fc00 --status nopcodeop
:cmge Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x7 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_cmge(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.29 CMGE (register) page C7-1447 line 79951 MATCH x0e203c00/mask=xbf20fc00
# CONSTRUCT x0ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@4
# AUNIT --inst x0ea03c00/mask=xffe0fc00 --status nopcodeop
:cmge Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x7 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_cmge(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.29 CMGE (register) page C7-1447 line 79951 MATCH x0e203c00/mask=xbf20fc00
# CONSTRUCT x0e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@2
# AUNIT --inst x0e603c00/mask=xffe0fc00 --status nopcodeop
:cmge Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x7 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_cmge(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.29 CMGE (register) page C7-1447 line 79951 MATCH x0e203c00/mask=xbf20fc00
# CONSTRUCT x4ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@4
# AUNIT --inst x4ea03c00/mask=xffe0fc00 --status nopcodeop
:cmge Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x7 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_cmge(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.29 CMGE (register) page C7-1447 line 79951 MATCH x0e203c00/mask=xbf20fc00
# CONSTRUCT x0e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@1
# AUNIT --inst x0e203c00/mask=xffe0fc00 --status nopcodeop
:cmge Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x7 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cmge(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.29 CMGE (register) page C7-1447 line 79951 MATCH x0e203c00/mask=xbf20fc00
# CONSTRUCT x4e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@2
# AUNIT --inst x4e603c00/mask=xffe0fc00 --status nopcodeop
:cmge Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x7 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_cmge(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.29 CMGE (register) page C7-1447 line 79951 MATCH x5e203c00/mask=xff20fc00
# CONSTRUCT x5ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2
# AUNIT --inst x5ee03c00/mask=xffe0fc00 --status nopcodeop
:cmge Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_2431=0b01011110 & b_2223=0b11 & b_21=1 & b_1015=0b001111 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
Rd_FPR64 = NEON_cmge(Rn_FPR64, Rm_FPR64);
}
# C7.2.30 CMGE (zero) page C7-1449 line 80089 MATCH x2e208800/mask=xbf3ffc00
# CONSTRUCT x6e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmge/2@1
# AUNIT --inst x6e208800/mask=xfffffc00 --status nopcodeop
:cmge Rd_VPR128.16B, Rn_VPR128.16B, "#0"
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cmge(Rn_VPR128.16B, 0:1, 1:1);
}
# C7.2.30 CMGE (zero) page C7-1449 line 80089 MATCH x2e208800/mask=xbf3ffc00
# CONSTRUCT x6ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmge/2@8
# AUNIT --inst x6ee08800/mask=xfffffc00 --status nopcodeop
:cmge Rd_VPR128.2D, Rn_VPR128.2D, "#0"
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_cmge(Rn_VPR128.2D, 0:8, 8:1);
}
# C7.2.30 CMGE (zero) page C7-1449 line 80089 MATCH x2e208800/mask=xbf3ffc00
# CONSTRUCT x2ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmge/2@4
# AUNIT --inst x2ea08800/mask=xfffffc00 --status nopcodeop
:cmge Rd_VPR64.2S, Rn_VPR64.2S, "#0"
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_cmge(Rn_VPR64.2S, 0:4, 4:1);
}
# C7.2.30 CMGE (zero) page C7-1449 line 80089 MATCH x2e208800/mask=xbf3ffc00
# CONSTRUCT x2e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmge/2@2
# AUNIT --inst x2e608800/mask=xfffffc00 --status nopcodeop
:cmge Rd_VPR64.4H, Rn_VPR64.4H, "#0"
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_cmge(Rn_VPR64.4H, 0:2, 2:1);
}
# C7.2.30 CMGE (zero) page C7-1449 line 80089 MATCH x2e208800/mask=xbf3ffc00
# CONSTRUCT x6ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmge/2@4
# AUNIT --inst x6ea08800/mask=xfffffc00 --status nopcodeop
:cmge Rd_VPR128.4S, Rn_VPR128.4S, "#0"
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_cmge(Rn_VPR128.4S, 0:4, 4:1);
}
# C7.2.30 CMGE (zero) page C7-1449 line 80089 MATCH x2e208800/mask=xbf3ffc00
# CONSTRUCT x2e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmge/2@1
# AUNIT --inst x2e208800/mask=xfffffc00 --status nopcodeop
:cmge Rd_VPR64.8B, Rn_VPR64.8B, "#0"
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cmge(Rn_VPR64.8B, 0:1, 1:1);
}
# C7.2.30 CMGE (zero) page C7-1449 line 80089 MATCH x2e208800/mask=xbf3ffc00
# CONSTRUCT x6e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmge/2@2
# AUNIT --inst x6e608800/mask=xfffffc00 --status nopcodeop
:cmge Rd_VPR128.8H, Rn_VPR128.8H, "#0"
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_cmge(Rn_VPR128.8H, 0:2, 2:1);
}
# C7.2.30 CMGE (zero) page C7-1449 line 80089 MATCH x7e208800/mask=xff3ffc00
# CONSTRUCT x7ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmge/2
# AUNIT --inst x7ee08800/mask=xfffffc00 --status nopcodeop
:cmge Rd_FPR64, Rn_FPR64, "#0"
is b_2431=0b01111110 & b_2223=0b11 & b_1021=0b100000100010 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_cmge(Rn_FPR64, 0:4);
}
# C7.2.31 CMGT (register) page C7-1452 line 80244 MATCH x0e203400/mask=xbf20fc00
# CONSTRUCT x4e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@1
# AUNIT --inst x4e203400/mask=xffe0fc00 --status nopcodeop
:cmgt Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cmgt(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.31 CMGT (register) page C7-1452 line 80244 MATCH x0e203400/mask=xbf20fc00
# CONSTRUCT x4ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@8
# AUNIT --inst x4ee03400/mask=xffe0fc00 --status nopcodeop
:cmgt Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_cmgt(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.31 CMGT (register) page C7-1452 line 80244 MATCH x0e203400/mask=xbf20fc00
# CONSTRUCT x0ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@4
# AUNIT --inst x0ea03400/mask=xffe0fc00 --status nopcodeop
:cmgt Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_cmgt(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.31 CMGT (register) page C7-1452 line 80244 MATCH x0e203400/mask=xbf20fc00
# CONSTRUCT x0e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@2
# AUNIT --inst x0e603400/mask=xffe0fc00 --status nopcodeop
:cmgt Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_cmgt(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.31 CMGT (register) page C7-1452 line 80244 MATCH x0e203400/mask=xbf20fc00
# CONSTRUCT x4ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@4
# AUNIT --inst x4ea03400/mask=xffe0fc00 --status nopcodeop
:cmgt Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_cmgt(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.31 CMGT (register) page C7-1452 line 80244 MATCH x0e203400/mask=xbf20fc00
# CONSTRUCT x0e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@1
# AUNIT --inst x0e203400/mask=xffe0fc00 --status nopcodeop
:cmgt Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cmgt(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.31 CMGT (register) page C7-1452 line 80244 MATCH x0e203400/mask=xbf20fc00
# CONSTRUCT x4e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@2
# AUNIT --inst x4e603400/mask=xffe0fc00 --status nopcodeop
:cmgt Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_cmgt(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.31 CMGT (register) page C7-1452 line 80244 MATCH x5e203400/mask=xff20fc00
# CONSTRUCT x5ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2
# AUNIT --inst x5ee03400/mask=xffe0fc00 --status nopcodeop
:cmgt Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_2431=0b01011110 & b_2223=0b11 & b_21=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
Rd_FPR64 = NEON_cmgt(Rn_FPR64, Rm_FPR64);
}
# C7.2.32 CMGT (zero) page C7-1454 line 80382 MATCH x0e208800/mask=xbf3ffc00
# CONSTRUCT x4e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmgt/2@1
# AUNIT --inst x4e208800/mask=xfffffc00 --status nopcodeop
:cmgt Rd_VPR128.16B, Rn_VPR128.16B, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cmgt(Rn_VPR128.16B, 0:1, 1:1);
}
# C7.2.32 CMGT (zero) page C7-1454 line 80382 MATCH x0e208800/mask=xbf3ffc00
# CONSTRUCT x4ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmgt/2@8
# AUNIT --inst x4ee08800/mask=xfffffc00 --status nopcodeop
:cmgt Rd_VPR128.2D, Rn_VPR128.2D, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_cmgt(Rn_VPR128.2D, 0:8, 8:1);
}
# C7.2.32 CMGT (zero) page C7-1454 line 80382 MATCH x0e208800/mask=xbf3ffc00
# CONSTRUCT x0ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmgt/2@4
# AUNIT --inst x0ea08800/mask=xfffffc00 --status nopcodeop
:cmgt Rd_VPR64.2S, Rn_VPR64.2S, "#0"
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_cmgt(Rn_VPR64.2S, 0:4, 4:1);
}
# C7.2.32 CMGT (zero) page C7-1454 line 80382 MATCH x0e208800/mask=xbf3ffc00
# CONSTRUCT x0e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmgt/2@2
# AUNIT --inst x0e608800/mask=xfffffc00 --status nopcodeop
:cmgt Rd_VPR64.4H, Rn_VPR64.4H, "#0"
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_cmgt(Rn_VPR64.4H, 0:2, 2:1);
}
# C7.2.32 CMGT (zero) page C7-1454 line 80382 MATCH x0e208800/mask=xbf3ffc00
# CONSTRUCT x4ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmgt/2@4
# AUNIT --inst x4ea08800/mask=xfffffc00 --status nopcodeop
:cmgt Rd_VPR128.4S, Rn_VPR128.4S, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_cmgt(Rn_VPR128.4S, 0:4, 4:1);
}
# C7.2.32 CMGT (zero) page C7-1454 line 80382 MATCH x0e208800/mask=xbf3ffc00
# CONSTRUCT x0e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmgt/2@1
# AUNIT --inst x0e208800/mask=xfffffc00 --status nopcodeop
:cmgt Rd_VPR64.8B, Rn_VPR64.8B, "#0"
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cmgt(Rn_VPR64.8B, 0:1, 1:1);
}
# C7.2.32 CMGT (zero) page C7-1454 line 80382 MATCH x0e208800/mask=xbf3ffc00
# CONSTRUCT x4e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmgt/2@2
# AUNIT --inst x4e608800/mask=xfffffc00 --status nopcodeop
:cmgt Rd_VPR128.8H, Rn_VPR128.8H, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_cmgt(Rn_VPR128.8H, 0:2, 2:1);
}
# C7.2.32 CMGT (zero) page C7-1454 line 80382 MATCH x5e208800/mask=xff3ffc00
# CONSTRUCT x5ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmgt/2
# AUNIT --inst x5ee08800/mask=xfffffc00 --status nopcodeop
:cmgt Rd_FPR64, Rn_FPR64, "#0"
is b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000100010 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_cmgt(Rn_FPR64, 0:8);
}
# C7.2.33 CMHI (register) page C7-1457 line 80537 MATCH x2e203400/mask=xbf20fc00
# CONSTRUCT x6e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@1
# AUNIT --inst x6e203400/mask=xffe0fc00 --status nopcodeop
:cmhi Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cmhi(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.33 CMHI (register) page C7-1457 line 80537 MATCH x2e203400/mask=xbf20fc00
# CONSTRUCT x6ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@8
# AUNIT --inst x6ee03400/mask=xffe0fc00 --status nopcodeop
:cmhi Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_cmhi(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.33 CMHI (register) page C7-1457 line 80537 MATCH x2e203400/mask=xbf20fc00
# CONSTRUCT x2ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@4
# AUNIT --inst x2ea03400/mask=xffe0fc00 --status nopcodeop
:cmhi Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_cmhi(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.33 CMHI (register) page C7-1457 line 80537 MATCH x2e203400/mask=xbf20fc00
# CONSTRUCT x2e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@2
# AUNIT --inst x2e603400/mask=xffe0fc00 --status nopcodeop
:cmhi Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_cmhi(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.33 CMHI (register) page C7-1457 line 80537 MATCH x2e203400/mask=xbf20fc00
# CONSTRUCT x6ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@4
# AUNIT --inst x6ea03400/mask=xffe0fc00 --status nopcodeop
:cmhi Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_cmhi(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.33 CMHI (register) page C7-1457 line 80537 MATCH x2e203400/mask=xbf20fc00
# CONSTRUCT x2e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@1
# AUNIT --inst x2e203400/mask=xffe0fc00 --status nopcodeop
:cmhi Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cmhi(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.33 CMHI (register) page C7-1457 line 80537 MATCH x2e203400/mask=xbf20fc00
# CONSTRUCT x6e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@2
# AUNIT --inst x6e603400/mask=xffe0fc00 --status nopcodeop
:cmhi Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_cmhi(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.33 CMHI (register) page C7-1457 line 80537 MATCH x7e203400/mask=xff20fc00
# CONSTRUCT x7ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2
# AUNIT --inst x7ee03400/mask=xffe0fc00 --status nopcodeop
:cmhi Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_2431=0b01111110 & b_2223=0b11 & b_21=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
Rd_FPR64 = NEON_cmhi(Rn_FPR64, Rm_FPR64);
}
# C7.2.34 CMHS (register) page C7-1459 line 80675 MATCH x2e203c00/mask=xbf20fc00
# CONSTRUCT x6e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@1
# AUNIT --inst x6e203c00/mask=xffe0fc00 --status nopcodeop
:cmhs Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x7 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cmhs(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.34 CMHS (register) page C7-1459 line 80675 MATCH x2e203c00/mask=xbf20fc00
# CONSTRUCT x6ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@8
# AUNIT --inst x6ee03c00/mask=xffe0fc00 --status nopcodeop
:cmhs Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x7 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_cmhs(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.34 CMHS (register) page C7-1459 line 80675 MATCH x2e203c00/mask=xbf20fc00
# CONSTRUCT x2ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@4
# AUNIT --inst x2ea03c00/mask=xffe0fc00 --status nopcodeop
:cmhs Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x7 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_cmhs(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.34 CMHS (register) page C7-1459 line 80675 MATCH x2e203c00/mask=xbf20fc00
# CONSTRUCT x2e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@2
# AUNIT --inst x2e603c00/mask=xffe0fc00 --status nopcodeop
:cmhs Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x7 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_cmhs(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.34 CMHS (register) page C7-1459 line 80675 MATCH x2e203c00/mask=xbf20fc00
# CONSTRUCT x6ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@4
# AUNIT --inst x6ea03c00/mask=xffe0fc00 --status nopcodeop
:cmhs Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x7 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_cmhs(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.34 CMHS (register) page C7-1459 line 80675 MATCH x2e203c00/mask=xbf20fc00
# CONSTRUCT x2e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@1
# AUNIT --inst x2e203c00/mask=xffe0fc00 --status nopcodeop
:cmhs Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x7 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cmhs(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.34 CMHS (register) page C7-1459 line 80675 MATCH x2e203c00/mask=xbf20fc00
# CONSTRUCT x6e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@2
# AUNIT --inst x6e603c00/mask=xffe0fc00 --status nopcodeop
:cmhs Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x7 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_cmhs(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.34 CMHS (register) page C7-1459 line 80675 MATCH x7e203c00/mask=xff20fc00
# CONSTRUCT x7ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2
# AUNIT --inst x7ee03c00/mask=xffe0fc00 --status nopcodeop
:cmhs Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_2431=0b01111110 & b_2223=0b11 & b_21=1 & b_1015=0b001111 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
Rd_FPR64 = NEON_cmhs(Rn_FPR64, Rm_FPR64);
}
# C7.2.35 CMLE (zero) page C7-1461 line 80813 MATCH x2e209800/mask=xbf3ffc00
# CONSTRUCT x6e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmle/2@1
# AUNIT --inst x6e209800/mask=xfffffc00 --status nopcodeop
:cmle Rd_VPR128.16B, Rn_VPR128.16B, "#0"
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cmle(Rn_VPR128.16B, 0:1, 1:1);
}
# C7.2.35 CMLE (zero) page C7-1461 line 80813 MATCH x2e209800/mask=xbf3ffc00
# CONSTRUCT x6ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmle/2@8
# AUNIT --inst x6ee09800/mask=xfffffc00 --status nopcodeop
:cmle Rd_VPR128.2D, Rn_VPR128.2D, "#0"
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_cmle(Rn_VPR128.2D, 0:8, 8:1);
}
# C7.2.35 CMLE (zero) page C7-1461 line 80813 MATCH x2e209800/mask=xbf3ffc00
# CONSTRUCT x2ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmle/2@4
# AUNIT --inst x2ea09800/mask=xfffffc00 --status nopcodeop
:cmle Rd_VPR64.2S, Rn_VPR64.2S, "#0"
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_cmle(Rn_VPR64.2S, 0:4, 4:1);
}
# C7.2.35 CMLE (zero) page C7-1461 line 80813 MATCH x2e209800/mask=xbf3ffc00
# CONSTRUCT x2e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmle/2@2
# AUNIT --inst x2e609800/mask=xfffffc00 --status nopcodeop
:cmle Rd_VPR64.4H, Rn_VPR64.4H, "#0"
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_cmle(Rn_VPR64.4H, 0:2, 2:1);
}
# C7.2.35 CMLE (zero) page C7-1461 line 80813 MATCH x2e209800/mask=xbf3ffc00
# CONSTRUCT x6ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmle/2@4
# AUNIT --inst x6ea09800/mask=xfffffc00 --status nopcodeop
:cmle Rd_VPR128.4S, Rn_VPR128.4S, "#0"
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_cmle(Rn_VPR128.4S, 0:4, 4:1);
}
# C7.2.35 CMLE (zero) page C7-1461 line 80813 MATCH x2e209800/mask=xbf3ffc00
# CONSTRUCT x2e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmle/2@1
# AUNIT --inst x2e209800/mask=xfffffc00 --status nopcodeop
:cmle Rd_VPR64.8B, Rn_VPR64.8B, "#0"
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cmle(Rn_VPR64.8B, 0:1, 1:1);
}
# C7.2.35 CMLE (zero) page C7-1461 line 80813 MATCH x2e209800/mask=xbf3ffc00
# CONSTRUCT x6e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmle/2@2
# AUNIT --inst x6e609800/mask=xfffffc00 --status nopcodeop
:cmle Rd_VPR128.8H, Rn_VPR128.8H, "#0"
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_cmle(Rn_VPR128.8H, 0:2, 2:1);
}
# C7.2.35 CMLE (zero) page C7-1461 line 80813 MATCH x7e209800/mask=xff3ffc00
# CONSTRUCT x7ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmle/2
# AUNIT --inst x7ee09800/mask=xfffffc00 --status nopcodeop
:cmle Rd_FPR64, Rn_FPR64, "#0"
is b_2431=0b01111110 & b_2223=0b11 & b_1021=0b100000100110 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_cmle(Rn_FPR64, 0:8);
}
# C7.2.36 CMLT (zero) page C7-1464 line 80968 MATCH x0e20a800/mask=xbf3ffc00
# CONSTRUCT x4e20a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmlt/2@1
# AUNIT --inst x4e20a800/mask=xfffffc00 --status nopcodeop
:cmlt Rd_VPR128.16B, Rn_VPR128.16B, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cmlt(Rn_VPR128.16B, 0:1, 1:1);
}
# C7.2.36 CMLT (zero) page C7-1464 line 80968 MATCH x0e20a800/mask=xbf3ffc00
# CONSTRUCT x4ee0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmlt/2@8
# AUNIT --inst x4ee0a800/mask=xfffffc00 --status nopcodeop
:cmlt Rd_VPR128.2D, Rn_VPR128.2D, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_cmlt(Rn_VPR128.2D, 0:8, 8:1);
}
# C7.2.36 CMLT (zero) page C7-1464 line 80968 MATCH x0e20a800/mask=xbf3ffc00
# CONSTRUCT x0ea0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmlt/2@4
# AUNIT --inst x0ea0a800/mask=xfffffc00 --status nopcodeop
:cmlt Rd_VPR64.2S, Rn_VPR64.2S, "#0"
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_cmlt(Rn_VPR64.2S, 0:4, 4:1);
}
# C7.2.36 CMLT (zero) page C7-1464 line 80968 MATCH x0e20a800/mask=xbf3ffc00
# CONSTRUCT x0e60a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmlt/2@2
# AUNIT --inst x0e60a800/mask=xfffffc00 --status nopcodeop
:cmlt Rd_VPR64.4H, Rn_VPR64.4H, "#0"
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_cmlt(Rn_VPR64.4H, 0:2, 2:1);
}
# C7.2.36 CMLT (zero) page C7-1464 line 80968 MATCH x0e20a800/mask=xbf3ffc00
# CONSTRUCT x4ea0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmlt/2@4
# AUNIT --inst x4ea0a800/mask=xfffffc00 --status nopcodeop
:cmlt Rd_VPR128.4S, Rn_VPR128.4S, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_cmlt(Rn_VPR128.4S, 0:4, 4:1);
}
# C7.2.36 CMLT (zero) page C7-1464 line 80968 MATCH x0e20a800/mask=xbf3ffc00
# CONSTRUCT x0e20a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmlt/2@1
# AUNIT --inst x0e20a800/mask=xfffffc00 --status nopcodeop
:cmlt Rd_VPR64.8B, Rn_VPR64.8B, "#0"
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cmlt(Rn_VPR64.8B, 0:1, 1:1);
}
# C7.2.36 CMLT (zero) page C7-1464 line 80968 MATCH x0e20a800/mask=xbf3ffc00
# CONSTRUCT x4e60a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmlt/2@2
# AUNIT --inst x4e60a800/mask=xfffffc00 --status nopcodeop
:cmlt Rd_VPR128.8H, Rn_VPR128.8H, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_cmlt(Rn_VPR128.8H, 0:2, 2:1);
}
# C7.2.36 CMLT (zero) page C7-1464 line 80968 MATCH x5e20a800/mask=xff3ffc00
# CONSTRUCT x5ee0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmlt/2
# AUNIT --inst x5ee0a800/mask=xfffffc00 --status nopcodeop
:cmlt Rd_FPR64, Rn_FPR64, "#0"
is b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000101010 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_cmlt(Rn_FPR64, 0:8);
}
# C7.2.37 CMTST page C7-1466 line 81106 MATCH x0e208c00/mask=xbf20fc00
# CONSTRUCT x4e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@1
# AUNIT --inst x4e208c00/mask=xffe0fc00 --status nopcodeop
:cmtst Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x11 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cmtst(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.37 CMTST page C7-1466 line 81106 MATCH x0e208c00/mask=xbf20fc00
# CONSTRUCT x4ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@8
# AUNIT --inst x4ee08c00/mask=xffe0fc00 --status nopcodeop
:cmtst Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_cmtst(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.37 CMTST page C7-1466 line 81106 MATCH x0e208c00/mask=xbf20fc00
# CONSTRUCT x0ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@4
# AUNIT --inst x0ea08c00/mask=xffe0fc00 --status nopcodeop
:cmtst Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x11 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_cmtst(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.37 CMTST page C7-1466 line 81106 MATCH x0e208c00/mask=xbf20fc00
# CONSTRUCT x0e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@2
# AUNIT --inst x0e608c00/mask=xffe0fc00 --status nopcodeop
:cmtst Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x11 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_cmtst(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.37 CMTST page C7-1466 line 81106 MATCH x0e208c00/mask=xbf20fc00
# CONSTRUCT x4ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@4
# AUNIT --inst x4ea08c00/mask=xffe0fc00 --status nopcodeop
:cmtst Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_cmtst(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.37 CMTST page C7-1466 line 81106 MATCH x0e208c00/mask=xbf20fc00
# CONSTRUCT x0e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@1
# AUNIT --inst x0e208c00/mask=xffe0fc00 --status nopcodeop
:cmtst Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x11 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cmtst(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.37 CMTST page C7-1466 line 81106 MATCH x0e208c00/mask=xbf20fc00
# CONSTRUCT x4e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@2
# AUNIT --inst x4e608c00/mask=xffe0fc00 --status nopcodeop
:cmtst Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_cmtst(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.37 CMTST page C7-1466 line 81106 MATCH x5e208c00/mask=xff20fc00
# CONSTRUCT x5ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2
# AUNIT --inst x5ee08c00/mask=xffe0fc00 --status nopcodeop
:cmtst Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_2431=0b01011110 & b_2223=0b11 & b_21=1 & b_1015=0b100011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
Rd_FPR64 = NEON_cmtst(Rn_FPR64, Rm_FPR64);
}
# C7.2.38 CNT page C7-1468 line 81245 MATCH x0e205800/mask=xbf3ffc00
# CONSTRUCT x4e205800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_cnt/1@1
# AUNIT --inst x4e205800/mask=xfffffc00 --status nopcodeop
:cnt Rd_VPR128.16B, Rn_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_cnt(Rn_VPR128.16B, 1:1);
}
# C7.2.38 CNT page C7-1468 line 81245 MATCH x0e205800/mask=xbf3ffc00
# CONSTRUCT x0e205800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_cnt/1@1
# AUNIT --inst x0e205800/mask=xfffffc00 --status nopcodeop
:cnt Rd_VPR64.8B, Rn_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x5 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_cnt(Rn_VPR64.8B, 1:1);
}
# C7.2.39 DUP (element) page C7-1470 line 81332 MATCH x0e000400/mask=xbfe0fc00
# CONSTRUCT x4e010400/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1
# AUNIT --inst x4e010400/mask=xffe1fc00 --status pass
:dup Rd_VPR128.16B, Rn_VPR128.B.imm_neon_uimm4
is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.16B & Zd
{
# simd element Rn_VPR128[imm_neon_uimm4] lane size 1
local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;
# simd duplicate Rd_VPR128.16B = all elements tmp1 (lane size 1)
Rd_VPR128.16B[0,8] = tmp1;
Rd_VPR128.16B[8,8] = tmp1;
Rd_VPR128.16B[16,8] = tmp1;
Rd_VPR128.16B[24,8] = tmp1;
Rd_VPR128.16B[32,8] = tmp1;
Rd_VPR128.16B[40,8] = tmp1;
Rd_VPR128.16B[48,8] = tmp1;
Rd_VPR128.16B[56,8] = tmp1;
Rd_VPR128.16B[64,8] = tmp1;
Rd_VPR128.16B[72,8] = tmp1;
Rd_VPR128.16B[80,8] = tmp1;
Rd_VPR128.16B[88,8] = tmp1;
Rd_VPR128.16B[96,8] = tmp1;
Rd_VPR128.16B[104,8] = tmp1;
Rd_VPR128.16B[112,8] = tmp1;
Rd_VPR128.16B[120,8] = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.39 DUP (element) page C7-1470 line 81332 MATCH x0e000400/mask=xbfe0fc00
# CONSTRUCT x4e080400/mask=xffeffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@8
# AUNIT --inst x4e080400/mask=xffeffc00 --status pass
:dup Rd_VPR128.2D, Rn_VPR128.D.imm_neon_uimm1
is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.2D & Zd
{
# simd element Rn_VPR128[imm_neon_uimm1] lane size 8
local tmp1:8 = Rn_VPR128.D.imm_neon_uimm1;
# simd duplicate Rd_VPR128.2D = all elements tmp1 (lane size 8)
Rd_VPR128.2D[0,64] = tmp1;
Rd_VPR128.2D[64,64] = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.39 DUP (element) page C7-1470 line 81332 MATCH x0e000400/mask=xbfe0fc00
# CONSTRUCT x0e040400/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4
# AUNIT --inst x0e040400/mask=xffe7fc00 --status pass
:dup Rd_VPR64.2S, Rn_VPR128.S.imm_neon_uimm2
is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR64.2S & Zd
{
# simd element Rn_VPR128[imm_neon_uimm2] lane size 4
local tmp1:4 = Rn_VPR128.S.imm_neon_uimm2;
# simd duplicate Rd_VPR64.2S = all elements tmp1 (lane size 4)
Rd_VPR64.2S[0,32] = tmp1;
Rd_VPR64.2S[32,32] = tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.39 DUP (element) page C7-1470 line 81332 MATCH x0e000400/mask=xbfe0fc00
# CONSTRUCT x0e020400/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2
# AUNIT --inst x0e020400/mask=xffe3fc00 --status pass
:dup Rd_VPR64.4H, Rn_VPR128.H.imm_neon_uimm3
is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR64.4H & Zd
{
# simd element Rn_VPR128[imm_neon_uimm3] lane size 2
local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;
# simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2)
Rd_VPR64.4H[0,16] = tmp1;
Rd_VPR64.4H[16,16] = tmp1;
Rd_VPR64.4H[32,16] = tmp1;
Rd_VPR64.4H[48,16] = tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.39 DUP (element) page C7-1470 line 81332 MATCH x0e000400/mask=xbfe0fc00
# CONSTRUCT x4e040400/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4
# AUNIT --inst x4e040400/mask=xffe7fc00 --status pass
:dup Rd_VPR128.4S, Rn_VPR128.S.imm_neon_uimm2
is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.4S & Zd
{
# simd element Rn_VPR128[imm_neon_uimm2] lane size 4
local tmp1:4 = Rn_VPR128.S.imm_neon_uimm2;
# simd duplicate Rd_VPR128.4S = all elements tmp1 (lane size 4)
Rd_VPR128.4S[0,32] = tmp1;
Rd_VPR128.4S[32,32] = tmp1;
Rd_VPR128.4S[64,32] = tmp1;
Rd_VPR128.4S[96,32] = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.39 DUP (element) page C7-1470 line 81332 MATCH x0e000400/mask=xbfe0fc00
# CONSTRUCT x0e010400/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1
# AUNIT --inst x0e010400/mask=xffe1fc00 --status pass
:dup Rd_VPR64.8B, Rn_VPR128.B.imm_neon_uimm4
is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR64.8B & Zd
{
# simd element Rn_VPR128[imm_neon_uimm4] lane size 1
local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;
# simd duplicate Rd_VPR64.8B = all elements tmp1 (lane size 1)
Rd_VPR64.8B[0,8] = tmp1;
Rd_VPR64.8B[8,8] = tmp1;
Rd_VPR64.8B[16,8] = tmp1;
Rd_VPR64.8B[24,8] = tmp1;
Rd_VPR64.8B[32,8] = tmp1;
Rd_VPR64.8B[40,8] = tmp1;
Rd_VPR64.8B[48,8] = tmp1;
Rd_VPR64.8B[56,8] = tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.39 DUP (element) page C7-1470 line 81332 MATCH x0e000400/mask=xbfe0fc00
# CONSTRUCT x4e020400/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2
# AUNIT --inst x4e020400/mask=xffe3fc00 --status pass
:dup Rd_VPR128.8H, Rn_VPR128.H.imm_neon_uimm3
is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.8H & Zd
{
# simd element Rn_VPR128[imm_neon_uimm3] lane size 2
local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;
# simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2)
Rd_VPR128.8H[0,16] = tmp1;
Rd_VPR128.8H[16,16] = tmp1;
Rd_VPR128.8H[32,16] = tmp1;
Rd_VPR128.8H[48,16] = tmp1;
Rd_VPR128.8H[64,16] = tmp1;
Rd_VPR128.8H[80,16] = tmp1;
Rd_VPR128.8H[96,16] = tmp1;
Rd_VPR128.8H[112,16] = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.39 DUP (element) page C7-1470 line 81332 MATCH x5e000400/mask=xffe0fc00
# C7.2.199 MOV (scalar) page C7-1854 line 104019 MATCH x5e000400/mask=xffe0fc00
# CONSTRUCT x5e010400/mask=xffe1fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 =ARG2
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1
# AUNIT --inst x5e010400/mask=xffe1fc00 --status pass
:dup Rd_FPR8, Rn_VPR128.B.imm_neon_uimm4
is b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR8 & Zd
{
# simd element Rn_VPR128[imm_neon_uimm4] lane size 1
Rd_FPR8 = Rn_VPR128.B.imm_neon_uimm4;
zext_zb(Zd); # zero upper 31 bytes of Zd
}
# C7.2.39 DUP (element) page C7-1470 line 81332 MATCH x5e000400/mask=xffe0fc00
# C7.2.199 MOV (scalar) page C7-1854 line 104019 MATCH x5e000400/mask=xffe0fc00
# CONSTRUCT x5e080400/mask=xffeffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 =ARG2
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@8
# AUNIT --inst x5e080400/mask=xffeffc00 --status pass
:dup Rd_FPR64, Rn_VPR128.D.imm_neon_uimm1
is b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR64 & Zd
{
# simd element Rn_VPR128[imm_neon_uimm1] lane size 8
Rd_FPR64 = Rn_VPR128.D.imm_neon_uimm1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.39 DUP (element) page C7-1470 line 81332 MATCH x5e000400/mask=xffe0fc00
# C7.2.199 MOV (scalar) page C7-1854 line 104019 MATCH x5e000400/mask=xffe0fc00
# CONSTRUCT x5e020400/mask=xffe3fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 =ARG2
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2
# AUNIT --inst x5e020400/mask=xffe3fc00 --status pass
:dup Rd_FPR16, Rn_VPR128.H.imm_neon_uimm3
is b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR16 & Zd
{
# simd element Rn_VPR128[imm_neon_uimm3] lane size 2
Rd_FPR16 = Rn_VPR128.H.imm_neon_uimm3;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.39 DUP (element) page C7-1470 line 81332 MATCH x5e000400/mask=xffe0fc00
# C7.2.199 MOV (scalar) page C7-1854 line 104019 MATCH x5e000400/mask=xffe0fc00
# CONSTRUCT x5e040400/mask=xffe7fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 =ARG2
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4
# AUNIT --inst x5e040400/mask=xffe7fc00 --status pass
:dup Rd_FPR32, Rn_VPR128.S.imm_neon_uimm2
is b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR32 & Zd
{
# simd element Rn_VPR128[imm_neon_uimm2] lane size 4
Rd_FPR32 = Rn_VPR128.S.imm_neon_uimm2;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.40 DUP (general) page C7-1473 line 81499 MATCH x0e000c00/mask=xbfe0fc00
# CONSTRUCT x4e010c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(force-primitive) ARG1 ARG2[0]:1 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1
# AUNIT --inst x4e010c00/mask=xffe1fc00 --status pass
:dup Rd_VPR128.16B, Rn_GPR32
is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_16=1 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR128.16B & Zd
{
local tmp1:1 = Rn_GPR32[0,8];
# simd duplicate Rd_VPR128.16B = all elements tmp1 (lane size 1)
Rd_VPR128.16B[0,8] = tmp1;
Rd_VPR128.16B[8,8] = tmp1;
Rd_VPR128.16B[16,8] = tmp1;
Rd_VPR128.16B[24,8] = tmp1;
Rd_VPR128.16B[32,8] = tmp1;
Rd_VPR128.16B[40,8] = tmp1;
Rd_VPR128.16B[48,8] = tmp1;
Rd_VPR128.16B[56,8] = tmp1;
Rd_VPR128.16B[64,8] = tmp1;
Rd_VPR128.16B[72,8] = tmp1;
Rd_VPR128.16B[80,8] = tmp1;
Rd_VPR128.16B[88,8] = tmp1;
Rd_VPR128.16B[96,8] = tmp1;
Rd_VPR128.16B[104,8] = tmp1;
Rd_VPR128.16B[112,8] = tmp1;
Rd_VPR128.16B[120,8] = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.40 DUP (general) page C7-1473 line 81499 MATCH x0e000c00/mask=xbfe0fc00
# CONSTRUCT x4e080c00/mask=xffeffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@8
# AUNIT --inst x4e080c00/mask=xffeffc00 --status pass
:dup Rd_VPR128.2D, Rn_GPR64
is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_1619=0b1000 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR64 & Rd_VPR128.2D & Zd
{
# simd duplicate Rd_VPR128.2D = all elements Rn_GPR64 (lane size 8)
Rd_VPR128.2D[0,64] = Rn_GPR64;
Rd_VPR128.2D[64,64] = Rn_GPR64;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.40 DUP (general) page C7-1473 line 81499 MATCH x0e000c00/mask=xbfe0fc00
# CONSTRUCT x0e040c00/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4
# AUNIT --inst x0e040c00/mask=xffe7fc00 --status pass
:dup Rd_VPR64.2S, Rn_GPR32
is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & b_1618=0b100 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR64.2S & Zd
{
# simd duplicate Rd_VPR64.2S = all elements Rn_GPR32 (lane size 4)
Rd_VPR64.2S[0,32] = Rn_GPR32;
Rd_VPR64.2S[32,32] = Rn_GPR32;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.40 DUP (general) page C7-1473 line 81499 MATCH x0e000c00/mask=xbfe0fc00
# CONSTRUCT x0e020c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[0]:2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2
# AUNIT --inst x0e020c00/mask=xffe3fc00 --status pass
:dup Rd_VPR64.4H, Rn_GPR32
is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & b_1617=0b10 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR64.4H & Zd
{
local tmp1:2 = Rn_GPR32[0,16];
# simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2)
Rd_VPR64.4H[0,16] = tmp1;
Rd_VPR64.4H[16,16] = tmp1;
Rd_VPR64.4H[32,16] = tmp1;
Rd_VPR64.4H[48,16] = tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.40 DUP (general) page C7-1473 line 81499 MATCH x0e000c00/mask=xbfe0fc00
# CONSTRUCT x4e040c00/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4
# AUNIT --inst x4e040c00/mask=xffe7fc00 --status pass
:dup Rd_VPR128.4S, Rn_GPR32
is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_1618=0b100 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR128.4S & Zd
{
# simd duplicate Rd_VPR128.4S = all elements Rn_GPR32 (lane size 4)
Rd_VPR128.4S[0,32] = Rn_GPR32;
Rd_VPR128.4S[32,32] = Rn_GPR32;
Rd_VPR128.4S[64,32] = Rn_GPR32;
Rd_VPR128.4S[96,32] = Rn_GPR32;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.40 DUP (general) page C7-1473 line 81499 MATCH x0e000c00/mask=xbfe0fc00
# CONSTRUCT x0e010c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[0]:1 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1
# AUNIT --inst x0e010c00/mask=xffe1fc00 --status pass
:dup Rd_VPR64.8B, Rn_GPR32
is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & b_16=1 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR64.8B & Zd
{
local tmp1:1 = Rn_GPR32[0,8];
# simd duplicate Rd_VPR64.8B = all elements tmp1 (lane size 1)
Rd_VPR64.8B[0,8] = tmp1;
Rd_VPR64.8B[8,8] = tmp1;
Rd_VPR64.8B[16,8] = tmp1;
Rd_VPR64.8B[24,8] = tmp1;
Rd_VPR64.8B[32,8] = tmp1;
Rd_VPR64.8B[40,8] = tmp1;
Rd_VPR64.8B[48,8] = tmp1;
Rd_VPR64.8B[56,8] = tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.40 DUP (general) page C7-1473 line 81499 MATCH x0e000c00/mask=xbfe0fc00
# CONSTRUCT x4e020c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[0]:2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2
# AUNIT --inst x4e020c00/mask=xffe3fc00 --status pass
:dup Rd_VPR128.8H, Rn_GPR32
is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_1617=0b10 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR128.8H & Zd
{
local tmp1:2 = Rn_GPR32[0,16];
# simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2)
Rd_VPR128.8H[0,16] = tmp1;
Rd_VPR128.8H[16,16] = tmp1;
Rd_VPR128.8H[32,16] = tmp1;
Rd_VPR128.8H[48,16] = tmp1;
Rd_VPR128.8H[64,16] = tmp1;
Rd_VPR128.8H[80,16] = tmp1;
Rd_VPR128.8H[96,16] = tmp1;
Rd_VPR128.8H[112,16] = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.41 EOR (vector) page C7-1475 line 81603 MATCH x2e201c00/mask=xbfe0fc00
# CONSTRUCT x6e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$^@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_eor/2@1
# AUNIT --inst x6e201c00/mask=xffe0fc00 --status pass
:eor Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix Rd_VPR128.16B = Rn_VPR128.16B ^ Rm_VPR128.16B on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] ^ Rm_VPR128.16B[0,8];
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] ^ Rm_VPR128.16B[8,8];
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] ^ Rm_VPR128.16B[16,8];
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] ^ Rm_VPR128.16B[24,8];
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] ^ Rm_VPR128.16B[32,8];
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] ^ Rm_VPR128.16B[40,8];
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] ^ Rm_VPR128.16B[48,8];
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] ^ Rm_VPR128.16B[56,8];
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] ^ Rm_VPR128.16B[64,8];
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] ^ Rm_VPR128.16B[72,8];
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] ^ Rm_VPR128.16B[80,8];
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] ^ Rm_VPR128.16B[88,8];
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] ^ Rm_VPR128.16B[96,8];
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] ^ Rm_VPR128.16B[104,8];
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] ^ Rm_VPR128.16B[112,8];
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] ^ Rm_VPR128.16B[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.41 EOR (vector) page C7-1475 line 81603 MATCH x2e201c00/mask=xbfe0fc00
# CONSTRUCT x2e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$^@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_eor/2@1
# AUNIT --inst x2e201c00/mask=xffe0fc00 --status pass
:eor Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix Rd_VPR64.8B = Rn_VPR64.8B ^ Rm_VPR64.8B on lane size 1
Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] ^ Rm_VPR64.8B[0,8];
Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] ^ Rm_VPR64.8B[8,8];
Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] ^ Rm_VPR64.8B[16,8];
Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] ^ Rm_VPR64.8B[24,8];
Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] ^ Rm_VPR64.8B[32,8];
Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] ^ Rm_VPR64.8B[40,8];
Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] ^ Rm_VPR64.8B[48,8];
Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] ^ Rm_VPR64.8B[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.42 EOR3 page C7-1477 line 81685 MATCH xce000000/mask=xffe08000
# CONSTRUCT xce000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 ARG4 $|@1 =$|@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_eor3/3@1
# AUNIT --inst xce000000/mask=xffe08000 --status noqemu
:eor3 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, Ra_VPR128.16B
is b_2131=0b11001110000 & b_15=0 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Ra_VPR128.16B & Zd
{
# simd infix TMPQ1 = Rm_VPR128.16B | Ra_VPR128.16B on lane size 1
TMPQ1[0,8] = Rm_VPR128.16B[0,8] | Ra_VPR128.16B[0,8];
TMPQ1[8,8] = Rm_VPR128.16B[8,8] | Ra_VPR128.16B[8,8];
TMPQ1[16,8] = Rm_VPR128.16B[16,8] | Ra_VPR128.16B[16,8];
TMPQ1[24,8] = Rm_VPR128.16B[24,8] | Ra_VPR128.16B[24,8];
TMPQ1[32,8] = Rm_VPR128.16B[32,8] | Ra_VPR128.16B[32,8];
TMPQ1[40,8] = Rm_VPR128.16B[40,8] | Ra_VPR128.16B[40,8];
TMPQ1[48,8] = Rm_VPR128.16B[48,8] | Ra_VPR128.16B[48,8];
TMPQ1[56,8] = Rm_VPR128.16B[56,8] | Ra_VPR128.16B[56,8];
TMPQ1[64,8] = Rm_VPR128.16B[64,8] | Ra_VPR128.16B[64,8];
TMPQ1[72,8] = Rm_VPR128.16B[72,8] | Ra_VPR128.16B[72,8];
TMPQ1[80,8] = Rm_VPR128.16B[80,8] | Ra_VPR128.16B[80,8];
TMPQ1[88,8] = Rm_VPR128.16B[88,8] | Ra_VPR128.16B[88,8];
TMPQ1[96,8] = Rm_VPR128.16B[96,8] | Ra_VPR128.16B[96,8];
TMPQ1[104,8] = Rm_VPR128.16B[104,8] | Ra_VPR128.16B[104,8];
TMPQ1[112,8] = Rm_VPR128.16B[112,8] | Ra_VPR128.16B[112,8];
TMPQ1[120,8] = Rm_VPR128.16B[120,8] | Ra_VPR128.16B[120,8];
# simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ1 on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ1[0,8];
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ1[8,8];
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ1[16,8];
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ1[24,8];
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ1[32,8];
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ1[40,8];
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ1[48,8];
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ1[56,8];
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ1[64,8];
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ1[72,8];
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ1[80,8];
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ1[88,8];
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ1[96,8];
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ1[104,8];
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ1[112,8];
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.43 EXT page C7-1478 line 81756 MATCH x2e000000/mask=xbfe08400
# CONSTRUCT x6e000000/mask=xffe08400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 imm4:1 =NEON_ext/3@1
# AUNIT --inst x6e000000/mask=xffe08400 --status nopcodeop
:ext Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, imm4
is b_3131=0 & q=1 & b_2429=0x2e & b_2223=0b00 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & imm4 & b_1010=0 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_ext(Rn_VPR128.16B, Rm_VPR128.16B, imm4:1, 1:1);
}
# C7.2.43 EXT page C7-1478 line 81756 MATCH x2e000000/mask=xbfe08400
# CONSTRUCT x2e000000/mask=xffe0c400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 imm4:1 =NEON_ext/3@1
# AUNIT --inst x2e000000/mask=xffe0c400 --status nopcodeop
:ext Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, imm4
is b_3131=0 & q=0 & b_2429=0x2e & b_2223=0b00 & b_2121=0 & Rm_VPR64.8B & b_1415=0 & imm4 & b_1010=0 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_ext(Rn_VPR64.8B, Rm_VPR64.8B, imm4:1, 1:1);
}
# C7.2.44 FABD page C7-1480 line 81859 MATCH x2ec01400/mask=xbfe0fc00
# CONSTRUCT x2ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f-@2 =$fabs@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@2
# AUNIT --inst x2ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant when Q=0 sz=1 bb=0 cc=00 F=VPR64.4H
:fabd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=1 & b_21=0 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
# simd infix TMPD1 = Rn_VPR64.4H f- Rm_VPR64.4H on lane size 2
TMPD1[0,16] = Rn_VPR64.4H[0,16] f- Rm_VPR64.4H[0,16];
TMPD1[16,16] = Rn_VPR64.4H[16,16] f- Rm_VPR64.4H[16,16];
TMPD1[32,16] = Rn_VPR64.4H[32,16] f- Rm_VPR64.4H[32,16];
TMPD1[48,16] = Rn_VPR64.4H[48,16] f- Rm_VPR64.4H[48,16];
# simd unary Rd_VPR64.4H = abs(TMPD1) on lane size 2
Rd_VPR64.4H[0,16] = abs(TMPD1[0,16]);
Rd_VPR64.4H[16,16] = abs(TMPD1[16,16]);
Rd_VPR64.4H[32,16] = abs(TMPD1[32,16]);
Rd_VPR64.4H[48,16] = abs(TMPD1[48,16]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.44 FABD page C7-1480 line 81859 MATCH x2ec01400/mask=xbfe0fc00
# CONSTRUCT x6ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f-@2 =$fabs@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@2
# AUNIT --inst x6ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant when Q=1 sz=1 bb=0 cc=00 F=VPR128.8H
:fabd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_21=0 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H f- Rm_VPR128.8H on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] f- Rm_VPR128.8H[0,16];
TMPQ1[16,16] = Rn_VPR128.8H[16,16] f- Rm_VPR128.8H[16,16];
TMPQ1[32,16] = Rn_VPR128.8H[32,16] f- Rm_VPR128.8H[32,16];
TMPQ1[48,16] = Rn_VPR128.8H[48,16] f- Rm_VPR128.8H[48,16];
TMPQ1[64,16] = Rn_VPR128.8H[64,16] f- Rm_VPR128.8H[64,16];
TMPQ1[80,16] = Rn_VPR128.8H[80,16] f- Rm_VPR128.8H[80,16];
TMPQ1[96,16] = Rn_VPR128.8H[96,16] f- Rm_VPR128.8H[96,16];
TMPQ1[112,16] = Rn_VPR128.8H[112,16] f- Rm_VPR128.8H[112,16];
# simd unary Rd_VPR128.8H = abs(TMPQ1) on lane size 2
Rd_VPR128.8H[0,16] = abs(TMPQ1[0,16]);
Rd_VPR128.8H[16,16] = abs(TMPQ1[16,16]);
Rd_VPR128.8H[32,16] = abs(TMPQ1[32,16]);
Rd_VPR128.8H[48,16] = abs(TMPQ1[48,16]);
Rd_VPR128.8H[64,16] = abs(TMPQ1[64,16]);
Rd_VPR128.8H[80,16] = abs(TMPQ1[80,16]);
Rd_VPR128.8H[96,16] = abs(TMPQ1[96,16]);
Rd_VPR128.8H[112,16] = abs(TMPQ1[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.44 FABD page C7-1480 line 81859 MATCH x2ea0d400/mask=xbfa0fc00
# CONSTRUCT x2ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f-@4 =$fabs@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@4
# AUNIT --inst x2ea0d400/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
# Vector half precision variant when Q=0 sz=0 bb=1 cc=11 F=VPR64.2S
:fabd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110101 & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd
{
# simd infix TMPD1 = Rn_VPR64.2S f- Rm_VPR64.2S on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] f- Rm_VPR64.2S[0,32];
TMPD1[32,32] = Rn_VPR64.2S[32,32] f- Rm_VPR64.2S[32,32];
# simd unary Rd_VPR64.2S = abs(TMPD1) on lane size 4
Rd_VPR64.2S[0,32] = abs(TMPD1[0,32]);
Rd_VPR64.2S[32,32] = abs(TMPD1[32,32]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.44 FABD page C7-1480 line 81859 MATCH x2ea0d400/mask=xbfa0fc00
# CONSTRUCT x6ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f-@4 =$fabs@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@4
# AUNIT --inst x6ea0d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
# Vector half precision variant when Q=1 sz=0 bb=1 cc=11 F=VPR128.4S
:fabd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110101 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S f- Rm_VPR128.4S on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] f- Rm_VPR128.4S[0,32];
TMPQ1[32,32] = Rn_VPR128.4S[32,32] f- Rm_VPR128.4S[32,32];
TMPQ1[64,32] = Rn_VPR128.4S[64,32] f- Rm_VPR128.4S[64,32];
TMPQ1[96,32] = Rn_VPR128.4S[96,32] f- Rm_VPR128.4S[96,32];
# simd unary Rd_VPR128.4S = abs(TMPQ1) on lane size 4
Rd_VPR128.4S[0,32] = abs(TMPQ1[0,32]);
Rd_VPR128.4S[32,32] = abs(TMPQ1[32,32]);
Rd_VPR128.4S[64,32] = abs(TMPQ1[64,32]);
Rd_VPR128.4S[96,32] = abs(TMPQ1[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.44 FABD page C7-1480 line 81859 MATCH x2ea0d400/mask=xbfa0fc00
# CONSTRUCT x6ee0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f-@8 =$fabs@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@8
# AUNIT --inst x6ee0d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
# Vector half precision variant when Q=1 sz=1 bb=1 cc=11 F=VPR128.2D
:fabd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_21=1 & b_1015=0b110101 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
{
# simd infix TMPQ1 = Rn_VPR128.2D f- Rm_VPR128.2D on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] f- Rm_VPR128.2D[0,64];
TMPQ1[64,64] = Rn_VPR128.2D[64,64] f- Rm_VPR128.2D[64,64];
# simd unary Rd_VPR128.2D = abs(TMPQ1) on lane size 8
Rd_VPR128.2D[0,64] = abs(TMPQ1[0,64]);
Rd_VPR128.2D[64,64] = abs(TMPQ1[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.44 FABD page C7-1480 line 81859 MATCH x7ec01400/mask=xffe0fc00
# CONSTRUCT x7ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f- =fabs
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2
# AUNIT --inst x7ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Scalar half precision variant when sz=1 bb=0 cc=00 F=FPR16
:fabd Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_2131=0b01111110110 & b_1015=0b000101 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
{
local tmp1:2 = Rn_FPR16 f- Rm_FPR16;
Rd_FPR16 = abs(tmp1);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.44 FABD page C7-1480 line 81859 MATCH x7ea0d400/mask=xffa0fc00
# CONSTRUCT x7ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f- =fabs
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2
# AUNIT --inst x7ea0d400/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
# Scalar half precision variant when sz=0 bb=1 cc=11 F=FPR32
:fabd Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_2131=0b01111110101 & b_1015=0b110101 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
{
local tmp1:4 = Rn_FPR32 f- Rm_FPR32;
Rd_FPR32 = abs(tmp1);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.44 FABD page C7-1480 line 81859 MATCH x7ea0d400/mask=xffa0fc00
# CONSTRUCT x7ee0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f- =fabs
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2
# AUNIT --inst x7ee0d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
# Scalar half precision variant when sz=1 bb=1 cc=11 F=FPR64
:fabd Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_2131=0b01111110111 & b_1015=0b110101 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
local tmp1:8 = Rn_FPR64 f- Rm_FPR64;
Rd_FPR64 = abs(tmp1);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.45 FABS (vector) page C7-1483 line 82050 MATCH x0ea0f800/mask=xbfbffc00
# CONSTRUCT x4ee0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$fabs@8
# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@8
# AUNIT --inst x4ee0f800/mask=xfffffc00 --rand dfp --status pass
:fabs Rd_VPR128.2D, Rn_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd unary Rd_VPR128.2D = abs(Rn_VPR128.2D) on lane size 8
Rd_VPR128.2D[0,64] = abs(Rn_VPR128.2D[0,64]);
Rd_VPR128.2D[64,64] = abs(Rn_VPR128.2D[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.45 FABS (vector) page C7-1483 line 82050 MATCH x0ea0f800/mask=xbfbffc00
# CONSTRUCT x0ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$fabs@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@4
# AUNIT --inst x0ea0f800/mask=xfffffc00 --rand sfp --status pass
:fabs Rd_VPR64.2S, Rn_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd unary Rd_VPR64.2S = abs(Rn_VPR64.2S) on lane size 4
Rd_VPR64.2S[0,32] = abs(Rn_VPR64.2S[0,32]);
Rd_VPR64.2S[32,32] = abs(Rn_VPR64.2S[32,32]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.45 FABS (vector) page C7-1483 line 82050 MATCH x0ea0f800/mask=xbfbffc00
# CONSTRUCT x4ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$fabs@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@4
# AUNIT --inst x4ea0f800/mask=xfffffc00 --rand sfp --status pass
:fabs Rd_VPR128.4S, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd unary Rd_VPR128.4S = abs(Rn_VPR128.4S) on lane size 4
Rd_VPR128.4S[0,32] = abs(Rn_VPR128.4S[0,32]);
Rd_VPR128.4S[32,32] = abs(Rn_VPR128.4S[32,32]);
Rd_VPR128.4S[64,32] = abs(Rn_VPR128.4S[64,32]);
Rd_VPR128.4S[96,32] = abs(Rn_VPR128.4S[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.45 FABS (vector) page C7-1483 line 82050 MATCH x0ef8f800/mask=xbffffc00
# CONSTRUCT x0ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$fabs@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@2
# AUNIT --inst x0ef8f800/mask=xfffffc00 --rand hfp --status noqemu
# FABS (vector) SIMD 4H when size=0 Q=0
:fabs Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_1029=0b00111011111000111110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
# simd unary Rd_VPR64.4H = abs(Rn_VPR64.4H) on lane size 2
Rd_VPR64.4H[0,16] = abs(Rn_VPR64.4H[0,16]);
Rd_VPR64.4H[16,16] = abs(Rn_VPR64.4H[16,16]);
Rd_VPR64.4H[32,16] = abs(Rn_VPR64.4H[32,16]);
Rd_VPR64.4H[48,16] = abs(Rn_VPR64.4H[48,16]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.45 FABS (vector) page C7-1483 line 82050 MATCH x0ef8f800/mask=xbffffc00
# CONSTRUCT x4ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$fabs@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@2
# AUNIT --inst x4ef8f800/mask=xfffffc00 --rand hfp --status noqemu
# FABS (vector) SIMD 8H when size=0 Q=1
:fabs Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_1029=0b00111011111000111110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
# simd unary Rd_VPR128.8H = abs(Rn_VPR128.8H) on lane size 2
Rd_VPR128.8H[0,16] = abs(Rn_VPR128.8H[0,16]);
Rd_VPR128.8H[16,16] = abs(Rn_VPR128.8H[16,16]);
Rd_VPR128.8H[32,16] = abs(Rn_VPR128.8H[32,16]);
Rd_VPR128.8H[48,16] = abs(Rn_VPR128.8H[48,16]);
Rd_VPR128.8H[64,16] = abs(Rn_VPR128.8H[64,16]);
Rd_VPR128.8H[80,16] = abs(Rn_VPR128.8H[80,16]);
Rd_VPR128.8H[96,16] = abs(Rn_VPR128.8H[96,16]);
Rd_VPR128.8H[112,16] = abs(Rn_VPR128.8H[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.46 FABS (scalar) page C7-1485 line 82158 MATCH x1e20c000/mask=xff3ffc00
# CONSTRUCT x1ee0c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =fabs
# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1
# AUNIT --inst x1ee0c000/mask=xfffffc00 --rand hfp --status noqemu
:fabs Rd_FPR16, Rn_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x1 & b_1014=0x10 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = abs(Rn_FPR16);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.46 FABS (scalar) page C7-1485 line 82158 MATCH x1e20c000/mask=xff3ffc00
# CONSTRUCT x1e60c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =fabs
# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1
# AUNIT --inst x1e60c000/mask=xfffffc00 --rand dfp --status pass
:fabs Rd_FPR64, Rn_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x1 & b_1014=0x10 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = abs(Rn_FPR64);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.46 FABS (scalar) page C7-1485 line 82158 MATCH x1e20c000/mask=xff3ffc00
# CONSTRUCT x1e20c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =fabs
# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1
# AUNIT --inst x1e20c000/mask=xfffffc00 --rand sfp --status pass
:fabs Rd_FPR32, Rn_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x1 & b_1014=0x10 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = abs(Rn_FPR32);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.47 FACGE page C7-1487 line 82250 MATCH x2e20ec00/mask=xbfa0fc00
# CONSTRUCT x6e60ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@8
# AUNIT --inst x6e60ec00/mask=xffe0fc00 --rand dfp --status nopcodeop
:facge Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1d & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_facge(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.47 FACGE page C7-1487 line 82250 MATCH x2e20ec00/mask=xbfa0fc00
# CONSTRUCT x2e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@4
# AUNIT --inst x2e20ec00/mask=xffe0fc00 --rand sfp --status nopcodeop
:facge Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1d & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_facge(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.47 FACGE page C7-1487 line 82250 MATCH x2e20ec00/mask=xbfa0fc00
# CONSTRUCT x6e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@4
# AUNIT --inst x6e20ec00/mask=xffe0fc00 --rand sfp --status nopcodeop
:facge Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1d & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_facge(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.47 FACGE page C7-1487 line 82250 MATCH x7e402c00/mask=xffe0fc00
# CONSTRUCT x7e402c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2
# AUNIT --inst x7e402c00/mask=xffe0fc00 --rand hfp --status noqemu
# Scalar half precision
:facge Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_2131=0b01111110010 & b_1015=0b001011 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
{
Rd_FPR16 = NEON_facge(Rn_FPR16, Rm_FPR16);
}
# C7.2.47 FACGE page C7-1487 line 82250 MATCH x7e20ec00/mask=xffa0fc00
# CONSTRUCT x7e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2
# AUNIT --inst x7e20ec00/mask=xffe0fc00 --rand sfp --status nopcodeop
# Scalar single-precision and double-precision sz=0
:facge Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_2331=0b011111100 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
{
Rd_FPR32 = NEON_facge(Rn_FPR32, Rm_FPR32);
}
# C7.2.47 FACGE page C7-1487 line 82250 MATCH x7e20ec00/mask=xffa0fc00
# CONSTRUCT x7e60ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2
# AUNIT --inst x7e60ec00/mask=xffe0fc00 --rand dfp --status nopcodeop
# Scalar single-precision and double-precision sz=1
:facge Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_2331=0b011111100 & b_22=1 & b_21=1 & b_1015=0b111011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
Rd_FPR64 = NEON_facge(Rn_FPR64, Rm_FPR64);
}
# C7.2.47 FACGE page C7-1487 line 82250 MATCH x2e402c00/mask=xbfe0fc00
# CONSTRUCT x2e402c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@2
# AUNIT --inst x2e402c00/mask=xffe0fc00 --rand hfp --status noqemu
# FACGE SIMD 4H when size=0 Q=0
:facge Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_facge(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.47 FACGE page C7-1487 line 82250 MATCH x2e402c00/mask=xbfe0fc00
# CONSTRUCT x6e402c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@2
# AUNIT --inst x6e402c00/mask=xffe0fc00 --rand hfp --status noqemu
# FACGE SIMD 8H when size=0 Q=1
:facge Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_facge(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.48 FACGT page C7-1491 line 82494 MATCH x2ea0ec00/mask=xbfa0fc00
# CONSTRUCT x6ee0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@8
# AUNIT --inst x6ee0ec00/mask=xffe0fc00 --rand dfp --status nopcodeop
:facgt Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1d & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_facgt(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.48 FACGT page C7-1491 line 82494 MATCH x2ea0ec00/mask=xbfa0fc00
# CONSTRUCT x2ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@4
# AUNIT --inst x2ea0ec00/mask=xffe0fc00 --rand sfp --status nopcodeop
:facgt Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1d & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_facgt(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.48 FACGT page C7-1491 line 82494 MATCH x2ea0ec00/mask=xbfa0fc00
# CONSTRUCT x6ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@4
# AUNIT --inst x6ea0ec00/mask=xffe0fc00 --rand sfp --status nopcodeop
:facgt Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1d & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_facgt(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.48 FACGT page C7-1491 line 82494 MATCH x7ec02c00/mask=xffe0fc00
# CONSTRUCT x7ec02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2
# AUNIT --inst x7ec02c00/mask=xffe0fc00 --rand hfp --status noqemu
# Scalar half precision
:facgt Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_2131=0b01111110110 & b_1015=0b001011 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
{
Rd_FPR16 = NEON_facgt(Rn_FPR16, Rm_FPR16);
}
# C7.2.48 FACGT page C7-1491 line 82494 MATCH x7ea0ec00/mask=xffa0fc00
# CONSTRUCT x7ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2
# AUNIT --inst x7ea0ec00/mask=xffe0fc00 --rand sfp --status nopcodeop
# Scalar single-precision and double-precision sz=0
:facgt Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_2331=0b011111101 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
{
Rd_FPR32 = NEON_facgt(Rn_FPR32, Rm_FPR32);
}
# C7.2.48 FACGT page C7-1491 line 82494 MATCH x7ea0ec00/mask=xffa0fc00
# CONSTRUCT x7ee0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2
# AUNIT --inst x7ee0ec00/mask=xffe0fc00 --rand dfp --status nopcodeop
# Scalar single-precision and double-precision sz=1
:facgt Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_2331=0b011111101 & b_22=1 & b_21=1 & b_1015=0b111011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
Rd_FPR64 = NEON_facgt(Rn_FPR64, Rm_FPR64);
}
# C7.2.48 FACGT page C7-1491 line 82494 MATCH x2ec02c00/mask=xbfe0fc00
# CONSTRUCT x2ec02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@2
# AUNIT --inst x2ec02c00/mask=xffe0fc00 --rand hfp --status noqemu
# Vector half-precision SIMD 4H when Q=0
:facgt Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b001011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_facgt(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.48 FACGT page C7-1491 line 82494 MATCH x2ec02c00/mask=xbfe0fc00
# CONSTRUCT x6ec02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@2
# AUNIT --inst x6ec02c00/mask=xffe0fc00 --rand hfp --status noqemu
# Vector half-precision SIMD 8H when Q=1
:facgt Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b001011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_facgt(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.49 FADD (vector) page C7-1495 line 82738 MATCH x0e20d400/mask=xbfa0fc00
# CONSTRUCT x4e60d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@8
# AUNIT --inst x4e60d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
:fadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1a & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd infix Rd_VPR128.2D = Rn_VPR128.2D f+ Rm_VPR128.2D on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f+ Rm_VPR128.2D[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f+ Rm_VPR128.2D[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.49 FADD (vector) page C7-1495 line 82738 MATCH x0e20d400/mask=xbfa0fc00
# CONSTRUCT x0e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@4
# AUNIT --inst x0e20d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
:fadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1a & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix Rd_VPR64.2S = Rn_VPR64.2S f+ Rm_VPR64.2S on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f+ Rm_VPR64.2S[0,32];
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f+ Rm_VPR64.2S[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.49 FADD (vector) page C7-1495 line 82738 MATCH x0e20d400/mask=xbfa0fc00
# CONSTRUCT x4e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@4
# AUNIT --inst x4e20d400/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
:fadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1a & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd infix Rd_VPR128.4S = Rn_VPR128.4S f+ Rm_VPR128.4S on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f+ Rm_VPR128.4S[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f+ Rm_VPR128.4S[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f+ Rm_VPR128.4S[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f+ Rm_VPR128.4S[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.49 FADD (vector) page C7-1495 line 82738 MATCH x0e401400/mask=xbfe0fc00
# CONSTRUCT x0e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@2
# AUNIT --inst x0e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision SIMD 4H when Q=0
:fadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
# simd infix Rd_VPR64.4H = Rn_VPR64.4H f+ Rm_VPR64.4H on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f+ Rm_VPR64.4H[0,16];
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f+ Rm_VPR64.4H[16,16];
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f+ Rm_VPR64.4H[32,16];
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f+ Rm_VPR64.4H[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.49 FADD (vector) page C7-1495 line 82738 MATCH x0e401400/mask=xbfe0fc00
# CONSTRUCT x4e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@2
# AUNIT --inst x4e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision SIMD 8H when Q=1
:fadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
# simd infix Rd_VPR128.8H = Rn_VPR128.8H f+ Rm_VPR128.8H on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f+ Rm_VPR128.8H[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f+ Rm_VPR128.8H[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f+ Rm_VPR128.8H[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f+ Rm_VPR128.8H[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f+ Rm_VPR128.8H[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f+ Rm_VPR128.8H[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f+ Rm_VPR128.8H[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f+ Rm_VPR128.8H[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.50 FADD (scalar) page C7-1497 line 82859 MATCH x1e202800/mask=xff20fc00
# CONSTRUCT x1e602800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f+
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2
# AUNIT --inst x1e602800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
:fadd Rd_FPR64, Rn_FPR64, Rm_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x2 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = Rn_FPR64 f+ Rm_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.50 FADD (scalar) page C7-1497 line 82859 MATCH x1e202800/mask=xff20fc00
# CONSTRUCT x1ee02800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f+
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2
# AUNIT --inst x1ee02800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
:fadd Rd_FPR16, Rn_FPR16, Rm_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x2 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = Rn_FPR16 f+ Rm_FPR16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.50 FADD (scalar) page C7-1497 line 82859 MATCH x1e202800/mask=xff20fc00
# CONSTRUCT x1e202800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f+
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2
# AUNIT --inst x1e202800/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
:fadd Rd_FPR32, Rn_FPR32, Rm_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x2 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = Rn_FPR32 f+ Rm_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.51 FADDP (scalar) page C7-1499 line 82962 MATCH x7e30d800/mask=xffbffc00
# CONSTRUCT x7e70d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =#f+
# SMACRO(pseudo) ARG1 ARG2 =NEON_faddp/1@8
# AUNIT --inst x7e70d800/mask=xfffffc00 --rand dfp --status pass --comment "nofpround"
:faddp Rd_FPR64, Rn_VPR128.2D
is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x38 & b_1216=0xd & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd
{
# sipd infix Rd_FPR64 = f+(Rn_VPR128.2D) on pairs lane size (8 to 8)
tmp1 = Rn_VPR128.2D[0,64];
tmp2 = Rn_VPR128.2D[64,64];
Rd_FPR64[0,64] = tmp1 f+ tmp2;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.51 FADDP (scalar) page C7-1499 line 82962 MATCH x7e30d800/mask=xffbffc00
# CONSTRUCT x7e30d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =#f+
# SMACRO(pseudo) ARG1 ARG2 =NEON_faddp/1@4
# AUNIT --inst x7e30d800/mask=xfffffc00 --rand sfp --status pass --comment "nofpround"
:faddp Rd_FPR32, Rn_VPR64.2S
is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x18 & b_1216=0xd & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd
{
# sipd infix Rd_FPR32 = f+(Rn_VPR64.2S) on pairs lane size (4 to 4)
tmp1 = Rn_VPR64.2S[0,32];
tmp2 = Rn_VPR64.2S[32,32];
Rd_FPR32[0,32] = tmp1 f+ tmp2;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.51 FADDP (scalar) page C7-1499 line 82962 MATCH x5e30d800/mask=xfffffc00
# CONSTRUCT x5e30d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_FPR32 =#f+@2
# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_faddp/1@2
# AUNIT --inst x5e30d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant
:faddp Rd_FPR16, vRn_VPR128^".2H"
is b_1031=0b0101111000110000110110 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd
{
# sipd infix Rd_FPR16 = f+(Rn_FPR32) on pairs lane size (2 to 2)
tmp1 = Rn_FPR32[0,16];
tmp2 = Rn_FPR32[16,16];
Rd_FPR16[0,16] = tmp1 f+ tmp2;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.52 FADDP (vector) page C7-1501 line 83067 MATCH x2e20d400/mask=xbfa0fc00
# CONSTRUCT x6e60d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 ARG3 =#f+/2 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@8
# AUNIT --inst x6e60d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
:faddp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1a & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = f+(Rn_VPR128.2D,Rm_VPR128.2D) on pairs lane size (8 to 8)
tmp2 = Rn_VPR128.2D[0,64];
tmp3 = Rn_VPR128.2D[64,64];
TMPQ1[0,64] = tmp2 f+ tmp3;
tmp2 = Rm_VPR128.2D[0,64];
tmp3 = Rm_VPR128.2D[64,64];
TMPQ1[64,64] = tmp2 f+ tmp3;
Rd_VPR128.2D = TMPQ1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.52 FADDP (vector) page C7-1501 line 83067 MATCH x2e20d400/mask=xbfa0fc00
# CONSTRUCT x2e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:8 ARG2 ARG3 =#f+/2 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@4
# AUNIT --inst x2e20d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
:faddp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1a & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
TMPD1 = 0;
# sipd infix TMPD1 = f+(Rn_VPR64.2S,Rm_VPR64.2S) on pairs lane size (4 to 4)
tmp2 = Rn_VPR64.2S[0,32];
tmp3 = Rn_VPR64.2S[32,32];
TMPD1[0,32] = tmp2 f+ tmp3;
tmp2 = Rm_VPR64.2S[0,32];
tmp3 = Rm_VPR64.2S[32,32];
TMPD1[32,32] = tmp2 f+ tmp3;
Rd_VPR64.2S = TMPD1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.52 FADDP (vector) page C7-1501 line 83067 MATCH x2e20d400/mask=xbfa0fc00
# CONSTRUCT x6e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 ARG3 =#f+/2 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@4
# AUNIT --inst x6e20d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
:faddp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1a & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = f+(Rn_VPR128.4S,Rm_VPR128.4S) on pairs lane size (4 to 4)
tmp2 = Rn_VPR128.4S[0,32];
tmp3 = Rn_VPR128.4S[32,32];
TMPQ1[0,32] = tmp2 f+ tmp3;
tmp2 = Rn_VPR128.4S[64,32];
tmp3 = Rn_VPR128.4S[96,32];
TMPQ1[32,32] = tmp2 f+ tmp3;
tmp2 = Rm_VPR128.4S[0,32];
tmp3 = Rm_VPR128.4S[32,32];
TMPQ1[64,32] = tmp2 f+ tmp3;
tmp2 = Rm_VPR128.4S[64,32];
tmp3 = Rm_VPR128.4S[96,32];
TMPQ1[96,32] = tmp2 f+ tmp3;
Rd_VPR128.4S = TMPQ1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.52 FADDP (vector) page C7-1501 line 83067 MATCH x2e401400/mask=xbfe0fc00
# CONSTRUCT x2e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:8 ARG3 ARG2 =#f+/2 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@2
# AUNIT --inst x2e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision SIMD 4H when Q = 0
:faddp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
TMPD1 = 0;
# sipd infix TMPD1 = f+(Rm_VPR64.4H,Rn_VPR64.4H) on pairs lane size (2 to 2)
tmp2 = Rm_VPR64.4H[0,16];
tmp3 = Rm_VPR64.4H[16,16];
TMPD1[0,16] = tmp2 f+ tmp3;
tmp2 = Rm_VPR64.4H[32,16];
tmp3 = Rm_VPR64.4H[48,16];
TMPD1[16,16] = tmp2 f+ tmp3;
tmp2 = Rn_VPR64.4H[0,16];
tmp3 = Rn_VPR64.4H[16,16];
TMPD1[32,16] = tmp2 f+ tmp3;
tmp2 = Rn_VPR64.4H[32,16];
tmp3 = Rn_VPR64.4H[48,16];
TMPD1[48,16] = tmp2 f+ tmp3;
Rd_VPR64.4H = TMPD1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.52 FADDP (vector) page C7-1501 line 83067 MATCH x2e401400/mask=xbfe0fc00
# CONSTRUCT x6e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 ARG3 =#f+/2 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@2
# AUNIT --inst x6e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision SIMD 8H when Q = 1
:faddp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = f+(Rn_VPR128.8H,Rm_VPR128.8H) on pairs lane size (2 to 2)
tmp2 = Rn_VPR128.8H[0,16];
tmp3 = Rn_VPR128.8H[16,16];
TMPQ1[0,16] = tmp2 f+ tmp3;
tmp2 = Rn_VPR128.8H[32,16];
tmp3 = Rn_VPR128.8H[48,16];
TMPQ1[16,16] = tmp2 f+ tmp3;
tmp2 = Rn_VPR128.8H[64,16];
tmp3 = Rn_VPR128.8H[80,16];
TMPQ1[32,16] = tmp2 f+ tmp3;
tmp2 = Rn_VPR128.8H[96,16];
tmp3 = Rn_VPR128.8H[112,16];
TMPQ1[48,16] = tmp2 f+ tmp3;
tmp2 = Rm_VPR128.8H[0,16];
tmp3 = Rm_VPR128.8H[16,16];
TMPQ1[64,16] = tmp2 f+ tmp3;
tmp2 = Rm_VPR128.8H[32,16];
tmp3 = Rm_VPR128.8H[48,16];
TMPQ1[80,16] = tmp2 f+ tmp3;
tmp2 = Rm_VPR128.8H[64,16];
tmp3 = Rm_VPR128.8H[80,16];
TMPQ1[96,16] = tmp2 f+ tmp3;
tmp2 = Rm_VPR128.8H[96,16];
tmp3 = Rm_VPR128.8H[112,16];
TMPQ1[112,16] = tmp2 f+ tmp3;
Rd_VPR128.8H = TMPQ1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.46 FCADD page C7-1090 line 63037 KEEPWITH
fcadd_rotate: #90 is b_12=0 { export 90:1; }
fcadd_rotate: #270 is b_12=1 { export 270:1; }
# C7.2.53 FCADD page C7-1503 line 83189 MATCH x2e00e400/mask=xbf20ec00
# CONSTRUCT x2e40e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@2
# AUNIT --inst x2e40e400/mask=xffe0ec00 --rand hfp --status noqemu --comment "nofpround"
# FCADD SIMD 4H when size = 01 , Q = 0
:fcadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, fcadd_rotate
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fcadd(Rn_VPR64.4H, Rm_VPR64.4H, fcadd_rotate, 2:1);
}
# C7.2.53 FCADD page C7-1503 line 83189 MATCH x2e00e400/mask=xbf20ec00
# CONSTRUCT x6e40e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@2
# AUNIT --inst x6e40e400/mask=xffe0ec00 --rand hfp --status noqemu --comment "nofpround"
# FCADD SIMD 8H when size = 01 , Q = 1
:fcadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, fcadd_rotate
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fcadd(Rn_VPR128.8H, Rm_VPR128.8H, fcadd_rotate, 2:1);
}
# C7.2.53 FCADD page C7-1503 line 83189 MATCH x2e00e400/mask=xbf20ec00
# CONSTRUCT x2e80e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@4
# AUNIT --inst x2e80e400/mask=xffe0ec00 --rand sfp --status noqemu --comment "nofpround"
# FCADD SIMD 2S when size = 10 , Q = 0
:fcadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, fcadd_rotate
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fcadd(Rn_VPR64.2S, Rm_VPR64.2S, fcadd_rotate, 4:1);
}
# C7.2.53 FCADD page C7-1503 line 83189 MATCH x2e00e400/mask=xbf20ec00
# CONSTRUCT x6e80e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@4
# AUNIT --inst x6e80e400/mask=xffe0ec00 --rand sfp --status noqemu --comment "nofpround"
# FCADD SIMD 4S when size = 10 , Q = 1
:fcadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, fcadd_rotate
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fcadd(Rn_VPR128.4S, Rm_VPR128.4S, fcadd_rotate, 4:1);
}
# C7.2.53 FCADD page C7-1503 line 83189 MATCH x2e00e400/mask=xbf20ec00
# CONSTRUCT x6ec0e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@8
# AUNIT --inst x6ec0e400/mask=xffe0ec00 --rand dfp --status noqemu --comment "nofpround"
# FCADD SIMD 2D when size = 11 , Q = 1
:fcadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, fcadd_rotate
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fcadd(Rn_VPR128.2D, Rm_VPR128.2D, fcadd_rotate, 8:1);
}
# C7.2.54 FCCMP page C7-1505 line 83301 MATCH x1e200400/mask=xff200c10
# CONSTRUCT x1e600400/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmp/4
# AUNIT --inst x1e600400/mask=xffe00c10 --rand dfp --status nodest --comment "flags"
:fccmp Rn_FPR64, Rm_FPR64, NZCVImm_uimm4, CondOp
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & CondOp & b_1011=1 & Rn_FPR64 & fpccmp.op=0 & NZCVImm_uimm4
{
setCC_NZCV(NZCVImm_uimm4:1);
local tmp1:1 = ! CondOp:1;
if (tmp1) goto inst_next;
fcomp(Rn_FPR64, Rm_FPR64);
}
# C7.2.54 FCCMP page C7-1505 line 83301 MATCH x1e200400/mask=xff200c10
# CONSTRUCT x1e200400/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmp/4
# AUNIT --inst x1e200400/mask=xffe00c10 --rand sfp --status nodest --comment "flags"
:fccmp Rn_FPR32, Rm_FPR32, NZCVImm_uimm4, CondOp
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & CondOp & b_1011=1 & Rn_FPR32 & fpccmp.op=0 & NZCVImm_uimm4
{
setCC_NZCV(NZCVImm_uimm4:1);
local tmp1:1 = ! CondOp:1;
if (tmp1) goto inst_next;
fcomp(Rn_FPR32, Rm_FPR32);
}
# C7.2.54 FCCMP page C7-1505 line 83301 MATCH x1e200400/mask=xff200c10
# CONSTRUCT x1ee00400/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmp/4
# AUNIT --inst x1ee00400/mask=xffe00c10 --rand hfp --status nodest --comment "flags"
:fccmp Rn_FPR16, Rm_FPR16, NZCVImm_uimm4, CondOp
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & CondOp & b_1011=1 & Rn_FPR16 & fpccmp.op=0 & NZCVImm_uimm4
{
setCC_NZCV(NZCVImm_uimm4:1);
local tmp1:1 = ! CondOp:1;
if (tmp1) goto inst_next;
fcomp(Rn_FPR16, Rm_FPR16);
}
# C7.2.55 FCCMPE page C7-1507 line 83416 MATCH x1e200410/mask=xff200c10
# CONSTRUCT x1e600410/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmpe/4
# AUNIT --inst x1e600410/mask=xffe00c10 --rand dfp --status nodest --comment "flags"
:fccmpe Rn_FPR64, Rm_FPR64, NZCVImm_uimm4, CondOp
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & CondOp & b_1011=1 & Rn_FPR64 & fpccmp.op=1 & NZCVImm_uimm4
{
setCC_NZCV(NZCVImm_uimm4:1);
local tmp1:1 = ! CondOp:1;
if (tmp1) goto inst_next;
ftestNAN(Rn_FPR64, Rm_FPR64);
fcomp(Rn_FPR64, Rm_FPR64);
}
# C7.2.55 FCCMPE page C7-1507 line 83416 MATCH x1e200410/mask=xff200c10
# CONSTRUCT x1e200410/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmpe/4
# AUNIT --inst x1e200410/mask=xffe00c10 --rand sfp --status nodest --comment "flags"
:fccmpe Rn_FPR32, Rm_FPR32, NZCVImm_uimm4, CondOp
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & CondOp & b_1011=1 & Rn_FPR32 & fpccmp.op=1 & NZCVImm_uimm4
{
setCC_NZCV(NZCVImm_uimm4:1);
local tmp1:1 = ! CondOp:1;
if (tmp1) goto inst_next;
ftestNAN(Rn_FPR32, Rm_FPR32);
fcomp(Rn_FPR32, Rm_FPR32);
}
# C7.2.55 FCCMPE page C7-1507 line 83416 MATCH x1e200410/mask=xff200c10
# CONSTRUCT x1ee00410/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmpe/4
# AUNIT --inst x1ee00410/mask=xffe00c10 --rand hfp --status nodest --comment "flags"
:fccmpe Rn_FPR16, Rm_FPR16, NZCVImm_uimm4, CondOp
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & CondOp & b_1011=1 & Rn_FPR16 & fpccmp.op=1 & NZCVImm_uimm4
{
setCC_NZCV(NZCVImm_uimm4:1);
local tmp1:1 = ! CondOp:1;
if (tmp1) goto inst_next;
ftestNAN(Rn_FPR16, Rm_FPR16);
fcomp(Rn_FPR16, Rm_FPR16);
}
# C7.2.56 FCMEQ (register) page C7-1509 line 83535 MATCH x0e20e400/mask=xbfa0fc00
# CONSTRUCT x4e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@8
# AUNIT --inst x4e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags"
:fcmeq Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fcmeq(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.56 FCMEQ (register) page C7-1509 line 83535 MATCH x0e20e400/mask=xbfa0fc00
# CONSTRUCT x0e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@4
# AUNIT --inst x0e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmeq Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fcmeq(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.56 FCMEQ (register) page C7-1509 line 83535 MATCH x0e20e400/mask=xbfa0fc00
# CONSTRUCT x4e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@4
# AUNIT --inst x4e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmeq Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fcmeq(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.56 FCMEQ (register) page C7-1509 line 83535 MATCH x5e402400/mask=xffe0fc00
# CONSTRUCT x5e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2
# AUNIT --inst x5e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
# Scalar half precision variant
:fcmeq Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_2131=0b01011110010 & b_1015=0b001001 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
{
Rd_FPR16 = NEON_fcmeq(Rn_FPR16, Rm_FPR16);
}
# C7.2.56 FCMEQ (register) page C7-1509 line 83535 MATCH x5e20e400/mask=xffa0fc00
# CONSTRUCT x5e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2
# AUNIT --inst x5e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision variant sz=0
:fcmeq Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_2331=0b010111100 & b_22=0 & b_21=1 & b_1015=0b111001 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
{
Rd_FPR32 = NEON_fcmeq(Rn_FPR32, Rm_FPR32);
}
# C7.2.56 FCMEQ (register) page C7-1509 line 83535 MATCH x5e20e400/mask=xffa0fc00
# CONSTRUCT x5e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2
# AUNIT --inst x5e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision variant sz=1
:fcmeq Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_2331=0b010111100 & b_22=1 & b_21=1 & b_1015=0b111001 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
Rd_FPR64 = NEON_fcmeq(Rn_FPR64, Rm_FPR64);
}
# C7.2.56 FCMEQ (register) page C7-1509 line 83535 MATCH x0e402400/mask=xbfe0fc00
# CONSTRUCT x0e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@2
# AUNIT --inst x0e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 4H when Q=0
:fcmeq Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b001001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fcmeq(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.56 FCMEQ (register) page C7-1509 line 83535 MATCH x0e402400/mask=xbfe0fc00
# CONSTRUCT x4e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@2
# AUNIT --inst x4e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 8H when Q=1
:fcmeq Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b001001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fcmeq(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.57 FCMEQ (zero) page C7-1513 line 83778 MATCH x0ea0d800/mask=xbfbffc00
# CONSTRUCT x4ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmeq/2@8
# AUNIT --inst x4ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
:fcmeq Rd_VPR128.2D, Rn_VPR128.2D, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xd & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fcmeq(Rn_VPR128.2D, 0:8, 8:1);
}
# C7.2.57 FCMEQ (zero) page C7-1513 line 83778 MATCH x0ea0d800/mask=xbfbffc00
# CONSTRUCT x0ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmeq/2@4
# AUNIT --inst x0ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmeq Rd_VPR64.2S, Rn_VPR64.2S, "#0"
is b_3131=0 & q=0 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fcmeq(Rn_VPR64.2S, 0:4, 4:1);
}
# C7.2.57 FCMEQ (zero) page C7-1513 line 83778 MATCH x0ea0d800/mask=xbfbffc00
# CONSTRUCT x4ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmeq/2@4
# AUNIT --inst x4ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmeq Rd_VPR128.4S, Rn_VPR128.4S, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fcmeq(Rn_VPR128.4S, 0:4, 4:1);
}
# C7.2.57 FCMEQ (zero) page C7-1513 line 83778 MATCH x5ef8d800/mask=xfffffc00
# CONSTRUCT x5ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmeq/2
# AUNIT --inst x5ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Scalar half precision variant
:fcmeq Rd_FPR16, Rn_FPR16, "#0.0"
is b_1031=0b0101111011111000110110 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = NEON_fcmeq(Rn_FPR16, 0:2);
}
# C7.2.57 FCMEQ (zero) page C7-1513 line 83778 MATCH x5ea0d800/mask=xffbffc00
# CONSTRUCT x5ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmeq/2
# AUNIT --inst x5ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision sz=0
:fcmeq Rd_FPR32, Rn_FPR32, "#0.0"
is b_2331=0b010111101 & b_22=0 & b_1021=0b100000110110 & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = NEON_fcmeq(Rn_FPR32, 0:4);
}
# C7.2.57 FCMEQ (zero) page C7-1513 line 83778 MATCH x5ea0d800/mask=xffbffc00
# CONSTRUCT x5ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmeq/2
# AUNIT --inst x5ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision sz=1
:fcmeq Rd_FPR64, Rn_FPR64, "#0.0"
is b_2331=0b010111101 & b_22=1 & b_1021=0b100000110110 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_fcmeq(Rn_FPR64, 0:8);
}
# C7.2.57 FCMEQ (zero) page C7-1513 line 83778 MATCH x0ef8d800/mask=xbffffc00
# CONSTRUCT x0ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmeq/2@2
# AUNIT --inst x0ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 4H when Q = 0
:fcmeq Rd_VPR64.4H, Rn_VPR64.4H, "#0.0"
is b_31=0 & b_30=0 & b_1029=0b00111011111000110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fcmeq(Rn_VPR64.4H, 0:2, 2:1);
}
# C7.2.57 FCMEQ (zero) page C7-1513 line 83778 MATCH x0ef8d800/mask=xbffffc00
# CONSTRUCT x4ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmeq/2@2
# AUNIT --inst x4ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 8H when Q = 1
:fcmeq Rd_VPR128.8H, Rn_VPR128.8H, "#0.0"
is b_31=0 & b_30=1 & b_1029=0b00111011111000110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fcmeq(Rn_VPR128.8H, 0:2, 2:1);
}
# C7.2.58 FCMGE (register) page C7-1516 line 83990 MATCH x2e20e400/mask=xbfa0fc00
# CONSTRUCT x6e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@8
# AUNIT --inst x6e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags"
:fcmge Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fcmge(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.58 FCMGE (register) page C7-1516 line 83990 MATCH x2e20e400/mask=xbfa0fc00
# CONSTRUCT x2e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@4
# AUNIT --inst x2e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmge Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fcmge(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.58 FCMGE (register) page C7-1516 line 83990 MATCH x2e20e400/mask=xbfa0fc00
# CONSTRUCT x6e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@4
# AUNIT --inst x6e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmge Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fcmge(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.58 FCMGE (register) page C7-1516 line 83990 MATCH x7e402400/mask=xffe0fc00
# CONSTRUCT x7e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2
# AUNIT --inst x7e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
# Scalar half precision variant
:fcmge Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_2131=0b01111110010 & b_1015=0b001001 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
{
Rd_FPR16 = NEON_fcmge(Rn_FPR16, Rm_FPR16);
}
# C7.2.58 FCMGE (register) page C7-1516 line 83990 MATCH x7e20e400/mask=xffa0fc00
# CONSTRUCT x7e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2
# AUNIT --inst x7e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision variant sz=0
:fcmge Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_2331=0b011111100 & b_22=0 & b_21=1 & b_1015=0b111001 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
{
Rd_FPR32 = NEON_fcmge(Rn_FPR32, Rm_FPR32);
}
# C7.2.58 FCMGE (register) page C7-1516 line 83990 MATCH x7e20e400/mask=xffa0fc00
# CONSTRUCT x7e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2
# AUNIT --inst x7e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision variant sz=1
:fcmge Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_2331=0b011111100 & b_22=1 & b_21=1 & b_1015=0b111001 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
Rd_FPR64 = NEON_fcmge(Rn_FPR64, Rm_FPR64);
}
# C7.2.58 FCMGE (register) page C7-1516 line 83990 MATCH x2e402400/mask=xbfe0fc00
# CONSTRUCT x2e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@2
# AUNIT --inst x2e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 4H when Q = 0
:fcmge Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fcmge(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.58 FCMGE (register) page C7-1516 line 83990 MATCH x2e402400/mask=xbfe0fc00
# CONSTRUCT x6e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@2
# AUNIT --inst x6e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 8H when Q = 1
:fcmge Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fcmge(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.59 FCMGE (zero) page C7-1520 line 84234 MATCH x2ea0c800/mask=xbfbffc00
# CONSTRUCT x6ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmge/2@8
# AUNIT --inst x6ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
:fcmge Rd_VPR128.2D, Rn_VPR128.2D, "#0"
is b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fcmge(Rn_VPR128.2D, 0:8, 8:1);
}
# C7.2.59 FCMGE (zero) page C7-1520 line 84234 MATCH x2ea0c800/mask=xbfbffc00
# CONSTRUCT x2ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmge/2@4
# AUNIT --inst x2ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmge Rd_VPR64.2S, Rn_VPR64.2S, "#0"
is b_3131=0 & q=0 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fcmge(Rn_VPR64.2S, 0:4, 4:1);
}
# C7.2.59 FCMGE (zero) page C7-1520 line 84234 MATCH x2ea0c800/mask=xbfbffc00
# CONSTRUCT x6ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmge/2@4
# AUNIT --inst x6ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmge Rd_VPR128.4S, Rn_VPR128.4S, "#0"
is b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fcmge(Rn_VPR128.4S, 0:4, 4:1);
}
# C7.2.59 FCMGE (zero) page C7-1520 line 84234 MATCH x7ef8c800/mask=xfffffc00
# CONSTRUCT x7ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmge/2
# AUNIT --inst x7ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Scalar half precision variant
:fcmge Rd_FPR16, Rn_FPR16, "#0.0"
is b_1031=0b0111111011111000110010 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = NEON_fcmge(Rn_FPR16, 0:2);
}
# C7.2.59 FCMGE (zero) page C7-1520 line 84234 MATCH x7ea0c800/mask=xffbffc00
# CONSTRUCT x7ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmge/2
# AUNIT --inst x7ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision sz=0
:fcmge Rd_FPR32, Rn_FPR32, "#0.0"
is b_2331=0b011111101 & b_22=0 & b_1021=0b100000110010 & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = NEON_fcmge(Rn_FPR32, 0:4);
}
# C7.2.59 FCMGE (zero) page C7-1520 line 84234 MATCH x7ea0c800/mask=xffbffc00
# CONSTRUCT x7ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmge/2
# AUNIT --inst x7ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision sz=1
:fcmge Rd_FPR64, Rn_FPR64, "#0.0"
is b_2331=0b011111101 & b_22=1 & b_1021=0b100000110010 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_fcmge(Rn_FPR64, 0:8);
}
# C7.2.59 FCMGE (zero) page C7-1520 line 84234 MATCH x2ef8c800/mask=xbffffc00
# CONSTRUCT x2ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmge/2@2
# AUNIT --inst x2ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 4H when Q = 0
:fcmge Rd_VPR64.4H, Rn_VPR64.4H, "#0.0"
is b_31=0 & b_30=0 & b_1029=0b10111011111000110010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fcmge(Rn_VPR64.4H, 0:2, 2:1);
}
# C7.2.59 FCMGE (zero) page C7-1520 line 84234 MATCH x2ef8c800/mask=xbffffc00
# CONSTRUCT x6ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmge/2@2
# AUNIT --inst x6ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 8H when Q = 1
:fcmge Rd_VPR128.8H, Rn_VPR128.8H, "#0.0"
is b_31=0 & b_30=1 & b_1029=0b10111011111000110010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fcmge(Rn_VPR128.8H, 0:2, 2:1);
}
# C7.2.60 FCMGT (register) page C7-1523 line 84446 MATCH x2ea0e400/mask=xbfa0fc00
# CONSTRUCT x6ee0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@8
# AUNIT --inst x6ee0e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags"
:fcmgt Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fcmgt(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.60 FCMGT (register) page C7-1523 line 84446 MATCH x2ea0e400/mask=xbfa0fc00
# CONSTRUCT x2ea0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@4
# AUNIT --inst x2ea0e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmgt Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fcmgt(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.60 FCMGT (register) page C7-1523 line 84446 MATCH x2ea0e400/mask=xbfa0fc00
# CONSTRUCT x6ea0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@4
# AUNIT --inst x6ea0e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmgt Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fcmgt(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.60 FCMGT (register) page C7-1523 line 84446 MATCH x7ec02400/mask=xffe0fc00
# CONSTRUCT x7ec02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2
# AUNIT --inst x7ec02400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
# Scalar half precision variant
:fcmgt Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_2131=0b01111110110 & b_1015=0b001001 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
{
Rd_FPR16 = NEON_fcmgt(Rn_FPR16, Rm_FPR16);
}
# C7.2.60 FCMGT (register) page C7-1523 line 84446 MATCH x7ea0e400/mask=xffa0fc00
# CONSTRUCT x7ea0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2
# AUNIT --inst x7ea0e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision variant sz=0
:fcmgt Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_2331=0b011111101 & b_22=0 & b_21=1 & b_1015=0b111001 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
{
Rd_FPR32 = NEON_fcmgt(Rn_FPR32, Rm_FPR32);
}
# C7.2.60 FCMGT (register) page C7-1523 line 84446 MATCH x7ea0e400/mask=xffa0fc00
# CONSTRUCT x7ee0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2
# AUNIT --inst x7ee0e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision variant sz=1
:fcmgt Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_2331=0b011111101 & b_22=1 & b_21=1 & b_1015=0b111001 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
Rd_FPR64 = NEON_fcmgt(Rn_FPR64, Rm_FPR64);
}
# C7.2.60 FCMGT (register) page C7-1523 line 84446 MATCH x2ec02400/mask=xbfe0fc00
# CONSTRUCT x2ec02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@2
# AUNIT --inst x2ec02400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 4H when Q = 0
:fcmgt Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b001001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fcmgt(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.60 FCMGT (register) page C7-1523 line 84446 MATCH x2ec02400/mask=xbfe0fc00
# CONSTRUCT x6ec02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@2
# AUNIT --inst x6ec02400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 8H when Q = 1
:fcmgt Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b001001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fcmgt(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.61 FCMGT (zero) page C7-1527 line 84689 MATCH x0ea0c800/mask=xbfbffc00
# CONSTRUCT x4ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmgt/2@8
# AUNIT --inst x4ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
:fcmgt Rd_VPR128.2D, Rn_VPR128.2D, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fcmgt(Rn_VPR128.2D, 0:8, 8:1);
}
# C7.2.61 FCMGT (zero) page C7-1527 line 84689 MATCH x0ea0c800/mask=xbfbffc00
# CONSTRUCT x0ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmgt/2@4
# AUNIT --inst x0ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmgt Rd_VPR64.2S, Rn_VPR64.2S, "#0"
is b_3131=0 & q=0 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fcmgt(Rn_VPR64.2S, 0:4, 4:1);
}
# C7.2.61 FCMGT (zero) page C7-1527 line 84689 MATCH x0ea0c800/mask=xbfbffc00
# CONSTRUCT x4ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmgt/2@4
# AUNIT --inst x4ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmgt Rd_VPR128.4S, Rn_VPR128.4S, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fcmgt(Rn_VPR128.4S, 0:4, 4:1);
}
# C7.2.61 FCMGT (zero) page C7-1527 line 84689 MATCH x5ef8c800/mask=xfffffc00
# CONSTRUCT x5ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmgt/2
# AUNIT --inst x5ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Scalar half precision variant
:fcmgt Rd_FPR16, Rn_FPR16, "#0.0"
is b_1031=0b0101111011111000110010 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = NEON_fcmgt(Rn_FPR16, 0:2);
}
# C7.2.61 FCMGT (zero) page C7-1527 line 84689 MATCH x5ea0c800/mask=xffbffc00
# CONSTRUCT x5ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmgt/2
# AUNIT --inst x5ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision sz=0
:fcmgt Rd_FPR32, Rn_FPR32, "#0.0"
is b_2331=0b010111101 & b_22=0 & b_1021=0b100000110010 & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = NEON_fcmgt(Rn_FPR32, 0:4);
}
# C7.2.61 FCMGT (zero) page C7-1527 line 84689 MATCH x5ea0c800/mask=xffbffc00
# CONSTRUCT x5ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmgt/2
# AUNIT --inst x5ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision sz=1
:fcmgt Rd_FPR64, Rn_FPR64, "#0.0"
is b_2331=0b010111101 & b_22=1 & b_1021=0b100000110010 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_fcmgt(Rn_FPR64, 0:8);
}
# C7.2.61 FCMGT (zero) page C7-1527 line 84689 MATCH x0ef8c800/mask=xbffffc00
# CONSTRUCT x0ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmgt/2@2
# AUNIT --inst x0ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 4H when Q = 0
:fcmgt Rd_VPR64.4H, Rn_VPR64.4H, "#0.0"
is b_31=0 & b_30=0 & b_1029=0b00111011111000110010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fcmgt(Rn_VPR64.4H, 0:2, 2:1);
}
# C7.2.61 FCMGT (zero) page C7-1527 line 84689 MATCH x0ef8c800/mask=xbffffc00
# CONSTRUCT x4ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmgt/2@2
# AUNIT --inst x4ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 8H when Q = 1
:fcmgt Rd_VPR128.8H, Rn_VPR128.8H, "#0.0"
is b_31=0 & b_30=1 & b_1029=0b00111011111000110010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fcmgt(Rn_VPR128.8H, 0:2, 2:1);
}
# C7.2.55 FCMLA (by element) page C7-1117 line 64749 KEEPWITH
fcmla_rotate: #0 is b_15=0 & b_1314=0b00 { export 0:1; }
fcmla_rotate: #90 is b_15=0 & b_1314=0b01 { export 90:1; }
fcmla_rotate: #180 is b_15=0 & b_1314=0b10 { export 180:1; }
fcmla_rotate: #270 is b_15=0 & b_1314=0b11 { export 270:1; }
fcmla_rotate: #0 is b_15=1 & b_1112=0b00 { export 0:1; }
fcmla_rotate: #90 is b_15=1 & b_1112=0b01 { export 90:1; }
fcmla_rotate: #180 is b_15=1 & b_1112=0b10 { export 180:1; }
fcmla_rotate: #270 is b_15=1 & b_1112=0b11 { export 270:1; }
# C7.2.62 FCMLA (by element) page C7-1530 line 84901 MATCH x2f001000/mask=xbf009400
# CONSTRUCT x2f401000/mask=xffc09c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@2
# AUNIT --inst x2f401000/mask=xffc09c00 --rand hfp --status noqemu --comment "noflags"
# The representation of Rm in the documentation as a 4 bit field
# extended by M actually makes it a standard 5 bit field.
# 4H variant when size = 01 , Q = 0 T=VPR64.4H imm=Re_VPR128.H.vIndexHL i1=Re_VPR128.H i2=vIndexHL
# NOTE: if size == '01' and H == '1' && Q == '0' then ReservedValue();
:fcmla Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128.H.vIndexHL, fcmla_rotate
is b_31=0 & b_30=0 & b_2429=0b101111 & b_2223=0b01 & b_15=0 & b_12=1 & b_11=0 & b_10=0 & fcmla_rotate & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128.H.vIndexHL & Re_VPR128.H & vIndexHL & Zd
{
local tmp1:2 = SIMD_PIECE(Re_VPR128.H, vIndexHL:1);
Rd_VPR64.4H = NEON_fcmla(Rn_VPR64.4H, tmp1, fcmla_rotate, 2:1);
}
# C7.2.62 FCMLA (by element) page C7-1530 line 84901 MATCH x2f001000/mask=xbf009400
# CONSTRUCT x6f401000/mask=xffc09400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@2
# AUNIT --inst x6f401000/mask=xffc09400 --rand hfp --status noqemu --comment "noflags"
# 8H variant when size = 01 , Q = 1 T=VPR128.8H imm=Re_VPR128.H.vIndexHL i1=Re_VPR128.H i2=vIndexHL
:fcmla Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128.H.vIndexHL, fcmla_rotate
is b_31=0 & b_30=1 & b_2429=0b101111 & b_2223=0b01 & b_15=0 & b_12=1 & b_10=0 & fcmla_rotate & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128.H.vIndexHL & Re_VPR128.H & vIndexHL & Zd
{
local tmp1:2 = SIMD_PIECE(Re_VPR128.H, vIndexHL:1);
Rd_VPR128.8H = NEON_fcmla(Rn_VPR128.8H, tmp1, fcmla_rotate, 2:1);
}
# C7.2.62 FCMLA (by element) page C7-1530 line 84901 MATCH x2f001000/mask=xbf009400
# CONSTRUCT x6f801000/mask=xffe09400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4
# AUNIT --inst x6f801000/mask=xffe09400 --rand sfp --status noqemu --comment "noflags"
# 4S variant when size = 10 , Q = 1 T=VPR128.4S imm=Re_VPR128.S.vIndex i1=Re_VPR128.S i2=vIndex
# NOTE: if size == '10' and (L == '1' || Q == '0') then ReservedValue();
:fcmla Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex, fcmla_rotate
is b_31=0 & b_30=1 & b_2429=0b101111 & b_2223=0b10 & b_21=0 & b_15=0 & b_12=1 & b_10=0 & fcmla_rotate & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd
{
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
Rd_VPR128.4S = NEON_fcmla(Rn_VPR128.4S, tmp1, fcmla_rotate, 4:1);
}
# C7.2.63 FCMLA page C7-1533 line 85073 MATCH x2e00c400/mask=xbf20e400
# CONSTRUCT x2e40c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4
# AUNIT --inst x2e40c400/mask=xffe0e400 --rand hfp --status noqemu --comment "noflags"
# FCMLA SIMD 4H when size = 01 , Q = 0
:fcmla Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, fcmla_rotate
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fcmla(Rn_VPR64.4H, Rm_VPR64.4H, fcmla_rotate, 4:1);
}
# C7.2.63 FCMLA page C7-1533 line 85073 MATCH x2e00c400/mask=xbf20e400
# CONSTRUCT x6e40c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4
# AUNIT --inst x6e40c400/mask=xffe0e400 --rand hfp --status noqemu --comment "noflags"
# FCMLA SIMD 8H when size = 01 , Q = 1
:fcmla Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, fcmla_rotate
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fcmla(Rn_VPR128.8H, Rm_VPR128.8H, fcmla_rotate, 4:1);
}
# C7.2.63 FCMLA page C7-1533 line 85073 MATCH x2e00c400/mask=xbf20e400
# CONSTRUCT x2e80c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4
# AUNIT --inst x2e80c400/mask=xffe0e400 --rand sfp --status noqemu --comment "noflags"
# FCMLA SIMD 2S when size = 10 , Q = 0
:fcmla Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, fcmla_rotate
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fcmla(Rn_VPR64.2S, Rm_VPR64.2S, fcmla_rotate, 4:1);
}
# C7.2.63 FCMLA page C7-1533 line 85073 MATCH x2e00c400/mask=xbf20e400
# CONSTRUCT x6e80c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4
# AUNIT --inst x6e80c400/mask=xffe0e400 --rand sfp --status noqemu --comment "noflags"
# FCMLA SIMD 4S when size = 10 , Q = 1
:fcmla Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, fcmla_rotate
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fcmla(Rn_VPR128.4S, Rm_VPR128.4S, fcmla_rotate, 4:1);
}
# C7.2.63 FCMLA page C7-1533 line 85073 MATCH x2e00c400/mask=xbf20e400
# CONSTRUCT x6ec0c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4
# AUNIT --inst x6ec0c400/mask=xffe0e400 --rand dfp --status noqemu --comment "noflags"
# FCMLA SIMD 2D when size = 11 , Q = 1
:fcmla Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, fcmla_rotate
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fcmla(Rn_VPR128.2D, Rm_VPR128.2D, fcmla_rotate, 4:1);
}
# C7.2.64 FCMLE (zero) page C7-1535 line 85215 MATCH x2ea0d800/mask=xbfbffc00
# CONSTRUCT x6ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmle/2@8
# AUNIT --inst x6ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
:fcmle Rd_VPR128.2D, Rn_VPR128.2D, "#0"
is b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xd & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fcmle(Rn_VPR128.2D, 0:8, 8:1);
}
# C7.2.64 FCMLE (zero) page C7-1535 line 85215 MATCH x2ea0d800/mask=xbfbffc00
# CONSTRUCT x2ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2@2
# AUNIT --inst x2ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmle Rd_VPR64.2S, Rn_VPR64.2S, "#0"
is b_3131=0 & q=0 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fcmle(Rn_VPR64.2S, 0:2, 2:1);
}
# C7.2.64 FCMLE (zero) page C7-1535 line 85215 MATCH x2ea0d800/mask=xbfbffc00
# CONSTRUCT x6ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmle/2@4
# AUNIT --inst x6ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop
:fcmle Rd_VPR128.4S, Rn_VPR128.4S, "#0"
is b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fcmle(Rn_VPR128.4S, 0:4, 4:1);
}
# C7.2.64 FCMLE (zero) page C7-1535 line 85215 MATCH x7ef8d800/mask=xfffffc00
# CONSTRUCT x7ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2
# AUNIT --inst x7ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Scalar half precision variant
:fcmle Rd_FPR16, Rn_FPR16, "#0.0"
is b_1031=0b0111111011111000110110 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = NEON_fcmle(Rn_FPR16, 0:2);
}
# C7.2.64 FCMLE (zero) page C7-1535 line 85215 MATCH x7ea0d800/mask=xffbffc00
# CONSTRUCT x7ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmle/2
# AUNIT --inst x7ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision sz=0
:fcmle Rd_FPR32, Rn_FPR32, "#0.0"
is b_2331=0b011111101 & b_22=0 & b_1021=0b100000110110 & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = NEON_fcmle(Rn_FPR32, 0:4);
}
# C7.2.64 FCMLE (zero) page C7-1535 line 85215 MATCH x7ea0d800/mask=xffbffc00
# CONSTRUCT x7ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmle/2
# AUNIT --inst x7ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision sz=1
:fcmle Rd_FPR64, Rn_FPR64, "#0.0"
is b_2331=0b011111101 & b_22=1 & b_1021=0b100000110110 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_fcmle(Rn_FPR64, 0:8);
}
# C7.2.64 FCMLE (zero) page C7-1535 line 85215 MATCH x2ef8d800/mask=xbffffc00
# CONSTRUCT x2ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2@2
# AUNIT --inst x2ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 4H when Q = 0
:fcmle Rd_VPR64.4H, Rn_VPR64.4H, "#0.0"
is b_31=0 & b_30=0 & b_1029=0b10111011111000110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fcmle(Rn_VPR64.4H, 0:2, 2:1);
}
# C7.2.64 FCMLE (zero) page C7-1535 line 85215 MATCH x2ef8d800/mask=xbffffc00
# CONSTRUCT x6ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2@2
# AUNIT --inst x6ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 8H when Q = 1
:fcmle Rd_VPR128.8H, Rn_VPR128.8H, "#0.0"
is b_31=0 & b_30=1 & b_1029=0b10111011111000110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fcmle(Rn_VPR128.8H, 0:2, 2:1);
}
# C7.2.65 FCMLT (zero) page C7-1538 line 85427 MATCH x0ea0e800/mask=xbfbffc00
# CONSTRUCT x4ee0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmlt/2@8
# AUNIT --inst x4ee0e800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
:fcmlt Rd_VPR128.2D, Rn_VPR128.2D, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xe & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fcmlt(Rn_VPR128.2D, 0:8, 8:1);
}
# C7.2.65 FCMLT (zero) page C7-1538 line 85427 MATCH x0ea0e800/mask=xbfbffc00
# CONSTRUCT x0ea0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmlt/2@4
# AUNIT --inst x0ea0e800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmlt Rd_VPR64.2S, Rn_VPR64.2S, "#0"
is b_3131=0 & q=0 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xe & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fcmlt(Rn_VPR64.2S, 0:4, 4:1);
}
# C7.2.65 FCMLT (zero) page C7-1538 line 85427 MATCH x0ea0e800/mask=xbfbffc00
# CONSTRUCT x4ea0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmlt/2@4
# AUNIT --inst x4ea0e800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
:fcmlt Rd_VPR128.4S, Rn_VPR128.4S, "#0"
is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xe & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fcmlt(Rn_VPR128.4S, 0:4, 4:1);
}
# C7.2.65 FCMLT (zero) page C7-1538 line 85427 MATCH x5ef8e800/mask=xfffffc00
# CONSTRUCT x5ef8e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmlt/2
# AUNIT --inst x5ef8e800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Scalar half precision variant
:fcmlt Rd_FPR16, Rn_FPR16, "#0.0"
is b_1031=0b0101111011111000111010 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = NEON_fcmlt(Rn_FPR16, 0:2);
}
# C7.2.65 FCMLT (zero) page C7-1538 line 85427 MATCH x5ea0e800/mask=xffbffc00
# CONSTRUCT x5ea0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmlt/2
# AUNIT --inst x5ea0e800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision sz=0
:fcmlt Rd_FPR32, Rn_FPR32, "#0.0"
is b_2331=0b010111101 & b_22=0 & b_1021=0b100000111010 & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = NEON_fcmlt(Rn_FPR32, 0:4);
}
# C7.2.65 FCMLT (zero) page C7-1538 line 85427 MATCH x5ea0e800/mask=xffbffc00
# CONSTRUCT x5ee0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmlt/2
# AUNIT --inst x5ee0e800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
# Scalar single-precision and double-precision sz=1
:fcmlt Rd_FPR64, Rn_FPR64, "#0.0"
is b_2331=0b010111101 & b_22=1 & b_1021=0b100000111010 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_fcmlt(Rn_FPR64, 0:8);
}
# C7.2.65 FCMLT (zero) page C7-1538 line 85427 MATCH x0ef8e800/mask=xbffffc00
# CONSTRUCT x0ef8e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmlt/2@2
# AUNIT --inst x0ef8e800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 4H when Q = 0
:fcmlt Rd_VPR64.4H, Rn_VPR64.4H, "#0.0"
is b_31=0 & b_30=0 & b_1029=0b00111011111000111010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fcmlt(Rn_VPR64.4H, 0:2, 2:1);
}
# C7.2.65 FCMLT (zero) page C7-1538 line 85427 MATCH x0ef8e800/mask=xbffffc00
# CONSTRUCT x4ef8e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmlt/2@2
# AUNIT --inst x4ef8e800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
# Vector half precision variant SIMD 8H when Q = 1
:fcmlt Rd_VPR128.8H, Rn_VPR128.8H, "#0.0"
is b_31=0 & b_30=1 & b_1029=0b00111011111000111010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fcmlt(Rn_VPR128.8H, 0:2, 2:1);
}
# C7.2.66 FCMP page C7-1541 line 85621 MATCH x1e202000/mask=xff20fc17
# CONSTRUCT x1e602000/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2
# AUNIT --inst x1e602000/mask=xffe0fc1f --rand dfp --status nodest --comment "flags"
:fcmp Rn_FPR64, Rm_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x0
{
fcomp(Rn_FPR64, Rm_FPR64);
}
# C7.2.66 FCMP page C7-1541 line 85621 MATCH x1e202000/mask=xff20fc17
# CONSTRUCT x1e602008/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2
# AUNIT --inst x1e602008/mask=xffe0fc1f --rand dfp --status nodest --comment "flags"
:fcmp Rn_FPR64, Rm_fpz64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_fpz64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x8
{
fcomp(Rn_FPR64, Rm_fpz64);
}
# C7.2.66 FCMP page C7-1541 line 85621 MATCH x1e202000/mask=xff20fc17
# CONSTRUCT x1e202008/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2
# AUNIT --inst x1e202008/mask=xffe0fc1f --rand sfp --status nodest --comment "flags"
:fcmp Rn_FPR32, Rm_fpz32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_fpz32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x8
{
fcomp(Rn_FPR32, Rm_fpz32);
}
# C7.2.66 FCMP page C7-1541 line 85621 MATCH x1e202000/mask=xff20fc17
# CONSTRUCT x1e202000/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2
# AUNIT --inst x1e202000/mask=xffe0fc1f --rand sfp --status nodest --comment "flags"
:fcmp Rn_FPR32, Rm_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x0
{
fcomp(Rn_FPR32, Rm_FPR32);
}
# C7.2.66 FCMP page C7-1541 line 85621 MATCH x1e202000/mask=xff20fc17
# CONSTRUCT x1ee02008/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2
# AUNIT --inst x1ee02008/mask=xffe0fc1f --rand hfp --status nodest --comment "flags"
:fcmp Rn_FPR16, Rm_fpz16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_fpz16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x8
{
fcomp(Rn_FPR16, Rm_fpz16);
}
# C7.2.66 FCMP page C7-1541 line 85621 MATCH x1e202000/mask=xff20fc17
# CONSTRUCT x1ee02000/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2
# AUNIT --inst x1ee02000/mask=xffe0fc1f --rand hfp --status nodest --comment "flags"
:fcmp Rn_FPR16, Rm_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x0
{
fcomp(Rn_FPR16, Rm_FPR16);
}
# C7.2.67 FCMPE page C7-1543 line 85756 MATCH x1e202010/mask=xff20fc17
# CONSTRUCT x1e602010/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2
# AUNIT --inst x1e602010/mask=xffe0fc1f --rand dfp --status nodest --comment "flags"
:fcmpe Rn_FPR64, Rm_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x10
{
ftestNAN(Rn_FPR64, Rm_FPR64);
fcomp(Rn_FPR64, Rm_FPR64);
}
# C7.2.67 FCMPE page C7-1543 line 85756 MATCH x1e202010/mask=xff20fc17
# CONSTRUCT x1e602018/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2
# AUNIT --inst x1e602018/mask=xffe0fc1f --rand dfp --status nodest --comment "flags"
:fcmpe Rn_FPR64, Rm_fpz64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_fpz64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x18
{
ftestNAN(Rn_FPR64, Rm_fpz64);
fcomp(Rn_FPR64, Rm_fpz64);
}
# C7.2.67 FCMPE page C7-1543 line 85756 MATCH x1e202010/mask=xff20fc17
# CONSTRUCT x1e202018/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2
# AUNIT --inst x1e202018/mask=xffe0fc1f --rand sfp --status nodest --comment "flags"
:fcmpe Rn_FPR32, Rm_fpz32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_fpz32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x18
{
ftestNAN(Rn_FPR32, Rm_fpz32);
fcomp(Rn_FPR32, Rm_fpz32);
}
# C7.2.67 FCMPE page C7-1543 line 85756 MATCH x1e202010/mask=xff20fc17
# CONSTRUCT x1e202010/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2
# AUNIT --inst x1e202010/mask=xffe0fc1f --rand sfp --status nodest --comment "flags"
:fcmpe Rn_FPR32, Rm_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x10
{
ftestNAN(Rn_FPR32, Rm_FPR32);
fcomp(Rn_FPR32, Rm_FPR32);
}
# C7.2.67 FCMPE page C7-1543 line 85756 MATCH x1e202010/mask=xff20fc17
# CONSTRUCT x1ee02018/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2
# AUNIT --inst x1ee02018/mask=xffe0fc1f --rand hfp --status nodest --comment "flags"
:fcmpe Rn_FPR16, Rm_fpz16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_fpz16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x18
{
ftestNAN(Rn_FPR16, Rm_fpz16);
fcomp(Rn_FPR16, Rm_fpz16);
}
# C7.2.67 FCMPE page C7-1543 line 85756 MATCH x1e202010/mask=xff20fc17
# CONSTRUCT x1ee02010/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2
# AUNIT --inst x1ee02010/mask=xffe0fc1f --rand hfp --status nodest --comment "flags"
:fcmpe Rn_FPR16, Rm_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x10
{
ftestNAN(Rn_FPR16, Rm_FPR16);
fcomp(Rn_FPR16, Rm_FPR16);
}
# C7.2.68 FCSEL page C7-1545 line 85895 MATCH x1e200c00/mask=xff200c00
# CONSTRUCT x1e600c00/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 = dup ext swap ARG4:1 inst_next goto =
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4:1 =NEON_fcsel/3
# AUNIT --inst x1e600c00/mask=xffe00c00 --rand dfp --status pass --comment "flags"
# Rm may be the same register as Rd, so it needs to be saved
:fcsel Rd_FPR64, Rn_FPR64, Rm_FPR64, CondOp
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & CondOp & b_1011=3 & Rn_FPR64 & Rd_FPR64 & Zd
{
local tmp1:8 = Rm_FPR64;
Rd_FPR64 = Rn_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
if (CondOp:1) goto inst_next;
Rd_FPR64 = tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.68 FCSEL page C7-1545 line 85895 MATCH x1e200c00/mask=xff200c00
# CONSTRUCT x1e200c00/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 = dup ext swap ARG4:1 inst_next goto =
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4:1 =NEON_fcsel/3
# AUNIT --inst x1e200c00/mask=xffe00c00 --rand sfp --status pass --comment "flags"
:fcsel Rd_FPR32, Rn_FPR32, Rm_FPR32, CondOp
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & CondOp & b_1011=3 & Rn_FPR32 & Rd_FPR32 & Zd
{
local tmp1:4 = Rm_FPR32;
Rd_FPR32 = Rn_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
if (CondOp:1) goto inst_next;
Rd_FPR32 = tmp1;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.68 FCSEL page C7-1545 line 85895 MATCH x1e200c00/mask=xff200c00
# CONSTRUCT x1ee00c00/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 = dup ext swap ARG4:1 inst_next goto =
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4:1 =NEON_fcsel/3
# AUNIT --inst x1ee00c00/mask=xffe00c00 --rand hfp --status noqemu --comment "flags"
:fcsel Rd_FPR16, Rn_FPR16, Rm_FPR16, CondOp
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & CondOp & b_1011=3 & Rn_FPR16 & Rd_FPR16 & Zd
{
local tmp1:2 = Rm_FPR16;
Rd_FPR16 = Rn_FPR16;
zext_zh(Zd); # zero upper 30 bytes of Zd
if (CondOp:1) goto inst_next;
Rd_FPR16 = tmp1;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.69 FCVT page C7-1547 line 86009 MATCH x1e224000/mask=xff3e7c00
# CONSTRUCT x1ee2c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1
# AUNIT --inst x1ee2c000/mask=xfffffc00 --rand hfp --status pass --comment "nofpround"
:fcvt Rd_FPR64, Rn_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x5 & b_1014=0x10 & Rn_FPR16 & Rd_FPR64 & Zd
{
Rd_FPR64 = float2float(Rn_FPR16);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.69 FCVT page C7-1547 line 86009 MATCH x1e224000/mask=xff3e7c00
# CONSTRUCT x1e22c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1
# AUNIT --inst x1e22c000/mask=xfffffc00 --rand sfp --status pass --comment "nofpround"
:fcvt Rd_FPR64, Rn_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x5 & b_1014=0x10 & Rn_FPR32 & Rd_FPR64 & Zd
{
Rd_FPR64 = float2float(Rn_FPR32);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.69 FCVT page C7-1547 line 86009 MATCH x1e224000/mask=xff3e7c00
# CONSTRUCT x1e63c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1
# AUNIT --inst x1e63c000/mask=xfffffc00 --rand hfp --status pass --comment "nofpround"
:fcvt Rd_FPR16, Rn_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x7 & b_1014=0x10 & Rn_FPR64 & Rd_FPR16 & Zd
{
Rd_FPR16 = float2float(Rn_FPR64);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.69 FCVT page C7-1547 line 86009 MATCH x1e224000/mask=xff3e7c00
# CONSTRUCT x1e23c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1
# AUNIT --inst x1e23c000/mask=xfffffc00 --rand hfp --status fail --comment "nofpround"
:fcvt Rd_FPR16, Rn_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x7 & b_1014=0x10 & Rn_FPR32 & Rd_FPR16 & Zd
{
Rd_FPR16 = float2float(Rn_FPR32);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.69 FCVT page C7-1547 line 86009 MATCH x1e224000/mask=xff3e7c00
# CONSTRUCT x1e624000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1
# AUNIT --inst x1e624000/mask=xfffffc00 --rand sfp --status fail --comment "nofpround"
:fcvt Rd_FPR32, Rn_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x4 & b_1014=0x10 & Rn_FPR64 & Rd_FPR32 & Zd
{
Rd_FPR32 = float2float(Rn_FPR64);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.69 FCVT page C7-1547 line 86009 MATCH x1e224000/mask=xff3e7c00
# CONSTRUCT x1ee24000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1
# AUNIT --inst x1ee24000/mask=xfffffc00 --rand hfp --status pass --comment "nofpround"
:fcvt Rd_FPR32, Rn_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x4 & b_1014=0x10 & Rn_FPR16 & Rd_FPR32 & Zd
{
Rd_FPR32 = float2float(Rn_FPR16);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.63 FCVTAS (vector) page C7-1136 line 65961 KEEPWITH
fcvt_vmnemonic: "fcvtas" is b_29=0 & b_23=0 & b_1314=0b10 & b_12=0 { }
fcvt_vmnemonic: "fcvtau" is b_29=1 & b_23=0 & b_1314=0b10 & b_12=0 { }
fcvt_vmnemonic: "fcvtms" is b_29=0 & b_23=0 & b_1314=0b01 & b_12=1 { }
fcvt_vmnemonic: "fcvtmu" is b_29=1 & b_23=0 & b_1314=0b01 & b_12=1 { }
fcvt_vmnemonic: "fcvtns" is b_29=0 & b_23=0 & b_1314=0b01 & b_12=0 { }
fcvt_vmnemonic: "fcvtnu" is b_29=1 & b_23=0 & b_1314=0b01 & b_12=0 { }
fcvt_vmnemonic: "fcvtps" is b_29=0 & b_23=1 & b_1314=0b01 & b_12=0 { }
fcvt_vmnemonic: "fcvtpu" is b_29=1 & b_23=1 & b_1314=0b01 & b_12=0 { }
fcvt_vmnemonic: "fcvtzs" is b_29=0 & b_23=1 & b_1314=0b01 & b_12=1 { }
fcvt_vmnemonic: "fcvtzu" is b_29=1 & b_23=1 & b_1314=0b01 & b_12=1 { }
fcvt_smnemonic: "fcvtas" is b_1920=0b00 & b_1618=0b100 { }
fcvt_smnemonic: "fcvtau" is b_1920=0b00 & b_1618=0b101 { }
fcvt_smnemonic: "fcvtms" is b_1920=0b10 & b_1618=0b000 { }
fcvt_smnemonic: "fcvtmu" is b_1920=0b10 & b_1618=0b001 { }
fcvt_smnemonic: "fcvtns" is b_1920=0b00 & b_1618=0b000 { }
fcvt_smnemonic: "fcvtnu" is b_1920=0b00 & b_1618=0b001 { }
fcvt_smnemonic: "fcvtps" is b_1920=0b01 & b_1618=0b000 { }
fcvt_smnemonic: "fcvtpu" is b_1920=0b01 & b_1618=0b001 { }
fcvt_smnemonic: "fcvtzs" is b_1920=0b11 & b_1618=0b000 { }
fcvt_smnemonic: "fcvtzu" is b_1920=0b11 & b_1618=0b001 { }
# C7.2.70 FCVTAS (vector) page C7-1549 line 86125 MATCH x5e79c800/mask=xfffffc00
# C7.2.72 FCVTAU (vector) page C7-1554 line 86430 MATCH x7e79c800/mask=xfffffc00
# CONSTRUCT x5e79c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x5e79c800/mask=xdffffc00 --rand hfp --status noqemu --comment "nofpround"
# Scalar half precision
:^fcvt_vmnemonic Rd_FPR16, Rn_FPR16
is b_3031=0b01 & b_1028=0b1111001111001110010 & fcvt_vmnemonic & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = trunc(Rn_FPR16);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.70 FCVTAS (vector) page C7-1549 line 86125 MATCH x5e21c800/mask=xffbffc00
# C7.2.72 FCVTAU (vector) page C7-1554 line 86430 MATCH x7e21c800/mask=xffbffc00
# CONSTRUCT x5e21c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x5e21c800/mask=xdffffc00 --rand sfp --status fail --comment "nofpround"
# Scalar single-precision and double-precision variant sz=0
:^fcvt_vmnemonic Rd_FPR32, Rn_FPR32
is b_3031=0b01 & b_2328=0b111100 & b_22=0 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = trunc(Rn_FPR32);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.70 FCVTAS (vector) page C7-1549 line 86125 MATCH x5e21c800/mask=xffbffc00
# C7.2.72 FCVTAU (vector) page C7-1554 line 86430 MATCH x7e21c800/mask=xffbffc00
# CONSTRUCT x5e61c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x5e61c800/mask=xdffffc00 --rand dfp --status fail --comment "nofpround"
# Scalar single-precision and double-precision variant sz=1
:^fcvt_vmnemonic Rd_FPR64, Rn_FPR64
is b_3031=0b01 & b_2328=0b111100 & b_22=1 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = trunc(Rn_FPR64);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.70 FCVTAS (vector) page C7-1549 line 86125 MATCH x0e79c800/mask=xbffffc00
# C7.2.72 FCVTAU (vector) page C7-1554 line 86430 MATCH x2e79c800/mask=xbffffc00
# CONSTRUCT x0e79c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2
# AUNIT --inst x0e79c800/mask=xdffffc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant Q=0
:^fcvt_vmnemonic Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_2328=0b011100 & b_1022=0b1111001110010 & fcvt_vmnemonic & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
# simd unary Rd_VPR64.4H = trunc(Rn_VPR64.4H) on lane size 2
Rd_VPR64.4H[0,16] = trunc(Rn_VPR64.4H[0,16]);
Rd_VPR64.4H[16,16] = trunc(Rn_VPR64.4H[16,16]);
Rd_VPR64.4H[32,16] = trunc(Rn_VPR64.4H[32,16]);
Rd_VPR64.4H[48,16] = trunc(Rn_VPR64.4H[48,16]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.70 FCVTAS (vector) page C7-1549 line 86125 MATCH x0e79c800/mask=xbffffc00
# C7.2.72 FCVTAU (vector) page C7-1554 line 86430 MATCH x2e79c800/mask=xbffffc00
# CONSTRUCT x4e79c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2
# AUNIT --inst x4e79c800/mask=xdffffc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant Q=1
:^fcvt_vmnemonic Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2328=0b011100 & b_1022=0b1111001110010 & fcvt_vmnemonic & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
# simd unary Rd_VPR128.8H = trunc(Rn_VPR128.8H) on lane size 2
Rd_VPR128.8H[0,16] = trunc(Rn_VPR128.8H[0,16]);
Rd_VPR128.8H[16,16] = trunc(Rn_VPR128.8H[16,16]);
Rd_VPR128.8H[32,16] = trunc(Rn_VPR128.8H[32,16]);
Rd_VPR128.8H[48,16] = trunc(Rn_VPR128.8H[48,16]);
Rd_VPR128.8H[64,16] = trunc(Rn_VPR128.8H[64,16]);
Rd_VPR128.8H[80,16] = trunc(Rn_VPR128.8H[80,16]);
Rd_VPR128.8H[96,16] = trunc(Rn_VPR128.8H[96,16]);
Rd_VPR128.8H[112,16] = trunc(Rn_VPR128.8H[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.70 FCVTAS (vector) page C7-1549 line 86125 MATCH x0e21c800/mask=xbfbffc00
# C7.2.72 FCVTAU (vector) page C7-1554 line 86430 MATCH x2e21c800/mask=xbfbffc00
# CONSTRUCT x0e21c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4
# AUNIT --inst x0e21c800/mask=xdffffc00 --rand sfp --status fail --comment "nofpround"
# Vector single-precision and double-precision variant SIMD 2S when sz = 0 , Q = 0
:^fcvt_vmnemonic Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2328=0b011100 & b_22=0 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
# simd unary Rd_VPR64.2S = trunc(Rn_VPR64.2S) on lane size 4
Rd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]);
Rd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.70 FCVTAS (vector) page C7-1549 line 86125 MATCH x0e21c800/mask=xbfbffc00
# C7.2.72 FCVTAU (vector) page C7-1554 line 86430 MATCH x2e21c800/mask=xbfbffc00
# CONSTRUCT x4e21c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4
# AUNIT --inst x4e21c800/mask=xdffffc00 --rand sfp --status fail --comment "nofpround"
# Vector single-precision and double-precision variant SIMD 4S when sz = 0 , Q = 1
:^fcvt_vmnemonic Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2328=0b011100 & b_22=0 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
# simd unary Rd_VPR128.4S = trunc(Rn_VPR128.4S) on lane size 4
Rd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]);
Rd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]);
Rd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]);
Rd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.70 FCVTAS (vector) page C7-1549 line 86125 MATCH x0e21c800/mask=xbfbffc00
# C7.2.72 FCVTAU (vector) page C7-1554 line 86430 MATCH x2e21c800/mask=xbfbffc00
# CONSTRUCT x4e61c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@8
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@8
# AUNIT --inst x4e61c800/mask=xdffffc00 --rand dfp --status fail --comment "nofpround"
# Vector single-precision and double-precision variant SIMD 2D when sz = 1 , Q = 1
:^fcvt_vmnemonic Rd_VPR128.2D, Rn_VPR128.2D
is b_31=0 & b_30=1 & b_2328=0b011100 & b_22=1 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_VPR128.2D & Rn_VPR128.2D & Zd
{
# simd unary Rd_VPR128.2D = trunc(Rn_VPR128.2D) on lane size 8
Rd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]);
Rd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.71 FCVTAS (scalar) page C7-1552 line 86310 MATCH x1e240000/mask=x7f3ffc00
# C7.2.73 FCVTAU (scalar) page C7-1557 line 86615 MATCH x1e250000/mask=x7f3ffc00
# CONSTRUCT x1ee40000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x1ee40000/mask=xfffefc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision to 32-bit variant when sf == 0 && type == 11
:^fcvt_smnemonic Rd_GPR32, Rn_FPR16
is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR16 & Rd_GPR64
{
Rd_GPR32 = trunc(Rn_FPR16);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.71 FCVTAS (scalar) page C7-1552 line 86310 MATCH x1e240000/mask=x7f3ffc00
# C7.2.73 FCVTAU (scalar) page C7-1557 line 86615 MATCH x1e250000/mask=x7f3ffc00
# CONSTRUCT x9ee40000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x9ee40000/mask=xfffefc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision to 64-bit variant when sf == 1 && type == 11
:^fcvt_smnemonic Rd_GPR64, Rn_FPR16
is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR16
{
Rd_GPR64 = trunc(Rn_FPR16);
}
# C7.2.71 FCVTAS (scalar) page C7-1552 line 86310 MATCH x1e240000/mask=x7f3ffc00
# C7.2.73 FCVTAU (scalar) page C7-1557 line 86615 MATCH x1e250000/mask=x7f3ffc00
# CONSTRUCT x1e240000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x1e240000/mask=xfffefc00 --rand sfp --status fail --comment "nofpround"
# Single-precision to 32-bit variant when sf == 0 && type == 00
:^fcvt_smnemonic Rd_GPR32, Rn_FPR32
is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR32 & Rd_GPR64
{
Rd_GPR32 = trunc(Rn_FPR32);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.71 FCVTAS (scalar) page C7-1552 line 86310 MATCH x1e240000/mask=x7f3ffc00
# C7.2.73 FCVTAU (scalar) page C7-1557 line 86615 MATCH x1e250000/mask=x7f3ffc00
# CONSTRUCT x9e240000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x9e240000/mask=xfffefc00 --rand sfp --status fail --comment "nofpround"
# Single-precision to 64-bit variant when sf == 1 && type == 00
:^fcvt_smnemonic Rd_GPR64, Rn_FPR32
is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR32
{
Rd_GPR64 = trunc(Rn_FPR32);
}
# C7.2.71 FCVTAS (scalar) page C7-1552 line 86310 MATCH x1e240000/mask=x7f3ffc00
# C7.2.73 FCVTAU (scalar) page C7-1557 line 86615 MATCH x1e250000/mask=x7f3ffc00
# CONSTRUCT x1e640000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x1e640000/mask=xfffefc00 --rand dfp --status fail --comment "nofpround"
# Double-precision to 32-bit variant when sf == 0 && type == 01
:^fcvt_smnemonic Rd_GPR32, Rn_FPR64
is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR64 & Rd_GPR64
{
Rd_GPR32 = trunc(Rn_FPR64);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.71 FCVTAS (scalar) page C7-1552 line 86310 MATCH x1e240000/mask=x7f3ffc00
# C7.2.73 FCVTAU (scalar) page C7-1557 line 86615 MATCH x1e250000/mask=x7f3ffc00
# CONSTRUCT x9e640000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x9e640000/mask=xfffefc00 --rand dfp --status fail --comment "nofpround"
# Double-precision to 64-bit variant sf == 1 && type == 01
:^fcvt_smnemonic Rd_GPR64, Rn_FPR64
is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR64
{
Rd_GPR64 = trunc(Rn_FPR64);
}
# C7.2.74 FCVTL, FCVTL2 page C7-1559 line 86735 MATCH x0e217800/mask=xbfbffc00
# CONSTRUCT x0e617800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =$float2float@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl/1@4
# AUNIT --inst x0e617800/mask=xfffffc00 --rand dfp --status fail --comment "ext nofpround"
:fcvtl Rd_VPR128.2D, Rn_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR64.2S;
# simd resize Rd_VPR128.2D = float2float(TMPD1) (lane size 4 to 8)
Rd_VPR128.2D[0,64] = float2float(TMPD1[0,32]);
Rd_VPR128.2D[64,64] = float2float(TMPD1[32,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.74 FCVTL, FCVTL2 page C7-1559 line 86735 MATCH x0e217800/mask=xbfbffc00
# CONSTRUCT x4e617800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 =$float2float@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl2/1@8
# AUNIT --inst x4e617800/mask=xfffffc00 --rand dfp --status fail --comment "ext nofpround"
:fcvtl2 Rd_VPR128.2D, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize Rd_VPR128.2D = float2float(TMPD1) (lane size 4 to 8)
Rd_VPR128.2D[0,64] = float2float(TMPD1[0,32]);
Rd_VPR128.2D[64,64] = float2float(TMPD1[32,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.74 FCVTL, FCVTL2 page C7-1559 line 86735 MATCH x0e217800/mask=xbfbffc00
# CONSTRUCT x0e217800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =$float2float@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl/1@4
# AUNIT --inst x0e217800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround"
:fcvtl Rd_VPR128.4S, Rn_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR64.4H;
# simd resize Rd_VPR128.4S = float2float(TMPD1) (lane size 2 to 4)
Rd_VPR128.4S[0,32] = float2float(TMPD1[0,16]);
Rd_VPR128.4S[32,32] = float2float(TMPD1[16,16]);
Rd_VPR128.4S[64,32] = float2float(TMPD1[32,16]);
Rd_VPR128.4S[96,32] = float2float(TMPD1[48,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.74 FCVTL, FCVTL2 page C7-1559 line 86735 MATCH x0e217800/mask=xbfbffc00
# CONSTRUCT x4e217800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 =$float2float@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl2/1@2
# AUNIT --inst x4e217800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround"
:fcvtl2 Rd_VPR128.4S, Rn_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize Rd_VPR128.4S = float2float(TMPD1) (lane size 2 to 4)
Rd_VPR128.4S[0,32] = float2float(TMPD1[0,16]);
Rd_VPR128.4S[32,32] = float2float(TMPD1[16,16]);
Rd_VPR128.4S[64,32] = float2float(TMPD1[32,16]);
Rd_VPR128.4S[96,32] = float2float(TMPD1[48,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.75 FCVTMS (vector) page C7-1561 line 86825 MATCH x5e79b800/mask=xfffffc00
# C7.2.77 FCVTMU (vector) page C7-1566 line 87133 MATCH x7e79b800/mask=xfffffc00
# C7.2.80 FCVTNS (vector) page C7-1573 line 87534 MATCH x5e79a800/mask=xfffffc00
# C7.2.82 FCVTNU (vector) page C7-1578 line 87842 MATCH x7e79a800/mask=xfffffc00
# C7.2.84 FCVTPS (vector) page C7-1583 line 88150 MATCH x5ef9a800/mask=xfffffc00
# C7.2.86 FCVTPU (vector) page C7-1588 line 88458 MATCH x7ef9a800/mask=xfffffc00
# C7.2.90 FCVTZS (vector, integer) page C7-1598 line 89055 MATCH x5ef9b800/mask=xfffffc00
# C7.2.94 FCVTZU (vector, integer) page C7-1608 line 89640 MATCH x7ef9b800/mask=xfffffc00
# CONSTRUCT x5e79a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x5e79a800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround"
# Scalar half precision
:^fcvt_vmnemonic Rd_FPR16, Rn_FPR16
is b_3031=0b01 & b_2428=0b11110 & b_1322=0b1111001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = trunc(Rn_FPR16);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.75 FCVTMS (vector) page C7-1561 line 86825 MATCH x5e21b800/mask=xffbffc00
# C7.2.77 FCVTMU (vector) page C7-1566 line 87133 MATCH x7e21b800/mask=xffbffc00
# C7.2.80 FCVTNS (vector) page C7-1573 line 87534 MATCH x5e21a800/mask=xffbffc00
# C7.2.82 FCVTNU (vector) page C7-1578 line 87842 MATCH x7e21a800/mask=xffbffc00
# C7.2.84 FCVTPS (vector) page C7-1583 line 88150 MATCH x5ea1a800/mask=xffbffc00
# C7.2.86 FCVTPU (vector) page C7-1588 line 88458 MATCH x7ea1a800/mask=xffbffc00
# C7.2.90 FCVTZS (vector, integer) page C7-1598 line 89055 MATCH x5ea1b800/mask=xffbffc00
# C7.2.94 FCVTZU (vector, integer) page C7-1608 line 89640 MATCH x7ea1b800/mask=xffbffc00
# CONSTRUCT x5e21a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x5e21a800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround"
# Scalar single-precision and double-precision variant sz=0
:^fcvt_vmnemonic Rd_FPR32, Rn_FPR32
is b_3031=0b01 & b_2428=0b11110 & b_22=0 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = trunc(Rn_FPR32);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.75 FCVTMS (vector) page C7-1561 line 86825 MATCH x5e21b800/mask=xffbffc00
# C7.2.77 FCVTMU (vector) page C7-1566 line 87133 MATCH x7e21b800/mask=xffbffc00
# C7.2.80 FCVTNS (vector) page C7-1573 line 87534 MATCH x5e21a800/mask=xffbffc00
# C7.2.82 FCVTNU (vector) page C7-1578 line 87842 MATCH x7e21a800/mask=xffbffc00
# C7.2.84 FCVTPS (vector) page C7-1583 line 88150 MATCH x5ea1a800/mask=xffbffc00
# C7.2.86 FCVTPU (vector) page C7-1588 line 88458 MATCH x7ea1a800/mask=xffbffc00
# C7.2.90 FCVTZS (vector, integer) page C7-1598 line 89055 MATCH x5ea1b800/mask=xffbffc00
# C7.2.94 FCVTZU (vector, integer) page C7-1608 line 89640 MATCH x7ea1b800/mask=xffbffc00
# CONSTRUCT x5e61a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x5e61a800/mask=xdf7fec00 --rand dfp --status fail --comment "nofpround"
# Scalar single-precision and double-precision variant sz=1
:^fcvt_vmnemonic Rd_FPR64, Rn_FPR64
is b_3031=0b01 & b_2428=0b11110 & b_22=1 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = trunc(Rn_FPR64);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.75 FCVTMS (vector) page C7-1561 line 86825 MATCH x0e79b800/mask=xbffffc00
# C7.2.77 FCVTMU (vector) page C7-1566 line 87133 MATCH x2e79b800/mask=xbffffc00
# C7.2.80 FCVTNS (vector) page C7-1573 line 87534 MATCH x0e79a800/mask=xbffffc00
# C7.2.82 FCVTNU (vector) page C7-1578 line 87842 MATCH x2e79a800/mask=xbffffc00
# C7.2.84 FCVTPS (vector) page C7-1583 line 88150 MATCH x0ef9a800/mask=xbffffc00
# C7.2.86 FCVTPU (vector) page C7-1588 line 88458 MATCH x2ef9a800/mask=xbffffc00
# C7.2.90 FCVTZS (vector, integer) page C7-1598 line 89055 MATCH x0ef9b800/mask=xbffffc00
# C7.2.94 FCVTZU (vector, integer) page C7-1608 line 89640 MATCH x2ef9b800/mask=xbffffc00
# CONSTRUCT x0e79a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2
# AUNIT --inst x0e79a800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant Q=0
:^fcvt_vmnemonic Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_2428=0b01110 & b_1322=0b1111001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
# simd unary Rd_VPR64.4H = trunc(Rn_VPR64.4H) on lane size 2
Rd_VPR64.4H[0,16] = trunc(Rn_VPR64.4H[0,16]);
Rd_VPR64.4H[16,16] = trunc(Rn_VPR64.4H[16,16]);
Rd_VPR64.4H[32,16] = trunc(Rn_VPR64.4H[32,16]);
Rd_VPR64.4H[48,16] = trunc(Rn_VPR64.4H[48,16]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.75 FCVTMS (vector) page C7-1561 line 86825 MATCH x0e79b800/mask=xbffffc00
# C7.2.77 FCVTMU (vector) page C7-1566 line 87133 MATCH x2e79b800/mask=xbffffc00
# C7.2.80 FCVTNS (vector) page C7-1573 line 87534 MATCH x0e79a800/mask=xbffffc00
# C7.2.82 FCVTNU (vector) page C7-1578 line 87842 MATCH x2e79a800/mask=xbffffc00
# C7.2.84 FCVTPS (vector) page C7-1583 line 88150 MATCH x0ef9a800/mask=xbffffc00
# C7.2.86 FCVTPU (vector) page C7-1588 line 88458 MATCH x2ef9a800/mask=xbffffc00
# C7.2.90 FCVTZS (vector, integer) page C7-1598 line 89055 MATCH x0ef9b800/mask=xbffffc00
# C7.2.94 FCVTZU (vector, integer) page C7-1608 line 89640 MATCH x2ef9b800/mask=xbffffc00
# CONSTRUCT x4e79a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2
# AUNIT --inst x4e79a800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant Q=1
:^fcvt_vmnemonic Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2428=0b01110 & b_1322=0b1111001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
# simd unary Rd_VPR128.8H = trunc(Rn_VPR128.8H) on lane size 2
Rd_VPR128.8H[0,16] = trunc(Rn_VPR128.8H[0,16]);
Rd_VPR128.8H[16,16] = trunc(Rn_VPR128.8H[16,16]);
Rd_VPR128.8H[32,16] = trunc(Rn_VPR128.8H[32,16]);
Rd_VPR128.8H[48,16] = trunc(Rn_VPR128.8H[48,16]);
Rd_VPR128.8H[64,16] = trunc(Rn_VPR128.8H[64,16]);
Rd_VPR128.8H[80,16] = trunc(Rn_VPR128.8H[80,16]);
Rd_VPR128.8H[96,16] = trunc(Rn_VPR128.8H[96,16]);
Rd_VPR128.8H[112,16] = trunc(Rn_VPR128.8H[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.75 FCVTMS (vector) page C7-1561 line 86825 MATCH x0e21b800/mask=xbfbffc00
# C7.2.77 FCVTMU (vector) page C7-1566 line 87133 MATCH x2e21b800/mask=xbfbffc00
# C7.2.80 FCVTNS (vector) page C7-1573 line 87534 MATCH x0e21a800/mask=xbfbffc00
# C7.2.82 FCVTNU (vector) page C7-1578 line 87842 MATCH x2e21a800/mask=xbfbffc00
# C7.2.84 FCVTPS (vector) page C7-1583 line 88150 MATCH x0ea1a800/mask=xbfbffc00
# C7.2.86 FCVTPU (vector) page C7-1588 line 88458 MATCH x2ea1a800/mask=xbfbffc00
# C7.2.90 FCVTZS (vector, integer) page C7-1598 line 89055 MATCH x0ea1b800/mask=xbfbffc00
# C7.2.94 FCVTZU (vector, integer) page C7-1608 line 89640 MATCH x2ea1b800/mask=xbfbffc00
# CONSTRUCT x0e21a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4
# AUNIT --inst x0e21a800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround"
# Vector single-precision and double-precision variant SIMD 2S when sz = 0 , Q = 0
:^fcvt_vmnemonic Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2428=0b01110 & b_22=0 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
# simd unary Rd_VPR64.2S = trunc(Rn_VPR64.2S) on lane size 4
Rd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]);
Rd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.75 FCVTMS (vector) page C7-1561 line 86825 MATCH x0e21b800/mask=xbfbffc00
# C7.2.77 FCVTMU (vector) page C7-1566 line 87133 MATCH x2e21b800/mask=xbfbffc00
# C7.2.80 FCVTNS (vector) page C7-1573 line 87534 MATCH x0e21a800/mask=xbfbffc00
# C7.2.82 FCVTNU (vector) page C7-1578 line 87842 MATCH x2e21a800/mask=xbfbffc00
# C7.2.84 FCVTPS (vector) page C7-1583 line 88150 MATCH x0ea1a800/mask=xbfbffc00
# C7.2.86 FCVTPU (vector) page C7-1588 line 88458 MATCH x2ea1a800/mask=xbfbffc00
# C7.2.90 FCVTZS (vector, integer) page C7-1598 line 89055 MATCH x0ea1b800/mask=xbfbffc00
# C7.2.94 FCVTZU (vector, integer) page C7-1608 line 89640 MATCH x2ea1b800/mask=xbfbffc00
# CONSTRUCT x4e21a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4
# AUNIT --inst x4e21a800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround"
# Vector single-precision and double-precision variant SIMD 4S when sz = 0 , Q = 1
:^fcvt_vmnemonic Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2428=0b01110 & b_22=0 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
# simd unary Rd_VPR128.4S = trunc(Rn_VPR128.4S) on lane size 4
Rd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]);
Rd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]);
Rd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]);
Rd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.75 FCVTMS (vector) page C7-1561 line 86825 MATCH x0e21b800/mask=xbfbffc00
# C7.2.77 FCVTMU (vector) page C7-1566 line 87133 MATCH x2e21b800/mask=xbfbffc00
# C7.2.80 FCVTNS (vector) page C7-1573 line 87534 MATCH x0e21a800/mask=xbfbffc00
# C7.2.82 FCVTNU (vector) page C7-1578 line 87842 MATCH x2e21a800/mask=xbfbffc00
# C7.2.84 FCVTPS (vector) page C7-1583 line 88150 MATCH x0ea1a800/mask=xbfbffc00
# C7.2.86 FCVTPU (vector) page C7-1588 line 88458 MATCH x2ea1a800/mask=xbfbffc00
# C7.2.90 FCVTZS (vector, integer) page C7-1598 line 89055 MATCH x0ea1b800/mask=xbfbffc00
# C7.2.94 FCVTZU (vector, integer) page C7-1608 line 89640 MATCH x2ea1b800/mask=xbfbffc00
# CONSTRUCT x4e61a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@8
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@8
# AUNIT --inst x4e61a800/mask=xdf7fec00 --rand dfp --status fail --comment "nofpround"
# Vector single-precision and double-precision variant SIMD 2D when sz = 1 , Q = 1
:^fcvt_vmnemonic Rd_VPR128.2D, Rn_VPR128.2D
is b_31=0 & b_30=1 & b_2428=0b01110 & b_22=1 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR128.2D & Rn_VPR128.2D & Zd
{
# simd unary Rd_VPR128.2D = trunc(Rn_VPR128.2D) on lane size 8
Rd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]);
Rd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.76 FCVTMS (scalar) page C7-1564 line 87010 MATCH x1e300000/mask=x7f3ffc00
# C7.2.78 FCVTMU (scalar) page C7-1569 line 87318 MATCH x1e310000/mask=x7f3ffc00
# C7.2.81 FCVTNS (scalar) page C7-1576 line 87719 MATCH x1e200000/mask=x7f3ffc00
# C7.2.83 FCVTNU (scalar) page C7-1581 line 88027 MATCH x1e210000/mask=x7f3ffc00
# C7.2.85 FCVTPS (scalar) page C7-1586 line 88335 MATCH x1e280000/mask=x7f3ffc00
# C7.2.87 FCVTPU (scalar) page C7-1591 line 88643 MATCH x1e290000/mask=x7f3ffc00
# C7.2.92 FCVTZS (scalar, integer) page C7-1603 line 89367 MATCH x1e380000/mask=x7f3ffc00
# C7.2.96 FCVTZU (scalar, integer) page C7-1613 line 89952 MATCH x1e390000/mask=x7f3ffc00
# CONSTRUCT x1ee00000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x1ee00000/mask=xffe6fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision to 32-bit variant when sf == 0 && type == 11
:^fcvt_smnemonic Rd_GPR32, Rn_FPR16
is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR16 & Rd_GPR64
{
Rd_GPR32 = trunc(Rn_FPR16);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.76 FCVTMS (scalar) page C7-1564 line 87010 MATCH x1e300000/mask=x7f3ffc00
# C7.2.78 FCVTMU (scalar) page C7-1569 line 87318 MATCH x1e310000/mask=x7f3ffc00
# C7.2.81 FCVTNS (scalar) page C7-1576 line 87719 MATCH x1e200000/mask=x7f3ffc00
# C7.2.83 FCVTNU (scalar) page C7-1581 line 88027 MATCH x1e210000/mask=x7f3ffc00
# C7.2.85 FCVTPS (scalar) page C7-1586 line 88335 MATCH x1e280000/mask=x7f3ffc00
# C7.2.87 FCVTPU (scalar) page C7-1591 line 88643 MATCH x1e290000/mask=x7f3ffc00
# C7.2.92 FCVTZS (scalar, integer) page C7-1603 line 89367 MATCH x1e380000/mask=x7f3ffc00
# C7.2.96 FCVTZU (scalar, integer) page C7-1613 line 89952 MATCH x1e390000/mask=x7f3ffc00
# CONSTRUCT x9ee00000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x9ee00000/mask=xffe6fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision to 64-bit variant when sf == 1 && type == 11
:^fcvt_smnemonic Rd_GPR64, Rn_FPR16
is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR16
{
Rd_GPR64 = trunc(Rn_FPR16);
}
# C7.2.76 FCVTMS (scalar) page C7-1564 line 87010 MATCH x1e300000/mask=x7f3ffc00
# C7.2.78 FCVTMU (scalar) page C7-1569 line 87318 MATCH x1e310000/mask=x7f3ffc00
# C7.2.81 FCVTNS (scalar) page C7-1576 line 87719 MATCH x1e200000/mask=x7f3ffc00
# C7.2.83 FCVTNU (scalar) page C7-1581 line 88027 MATCH x1e210000/mask=x7f3ffc00
# C7.2.85 FCVTPS (scalar) page C7-1586 line 88335 MATCH x1e280000/mask=x7f3ffc00
# C7.2.87 FCVTPU (scalar) page C7-1591 line 88643 MATCH x1e290000/mask=x7f3ffc00
# C7.2.92 FCVTZS (scalar, integer) page C7-1603 line 89367 MATCH x1e380000/mask=x7f3ffc00
# C7.2.96 FCVTZU (scalar, integer) page C7-1613 line 89952 MATCH x1e390000/mask=x7f3ffc00
# CONSTRUCT x1e200000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x1e200000/mask=xffe6fc00 --rand sfp --status fail --comment "nofpround"
# Single-precision to 32-bit variant when sf == 0 && type == 00
:^fcvt_smnemonic Rd_GPR32, Rn_FPR32
is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR32 & Rd_GPR64
{
Rd_GPR32 = trunc(Rn_FPR32);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.76 FCVTMS (scalar) page C7-1564 line 87010 MATCH x1e300000/mask=x7f3ffc00
# C7.2.78 FCVTMU (scalar) page C7-1569 line 87318 MATCH x1e310000/mask=x7f3ffc00
# C7.2.81 FCVTNS (scalar) page C7-1576 line 87719 MATCH x1e200000/mask=x7f3ffc00
# C7.2.83 FCVTNU (scalar) page C7-1581 line 88027 MATCH x1e210000/mask=x7f3ffc00
# C7.2.85 FCVTPS (scalar) page C7-1586 line 88335 MATCH x1e280000/mask=x7f3ffc00
# C7.2.87 FCVTPU (scalar) page C7-1591 line 88643 MATCH x1e290000/mask=x7f3ffc00
# C7.2.92 FCVTZS (scalar, integer) page C7-1603 line 89367 MATCH x1e380000/mask=x7f3ffc00
# C7.2.96 FCVTZU (scalar, integer) page C7-1613 line 89952 MATCH x1e390000/mask=x7f3ffc00
# CONSTRUCT x9e200000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x9e200000/mask=xffe6fc00 --rand sfp --status fail --comment "nofpround"
# Single-precision to 64-bit variant when sf == 1 && type == 00
:^fcvt_smnemonic Rd_GPR64, Rn_FPR32
is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR32
{
Rd_GPR64 = trunc(Rn_FPR32);
}
# C7.2.76 FCVTMS (scalar) page C7-1564 line 87010 MATCH x1e300000/mask=x7f3ffc00
# C7.2.78 FCVTMU (scalar) page C7-1569 line 87318 MATCH x1e310000/mask=x7f3ffc00
# C7.2.81 FCVTNS (scalar) page C7-1576 line 87719 MATCH x1e200000/mask=x7f3ffc00
# C7.2.83 FCVTNU (scalar) page C7-1581 line 88027 MATCH x1e210000/mask=x7f3ffc00
# C7.2.85 FCVTPS (scalar) page C7-1586 line 88335 MATCH x1e280000/mask=x7f3ffc00
# C7.2.87 FCVTPU (scalar) page C7-1591 line 88643 MATCH x1e290000/mask=x7f3ffc00
# C7.2.92 FCVTZS (scalar, integer) page C7-1603 line 89367 MATCH x1e380000/mask=x7f3ffc00
# C7.2.96 FCVTZU (scalar, integer) page C7-1613 line 89952 MATCH x1e390000/mask=x7f3ffc00
# CONSTRUCT x1e600000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x1e600000/mask=xffe6fc00 --rand dfp --status fail --comment "nofpround"
# Double-precision to 32-bit variant when sf == 0 && type == 01
:^fcvt_smnemonic Rd_GPR32, Rn_FPR64
is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR64 & Rd_GPR64
{
Rd_GPR32 = trunc(Rn_FPR64);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.76 FCVTMS (scalar) page C7-1564 line 87010 MATCH x1e300000/mask=x7f3ffc00
# C7.2.78 FCVTMU (scalar) page C7-1569 line 87318 MATCH x1e310000/mask=x7f3ffc00
# C7.2.81 FCVTNS (scalar) page C7-1576 line 87719 MATCH x1e200000/mask=x7f3ffc00
# C7.2.83 FCVTNU (scalar) page C7-1581 line 88027 MATCH x1e210000/mask=x7f3ffc00
# C7.2.85 FCVTPS (scalar) page C7-1586 line 88335 MATCH x1e280000/mask=x7f3ffc00
# C7.2.87 FCVTPU (scalar) page C7-1591 line 88643 MATCH x1e290000/mask=x7f3ffc00
# C7.2.92 FCVTZS (scalar, integer) page C7-1603 line 89367 MATCH x1e380000/mask=x7f3ffc00
# C7.2.96 FCVTZU (scalar, integer) page C7-1613 line 89952 MATCH x1e390000/mask=x7f3ffc00
# CONSTRUCT x9e600000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
# AUNIT --inst x9e600000/mask=xffe6fc00 --rand dfp --status fail --comment "nofpround"
# Double-precision to 64-bit variant sf == 1 && type == 01
:^fcvt_smnemonic Rd_GPR64, Rn_FPR64
is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR64
{
Rd_GPR64 = trunc(Rn_FPR64);
}
# C7.2.79 FCVTN, FCVTN2 page C7-1571 line 87441 MATCH x0e216800/mask=xbfbffc00
# CONSTRUCT x0e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =$float2float@8:8
# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@8
# AUNIT --inst x0e616800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround"
:fcvtn Rd_VPR64.2S, Rn_VPR128.2D
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.2D & Rd_VPR64.2S & Rd_VPR128 & Zd
{
TMPQ1 = Rn_VPR128.2D;
# simd resize Rd_VPR64.2S = float2float(TMPQ1) (lane size 8 to 4)
Rd_VPR64.2S[0,32] = float2float(TMPQ1[0,64]);
Rd_VPR64.2S[32,32] = float2float(TMPQ1[64,64]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.79 FCVTN, FCVTN2 page C7-1571 line 87441 MATCH x0e216800/mask=xbfbffc00
# CONSTRUCT x4e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $float2float@8:8 1:1 &=$copy
# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn2/2@8
# AUNIT --inst x4e616800/mask=xfffffc00 --rand sfp --status pass --comment "ext nofpround"
:fcvtn2 Rd_VPR128.4S, Rn_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
# simd resize TMPD1 = float2float(Rn_VPR128.2D) (lane size 8 to 4)
TMPD1[0,32] = float2float(Rn_VPR128.2D[0,64]);
TMPD1[32,32] = float2float(Rn_VPR128.2D[64,64]);
# simd copy Rd_VPR128.4S element 1:1 = TMPD1 (lane size 8)
Rd_VPR128.4S[64,64] = TMPD1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.79 FCVTN, FCVTN2 page C7-1571 line 87441 MATCH x0e216800/mask=xbfbffc00
# CONSTRUCT x0e216800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =$float2float@4:8
# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@4
# AUNIT --inst x0e216800/mask=xfffffc00 --rand hfp --status fail --comment "ext nofpround"
:fcvtn Rd_VPR64.4H, Rn_VPR128.4S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.4S & Rd_VPR64.4H & Rd_VPR128 & Zd
{
TMPQ1 = Rn_VPR128.4S;
# simd resize Rd_VPR64.4H = float2float(TMPQ1) (lane size 4 to 2)
Rd_VPR64.4H[0,16] = float2float(TMPQ1[0,32]);
Rd_VPR64.4H[16,16] = float2float(TMPQ1[32,32]);
Rd_VPR64.4H[32,16] = float2float(TMPQ1[64,32]);
Rd_VPR64.4H[48,16] = float2float(TMPQ1[96,32]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.79 FCVTN, FCVTN2 page C7-1571 line 87441 MATCH x0e216800/mask=xbfbffc00
# CONSTRUCT x4e216800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $float2float@4:8 1:1 &=$copy
# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn2/2@4
# AUNIT --inst x4e216800/mask=xfffffc00 --rand hfp --status fail --comment "ext nofpround"
:fcvtn2 Rd_VPR128.8H, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
# simd resize TMPD1 = float2float(Rn_VPR128.4S) (lane size 4 to 2)
TMPD1[0,16] = float2float(Rn_VPR128.4S[0,32]);
TMPD1[16,16] = float2float(Rn_VPR128.4S[32,32]);
TMPD1[32,16] = float2float(Rn_VPR128.4S[64,32]);
TMPD1[48,16] = float2float(Rn_VPR128.4S[96,32]);
# simd copy Rd_VPR128.8H element 1:1 = TMPD1 (lane size 8)
Rd_VPR128.8H[64,64] = TMPD1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.88 FCVTXN, FCVTXN2 page C7-1593 line 88766 MATCH x7e216800/mask=xffbffc00
# CONSTRUCT x7e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float
# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtxn/2
# AUNIT --inst x7e616800/mask=xfffffc00 --rand sfp --status fail --comment "nofpround"
:fcvtxn Rd_FPR32, Rn_FPR64
is b_2331=0b011111100 & b_22=1 & b_1021=0b100001011010 & Rd_FPR32 & Rn_FPR64 & Zd
{
Rd_FPR32 = float2float(Rn_FPR64);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.88 FCVTXN, FCVTXN2 page C7-1593 line 88766 MATCH x2e216800/mask=xbfbffc00
# CONSTRUCT x2e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =$float2float@8:8
# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtxn/2@8
# AUNIT --inst x2e616800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround"
# Vector Variant
:fcvtxn Rd_VPR64.2S, Rn_VPR128.2D
is b_31=0 & b_30=0 & b_2329=0b1011100 & b_22=1 & b_1021=0b100001011010 & Rd_VPR64.2S & Rd_VPR128 & Rn_VPR128.2D & Zd
{
TMPQ1 = Rn_VPR128.2D;
# simd resize Rd_VPR64.2S = float2float(TMPQ1) (lane size 8 to 4)
Rd_VPR64.2S[0,32] = float2float(TMPQ1[0,64]);
Rd_VPR64.2S[32,32] = float2float(TMPQ1[64,64]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.88 FCVTXN, FCVTXN2 page C7-1593 line 88766 MATCH x2e216800/mask=xbfbffc00
# CONSTRUCT x6e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $float2float@8:8 1:1 &=$copy
# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtxn2/2@8
# AUNIT --inst x6e616800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround"
# Vector Variant
:fcvtxn2 Rd_VPR128.4S, Rn_VPR128.2D
is b_31=0 & b_30=1 & b_2329=0b1011100 & b_22=1 & b_1021=0b100001011010 & Rd_VPR128.4S & Rn_VPR128.2D & Rd_VPR128 & Zd
{
# simd resize TMPD1 = float2float(Rn_VPR128.2D) (lane size 8 to 4)
TMPD1[0,32] = float2float(Rn_VPR128.2D[0,64]);
TMPD1[32,32] = float2float(Rn_VPR128.2D[64,64]);
# simd copy Rd_VPR128.4S element 1:1 = TMPD1 (lane size 8)
Rd_VPR128.4S[64,64] = TMPD1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.89 FCVTZS (vector, fixed-point) page C7-1595 line 88905 MATCH x5f00fc00/mask=xff80fc00
# CONSTRUCT x5f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 zext:8 =NEON_fcvtzs/2
# AUNIT --inst x5f40fc00/mask=xffc0fc00 --rand dfp --status nopcodeop --comment "nofpround"
# Scalar variant when immh=1xxx
:fcvtzs Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_2331=0b010111110 & b_22=1 & b_1015=0b111111 & Imm_shr_imm64 & Rn_FPR64 & Rd_FPR64 & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
Rd_FPR64 = NEON_fcvtzs(Rn_FPR64, tmp1);
}
# C7.2.89 FCVTZS (vector, fixed-point) page C7-1595 line 88905 MATCH x5f00fc00/mask=xff80fc00
# CONSTRUCT x5f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzs/2
# AUNIT --inst x5f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
# Scalar variant when immh=01xx
:fcvtzs Rd_FPR32, Rn_FPR32, Imm_shr_imm32
is b_2331=0b010111110 & b_2122=0b01 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fcvtzs(Rn_FPR32, Imm_shr_imm32:4);
}
# C7.2.89 FCVTZS (vector, fixed-point) page C7-1595 line 88905 MATCH x5f00fc00/mask=xff80fc00
# CONSTRUCT x5f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2
# AUNIT --inst x5f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround"
# Scalar variant when immh=001x
:fcvtzs Rd_FPR16, Rn_FPR16, Imm_shr_imm16
is b_2331=0b010111110 & b_2022=0b001 & b_1015=0b111111 & Imm_shr_imm16 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_fcvtzs(Rn_FPR16, Imm_shr_imm16);
}
# C7.2.89 FCVTZS (vector, fixed-point) page C7-1595 line 88905 MATCH x0f00fc00/mask=xbf80fc00
# CONSTRUCT x4f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 zext:8 =NEON_fcvtzs/2@8
# AUNIT --inst x4f40fc00/mask=xffc0fc00 --rand dfp --status nopcodeop --comment "nofpround"
# Vector 2D variant when immh=1xxx Q=1 bb=b_22 cc=1 V=VPR128.2D imm=Imm_shr_imm64
:fcvtzs Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_31=0 & b_30=1 & b_2329=0b0011110 & b_22=1 & b_1015=0b111111 & Rd_VPR128.2D & Rn_VPR128.2D & Imm_shr_imm64 & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
Rd_VPR128.2D = NEON_fcvtzs(Rn_VPR128.2D, tmp1, 8:1);
}
# C7.2.89 FCVTZS (vector, fixed-point) page C7-1595 line 88905 MATCH x0f00fc00/mask=xbf80fc00
# CONSTRUCT x0f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzs/2@4
# AUNIT --inst x0f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
# Vector 2S variant when immh=01xx Q=0 bb=b_2122 cc=0b01 V=VPR64.2S imm=Imm_shr_imm32
:fcvtzs Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_31=0 & b_30=0 & b_2329=0b0011110 & b_2122=0b01 & b_1015=0b111111 & Rd_VPR64.2S & Rn_VPR64.2S & Imm_shr_imm32 & Zd
{
Rd_VPR64.2S = NEON_fcvtzs(Rn_VPR64.2S, Imm_shr_imm32:4, 4:1);
}
# C7.2.89 FCVTZS (vector, fixed-point) page C7-1595 line 88905 MATCH x0f00fc00/mask=xbf80fc00
# CONSTRUCT x4f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzs/2@4
# AUNIT --inst x4f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
# Vector 4S variant when immh=01xx Q=1 bb=b_2122 cc=0b01 V=VPR128.4S imm=Imm_shr_imm32
:fcvtzs Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_31=0 & b_30=1 & b_2329=0b0011110 & b_2122=0b01 & b_1015=0b111111 & Rd_VPR128.4S & Rn_VPR128.4S & Imm_shr_imm32 & Zd
{
Rd_VPR128.4S = NEON_fcvtzs(Rn_VPR128.4S, Imm_shr_imm32:4, 4:1);
}
# C7.2.89 FCVTZS (vector, fixed-point) page C7-1595 line 88905 MATCH x0f00fc00/mask=xbf80fc00
# CONSTRUCT x0f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2@2
# AUNIT --inst x0f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround"
# Vector 4H variant when immh=001x Q=0 bb=b_2022 cc=0b001 V=VPR64.4H imm=Imm_shr_imm16
:fcvtzs Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
is b_31=0 & b_30=0 & b_2329=0b0011110 & b_2022=0b001 & b_1015=0b111111 & Rd_VPR64.4H & Rn_VPR64.4H & Imm_shr_imm16 & Zd
{
Rd_VPR64.4H = NEON_fcvtzs(Rn_VPR64.4H, Imm_shr_imm16, 2:1);
}
# C7.2.89 FCVTZS (vector, fixed-point) page C7-1595 line 88905 MATCH x0f00fc00/mask=xbf80fc00
# CONSTRUCT x4f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2@2
# AUNIT --inst x4f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround"
# Vector 8H variant when immh=001x Q=1 bb=b_2022 cc=0b001 V=VPR128.8H imm=Imm_shr_imm16
:fcvtzs Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
is b_31=0 & b_30=1 & b_2329=0b0011110 & b_2022=0b001 & b_1015=0b111111 & Rd_VPR128.8H & Rn_VPR128.8H & Imm_shr_imm16 & Zd
{
Rd_VPR128.8H = NEON_fcvtzs(Rn_VPR128.8H, Imm_shr_imm16, 2:1);
}
# C7.2.91 FCVTZS (scalar, fixed-point) page C7-1601 line 89240 MATCH x1e180000/mask=x7f3f0000
# CONSTRUCT x1ed88000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 FBits16 f* =trunc
# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_fcvtzs/2
# AUNIT --inst x1ed88000/mask=xffff8000 --rand hfp --status noqemu --comment "nofpround"
# if sf == '0' && scale<5> == '0' then UnallocatedEncoding();
# Half-precision to 32-bit variant when sf == 0 && type == 11 G=GPR32 V=FPR16 size=2 fbits=FBits16
:fcvtzs Rd_GPR32, Rn_FPR16, FBitsOp
is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_1621=0b011000 & b_15=1 & Rd_GPR32 & Rn_FPR16 & FBitsOp & FBits16 & Rd_GPR64
{
local tmp1:2 = Rn_FPR16 f* FBits16;
Rd_GPR32 = trunc(tmp1);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.91 FCVTZS (scalar, fixed-point) page C7-1601 line 89240 MATCH x1e180000/mask=x7f3f0000
# CONSTRUCT x9ed80000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f* =trunc
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2
# AUNIT --inst x9ed80000/mask=xffff0000 --rand hfp --status noqemu --comment "nofpround"
# Half-precision to 64-bit variant when sf == 1 && type == 11 G=GPR64 V=FPR16 size=2 fbits=FBits16
:fcvtzs Rd_GPR64, Rn_FPR16, FBitsOp
is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_1621=0b011000 & Rd_GPR64 & Rn_FPR16 & FBitsOp & FBits16
{
local tmp1:2 = Rn_FPR16 f* FBitsOp;
Rd_GPR64 = trunc(tmp1);
}
# C7.2.91 FCVTZS (scalar, fixed-point) page C7-1601 line 89240 MATCH x1e180000/mask=x7f3f0000
# CONSTRUCT x1e188000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 FBits32 f* =trunc
# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzs/2
# AUNIT --inst x1e188000/mask=xffff8000 --rand sfp --status fail --comment "nofpround"
# Single-precision to 32-bit variant when sf == 0 && type == 00 G=GPR32 V=FPR32 size=4 fbits=FBits32
:fcvtzs Rd_GPR32, Rn_FPR32, FBitsOp
is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_1621=0b011000 & b_15=1 & Rd_GPR32 & Rn_FPR32 & FBitsOp & FBits32 & Rd_GPR64
{
local tmp1:4 = Rn_FPR32 f* FBits32;
Rd_GPR32 = trunc(tmp1);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.91 FCVTZS (scalar, fixed-point) page C7-1601 line 89240 MATCH x1e180000/mask=x7f3f0000
# CONSTRUCT x9e180000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 FBits32 f* =trunc
# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzs/2
# AUNIT --inst x9e180000/mask=xffff0000 --rand sfp --status pass --comment "nofpround"
# Single-precision to 64-bit variant when sf == 1 && type == 00 G=GPR64 V=FPR32 size=4 fbits=FBits32
:fcvtzs Rd_GPR64, Rn_FPR32, FBitsOp
is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_1621=0b011000 & Rd_GPR64 & Rn_FPR32 & FBitsOp & FBits32
{
local tmp1:4 = Rn_FPR32 f* FBits32;
Rd_GPR64 = trunc(tmp1);
}
# C7.2.91 FCVTZS (scalar, fixed-point) page C7-1601 line 89240 MATCH x1e180000/mask=x7f3f0000
# CONSTRUCT x1e588000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 FBits64 f* =trunc
# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_fcvtzs/2
# AUNIT --inst x1e588000/mask=xffff8000 --rand dfp --status fail --comment "nofpround"
# Double-precision to 32-bit variant when sf == 0 && type == 01 G=GPR32 V=FPR64 size=8 fbits=FBits64
:fcvtzs Rd_GPR32, Rn_FPR64, FBitsOp
is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_1621=0b011000 & b_15=1 & Rd_GPR32 & Rn_FPR64 & FBitsOp & FBits64 & Rd_GPR64
{
local tmp1:8 = Rn_FPR64 f* FBits64;
Rd_GPR32 = trunc(tmp1);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.91 FCVTZS (scalar, fixed-point) page C7-1601 line 89240 MATCH x1e180000/mask=x7f3f0000
# CONSTRUCT x9e580000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 FBits64 f* =trunc
# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_fcvtzs/2
# AUNIT --inst x9e580000/mask=xffff0000 --rand dfp --status pass --comment "nofpround"
# Double-precision to 64-bit variant when sf == 1 && type == 01 G=GPR64 V=FPR64 size=8 fbits=FBits64
:fcvtzs Rd_GPR64, Rn_FPR64, FBitsOp
is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_1621=0b011000 & Rd_GPR64 & Rn_FPR64 & FBitsOp & FBits64
{
local tmp1:8 = Rn_FPR64 f* FBits64;
Rd_GPR64 = trunc(tmp1);
}
# C7.2.93 FCVTZU (vector, fixed-point) page C7-1605 line 89490 MATCH x2f00fc00/mask=xbf80fc00
# CONSTRUCT x6f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 zext:8 =NEON_fcvtzu/2@8
# AUNIT --inst x6f40fc00/mask=xffc0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fcvtzu Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1f & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
Rd_VPR128.2D = NEON_fcvtzu(Rn_VPR128.2D, tmp1, 8:1);
}
# C7.2.93 FCVTZU (vector, fixed-point) page C7-1605 line 89490 MATCH x2f00fc00/mask=xbf80fc00
# CONSTRUCT x2f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzu/2@4
# AUNIT --inst x2f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fcvtzu Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1f & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fcvtzu(Rn_VPR64.2S, Imm_shr_imm32:4, 4:1);
}
# C7.2.93 FCVTZU (vector, fixed-point) page C7-1605 line 89490 MATCH x2f00fc00/mask=xbf80fc00
# CONSTRUCT x6f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzu/2@4
# AUNIT --inst x6f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fcvtzu Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1f & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fcvtzu(Rn_VPR128.4S, Imm_shr_imm32:4, 4:1);
}
# C7.2.93 FCVTZU (vector, fixed-point) page C7-1605 line 89490 MATCH x2f00fc00/mask=xbf80fc00
# CONSTRUCT x2f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2@2
# AUNIT --inst x2f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround"
:fcvtzu Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm16 & b_1115=0x1f & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fcvtzu(Rn_VPR64.4H, Imm_shr_imm16, 2:1);
}
# C7.2.93 FCVTZU (vector, fixed-point) page C7-1605 line 89490 MATCH x2f00fc00/mask=xbf80fc00
# CONSTRUCT x6f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2@2
# AUNIT --inst x6f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround"
:fcvtzu Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm16 & b_1115=0x1f & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fcvtzu(Rn_VPR128.8H, Imm_shr_imm16, 2:1);
}
# C7.2.93 FCVTZU (vector, fixed-point) page C7-1605 line 89490 MATCH x7f00fc00/mask=xff80fc00
# CONSTRUCT x7f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 1:2 ARG3 << int2float:2 f* fabs =trunc
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2
# AUNIT --inst x7f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround"
# FCVTZU (vector, fixed-point) Scalar immh=001x
:fcvtzu Rd_FPR16, Rn_FPR16, Imm_shr_imm32
is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR16 & Rd_FPR16 & Zd
{
local tmp1:2 = 1:2 << Imm_shr_imm32;
local tmp2:2 = int2float(tmp1);
local tmp3:2 = Rn_FPR16 f* tmp2;
local tmp4:2 = abs(tmp3);
Rd_FPR16 = trunc(tmp4);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.93 FCVTZU (vector, fixed-point) page C7-1605 line 89490 MATCH x7f00fc00/mask=xff80fc00
# CONSTRUCT x7f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 1:4 ARG3:4 << int2float:4 f* fabs =trunc
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2
# AUNIT --inst x7f20fc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
# FCVTZU (vector, fixed-point) Scalar immh=01xx
:fcvtzu Rd_FPR32, Rn_FPR32, Imm_shr_imm32
is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR32 & Rd_FPR32 & Zd
{
local tmp1:4 = 1:4 << Imm_shr_imm32:4;
local tmp2:4 = int2float(tmp1);
local tmp3:4 = Rn_FPR32 f* tmp2;
local tmp4:4 = abs(tmp3);
Rd_FPR32 = trunc(tmp4);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.93 FCVTZU (vector, fixed-point) page C7-1605 line 89490 MATCH x7f00fc00/mask=xff80fc00
# CONSTRUCT x7f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 1:8 ARG3 zext:8 << int2float:8 f* fabs =trunc
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2
# AUNIT --inst x7f40fc00/mask=xffc0fc00 --rand dfp --status fail --comment "nofpround"
# FCVTZU (vector, fixed-point) Scalar immh=1xxx
:fcvtzu Rd_FPR64, Rn_FPR64, Imm_shr_imm32
is b_2331=0b011111110 & b_22=1 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR64 & Rd_FPR64 & Zd
{
local tmp1:8 = zext(Imm_shr_imm32);
local tmp2:8 = 1:8 << tmp1;
local tmp3:8 = int2float(tmp2);
local tmp4:8 = Rn_FPR64 f* tmp3;
local tmp5:8 = abs(tmp4);
Rd_FPR64 = trunc(tmp5);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.95 FCVTZU (scalar, fixed-point) page C7-1611 line 89825 MATCH x1e190000/mask=x7f3f0000
# CONSTRUCT x1ed98000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f* =trunc
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2
# AUNIT --inst x1ed98000/mask=xffff8000 --rand hfp --status noqemu --comment "nofpround"
:fcvtzu Rd_GPR32, Rn_FPR16, FBitsOp
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=3 & fpOpcode=1 & b_15=1 & FBitsOp & FBits16 & Rn_FPR16 & Rd_GPR32 & Rd_GPR64
{
local tmp1:2 = Rn_FPR16 f* FBitsOp;
Rd_GPR32 = trunc(tmp1);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.95 FCVTZU (scalar, fixed-point) page C7-1611 line 89825 MATCH x1e190000/mask=x7f3f0000
# CONSTRUCT x9ed90000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f* =trunc
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2
# AUNIT --inst x9ed90000/mask=xffff0000 --rand hfp --status noqemu --comment "nofpround"
:fcvtzu Rd_GPR64, Rn_FPR16, FBitsOp
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=3 & fpOpcode=1 & FBitsOp & FBits16 & Rn_FPR16 & Rd_GPR64
{
local tmp1:2 = Rn_FPR16 f* FBitsOp;
Rd_GPR64 = trunc(tmp1);
}
# C7.2.95 FCVTZU (scalar, fixed-point) page C7-1611 line 89825 MATCH x1e190000/mask=x7f3f0000
# CONSTRUCT x1e598000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 FBits64 f* =trunc
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2
# AUNIT --inst x1e598000/mask=xffff8000 --rand dfp --status fail --comment "nofpround"
:fcvtzu Rd_GPR32, Rn_FPR64, FBitsOp
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=3 & fpOpcode=1 & b_15=1 & FBitsOp & FBits64 & Rn_FPR64 & Rd_GPR32 & Rd_GPR64
{
local tmp1:8 = Rn_FPR64 f* FBits64;
Rd_GPR32 = trunc(tmp1);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.95 FCVTZU (scalar, fixed-point) page C7-1611 line 89825 MATCH x1e190000/mask=x7f3f0000
# CONSTRUCT x1e198000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 FBits32 f* =trunc
# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzu/2
# AUNIT --inst x1e198000/mask=xffff8000 --rand sfp --status fail --comment "nofpround"
:fcvtzu Rd_GPR32, Rn_FPR32, FBitsOp
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=3 & fpOpcode=1 & b_15=1 & FBitsOp & FBits32 & Rn_FPR32 & Rd_GPR32 & Rd_GPR64
{
local tmp1:4 = Rn_FPR32 f* FBits32;
Rd_GPR32 = trunc(tmp1);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.95 FCVTZU (scalar, fixed-point) page C7-1611 line 89825 MATCH x1e190000/mask=x7f3f0000
# CONSTRUCT x9e590000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 FBits64 f* =trunc
# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_fcvtzu/2
# AUNIT --inst x9e590000/mask=xffff0000 --rand dfp --status fail --comment "nofpround"
:fcvtzu Rd_GPR64, Rn_FPR64, FBitsOp
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=3 & fpOpcode=1 & FBitsOp & FBits64 & Rn_FPR64 & Rd_GPR64
{
local tmp1:8 = Rn_FPR64 f* FBits64;
Rd_GPR64 = trunc(tmp1);
}
# C7.2.95 FCVTZU (scalar, fixed-point) page C7-1611 line 89825 MATCH x1e190000/mask=x7f3f0000
# CONSTRUCT x9e190000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 FBits32 f* =trunc
# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzu/2
# AUNIT --inst x9e190000/mask=xffff0000 --rand sfp --status fail --comment "nofpround"
:fcvtzu Rd_GPR64, Rn_FPR32, FBitsOp
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=3 & fpOpcode=1 & FBitsOp & FBits32 & Rn_FPR32 & Rd_GPR64
{
local tmp1:4 = Rn_FPR32 f* FBits32;
Rd_GPR64 = trunc(tmp1);
}
# C7.2.97 FDIV (vector) page C7-1615 line 90075 MATCH x2e20fc00/mask=xbfa0fc00
# CONSTRUCT x6e60fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f/@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@8
# AUNIT --inst x6e60fc00/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
:fdiv Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1f & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd infix Rd_VPR128.2D = Rn_VPR128.2D f/ Rm_VPR128.2D on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f/ Rm_VPR128.2D[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f/ Rm_VPR128.2D[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.97 FDIV (vector) page C7-1615 line 90075 MATCH x2e20fc00/mask=xbfa0fc00
# CONSTRUCT x2e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f/@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@4
# AUNIT --inst x2e20fc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
:fdiv Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1f & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix Rd_VPR64.2S = Rn_VPR64.2S f/ Rm_VPR64.2S on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f/ Rm_VPR64.2S[0,32];
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f/ Rm_VPR64.2S[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.97 FDIV (vector) page C7-1615 line 90075 MATCH x2e20fc00/mask=xbfa0fc00
# CONSTRUCT x6e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f/@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@4
# AUNIT --inst x6e20fc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
:fdiv Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1f & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd infix Rd_VPR128.4S = Rn_VPR128.4S f/ Rm_VPR128.4S on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f/ Rm_VPR128.4S[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f/ Rm_VPR128.4S[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f/ Rm_VPR128.4S[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f/ Rm_VPR128.4S[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.97 FDIV (vector) page C7-1615 line 90075 MATCH x2e403c00/mask=xbfe0fc00
# CONSTRUCT x2e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f/@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@2
# AUNIT --inst x2e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fdiv Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
# simd infix Rd_VPR64.4H = Rn_VPR64.4H f/ Rm_VPR64.4H on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f/ Rm_VPR64.4H[0,16];
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f/ Rm_VPR64.4H[16,16];
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f/ Rm_VPR64.4H[32,16];
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f/ Rm_VPR64.4H[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.97 FDIV (vector) page C7-1615 line 90075 MATCH x2e403c00/mask=xbfe0fc00
# CONSTRUCT x6e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f/@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@2
# AUNIT --inst x6e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fdiv Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
# simd infix Rd_VPR128.8H = Rn_VPR128.8H f/ Rm_VPR128.8H on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f/ Rm_VPR128.8H[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f/ Rm_VPR128.8H[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f/ Rm_VPR128.8H[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f/ Rm_VPR128.8H[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f/ Rm_VPR128.8H[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f/ Rm_VPR128.8H[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f/ Rm_VPR128.8H[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f/ Rm_VPR128.8H[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.98 FDIV (scalar) page C7-1617 line 90190 MATCH x1e201800/mask=xff20fc00
# CONSTRUCT x1e601800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f/
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2
# AUNIT --inst x1e601800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
:fdiv Rd_FPR64, Rn_FPR64, Rm_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x1 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = Rn_FPR64 f/ Rm_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.98 FDIV (scalar) page C7-1617 line 90190 MATCH x1e201800/mask=xff20fc00
# CONSTRUCT x1e201800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f/
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2
# AUNIT --inst x1e201800/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
:fdiv Rd_FPR32, Rn_FPR32, Rm_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x1 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = Rn_FPR32 f/ Rm_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.98 FDIV (scalar) page C7-1617 line 90190 MATCH x1e201800/mask=xff20fc00
# CONSTRUCT x1ee01800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f/
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2
# AUNIT --inst x1ee01800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
:fdiv Rd_FPR16, Rn_FPR16, Rm_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x1 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = Rn_FPR16 f/ Rm_FPR16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.99 FJCVTZS page C7-1619 line 90296 MATCH x1e7e0000/mask=xfffffc00
# CONSTRUCT x1e7e0000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_fjcvtzs/1
# AUNIT --inst x1e7e0000/mask=xfffffc00 --rand dfp --status noqemu --comment "nofpround"
:fjcvtzs Rd_GPR32, Rn_FPR64
is b_1031=0b0001111001111110000000 & Rd_GPR32 & Rn_FPR64 & Rd_GPR64
{
Rd_GPR32 = trunc(Rn_FPR64);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.100 FMADD page C7-1620 line 90360 MATCH x1f000000/mask=xff208000
# CONSTRUCT x1f400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmadd/3
# AUNIT --inst x1f400000/mask=xffe08000 --rand dfp --status nopcodeop --comment "nofpround"
:fmadd Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=0 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_fmadd(Rn_FPR64, Rm_FPR64, Ra_FPR64);
}
# C7.2.100 FMADD page C7-1620 line 90360 MATCH x1f000000/mask=xff208000
# CONSTRUCT x1f000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmadd/3
# AUNIT --inst x1f000000/mask=xffe08000 --rand sfp --status nopcodeop --comment "nofpround"
:fmadd Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=0 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fmadd(Rn_FPR32, Rm_FPR32, Ra_FPR32);
}
# C7.2.100 FMADD page C7-1620 line 90360 MATCH x1f000000/mask=xff208000
# CONSTRUCT x1fc00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmadd/3
# AUNIT --inst x1fc00000/mask=xffe08000 --rand hfp --status noqemu --comment "nofpround"
:fmadd Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=0 & Rm_FPR16 & b_15=0 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_fmadd(Rn_FPR16, Rm_FPR16, Ra_FPR16);
}
# C7.2.101 FMAX (vector) page C7-1622 line 90483 MATCH x0e20f400/mask=xbfa0fc00
# CONSTRUCT x4e60f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@8
# AUNIT --inst x4e60f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmax Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fmax(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.101 FMAX (vector) page C7-1622 line 90483 MATCH x0e20f400/mask=xbfa0fc00
# CONSTRUCT x0e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@4
# AUNIT --inst x0e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmax Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fmax(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.101 FMAX (vector) page C7-1622 line 90483 MATCH x0e20f400/mask=xbfa0fc00
# CONSTRUCT x4e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@4
# AUNIT --inst x4e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmax Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fmax(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.101 FMAX (vector) page C7-1622 line 90483 MATCH x0e403400/mask=xbfe0fc00
# CONSTRUCT x0e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@2
# AUNIT --inst x0e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fmax Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fmax(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.101 FMAX (vector) page C7-1622 line 90483 MATCH x0e403400/mask=xbfe0fc00
# CONSTRUCT x4e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@2
# AUNIT --inst x4e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fmax Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fmax(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.102 FMAX (scalar) page C7-1624 line 90609 MATCH x1e204800/mask=xff20fc00
# CONSTRUCT x1e604800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2
# AUNIT --inst x1e604800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmax Rd_FPR64, Rn_FPR64, Rm_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x4 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = Rn_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
local tmp1:1 = Rn_FPR64 f> Rm_FPR64;
if (tmp1) goto inst_next;
Rd_FPR64 = Rm_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.102 FMAX (scalar) page C7-1624 line 90609 MATCH x1e204800/mask=xff20fc00
# CONSTRUCT x1e204800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2
# AUNIT --inst x1e204800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmax Rd_FPR32, Rn_FPR32, Rm_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x4 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = Rn_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
local tmp1:1 = Rn_FPR32 f> Rm_FPR32;
if (tmp1) goto inst_next;
Rd_FPR32 = Rm_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.102 FMAX (scalar) page C7-1624 line 90609 MATCH x1e204800/mask=xff20fc00
# CONSTRUCT x1ee04800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2
# AUNIT --inst x1ee04800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
:fmax Rd_FPR16, Rn_FPR16, Rm_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x4 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_fmax(Rn_FPR16, Rm_FPR16);
}
# C7.2.103 FMAXNM (vector) page C7-1626 line 90711 MATCH x0e20c400/mask=xbfa0fc00
# CONSTRUCT x4e60c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@8
# AUNIT --inst x4e60c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmaxnm Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fmaxnm(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.103 FMAXNM (vector) page C7-1626 line 90711 MATCH x0e20c400/mask=xbfa0fc00
# CONSTRUCT x0e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@4
# AUNIT --inst x0e20c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmaxnm Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fmaxnm(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.103 FMAXNM (vector) page C7-1626 line 90711 MATCH x0e20c400/mask=xbfa0fc00
# CONSTRUCT x4e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@4
# AUNIT --inst x4e20c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmaxnm Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fmaxnm(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.103 FMAXNM (vector) page C7-1626 line 90711 MATCH x0e400400/mask=xbfe0fc00
# CONSTRUCT x0e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@2
# AUNIT --inst x0e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision SIMD 4H when Q = 0
:fmaxnm Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fmaxnm(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.103 FMAXNM (vector) page C7-1626 line 90711 MATCH x0e400400/mask=xbfe0fc00
# CONSTRUCT x4e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@2
# AUNIT --inst x4e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision SIMD 8H when Q = 1
:fmaxnm Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fmaxnm(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.104 FMAXNM (scalar) page C7-1628 line 90842 MATCH x1e206800/mask=xff20fc00
# CONSTRUCT x1e606800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2
# AUNIT --inst x1e606800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmaxnm Rd_FPR64, Rn_FPR64, Rm_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x6 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = Rn_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
local tmp1:1 = Rn_FPR64 f> Rm_FPR64;
if (tmp1) goto inst_next;
Rd_FPR64 = Rm_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.104 FMAXNM (scalar) page C7-1628 line 90842 MATCH x1e206800/mask=xff20fc00
# CONSTRUCT x1e206800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2
# AUNIT --inst x1e206800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmaxnm Rd_FPR32, Rn_FPR32, Rm_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x6 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = Rn_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
local tmp1:1 = Rn_FPR32 f> Rm_FPR32;
if (tmp1) goto inst_next;
Rd_FPR32 = Rm_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.104 FMAXNM (scalar) page C7-1628 line 90842 MATCH x1e206800/mask=xff20fc00
# CONSTRUCT x1ee06800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2
# AUNIT --inst x1ee06800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
:fmaxnm Rd_FPR16, Rn_FPR16, Rm_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x6 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = Rn_FPR16;
zext_zh(Zd); # zero upper 30 bytes of Zd
local tmp1:1 = Rn_FPR16 f> Rm_FPR16;
if (tmp1) goto inst_next;
Rd_FPR16 = Rm_FPR16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.105 FMAXNMP (scalar) page C7-1630 line 90948 MATCH x7e30c800/mask=xffbffc00
# CONSTRUCT x7e70c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmp/1@8
# AUNIT --inst x7e70c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmaxnmp Rd_FPR64, Rn_VPR128.2D
is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x38 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_fmaxnmp(Rn_VPR128.2D, 8:1);
}
# C7.2.105 FMAXNMP (scalar) page C7-1630 line 90948 MATCH x7e30c800/mask=xffbffc00
# CONSTRUCT x7e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmp/1@4
# AUNIT --inst x7e30c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmaxnmp Rd_FPR32, Rn_VPR64.2S
is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fmaxnmp(Rn_VPR64.2S, 4:1);
}
# C7.2.105 FMAXNMP (scalar) page C7-1630 line 90948 MATCH x5e30c800/mask=xfffffc00
# CONSTRUCT x5e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fmaxnmp/1@2
# AUNIT --inst x5e30c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant
:fmaxnmp Rd_FPR16, vRn_VPR128^".2H"
is b_1031=0b0101111000110000110010 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd
{
Rd_FPR16 = NEON_fmaxnmp(Rn_FPR32, 2:1);
}
# C7.2.106 FMAXNMP (vector) page C7-1632 line 91052 MATCH x2e20c400/mask=xbfa0fc00
# CONSTRUCT x6e60c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@8
# AUNIT --inst x6e60c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmaxnmp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fmaxnmp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.106 FMAXNMP (vector) page C7-1632 line 91052 MATCH x2e20c400/mask=xbfa0fc00
# CONSTRUCT x2e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@4
# AUNIT --inst x2e20c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmaxnmp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fmaxnmp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.106 FMAXNMP (vector) page C7-1632 line 91052 MATCH x2e20c400/mask=xbfa0fc00
# CONSTRUCT x6e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@4
# AUNIT --inst x6e20c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmaxnmp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fmaxnmp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.106 FMAXNMP (vector) page C7-1632 line 91052 MATCH x2e400400/mask=xbfe0fc00
# CONSTRUCT x2e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@2
# AUNIT --inst x2e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fmaxnmp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fmaxnmp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.106 FMAXNMP (vector) page C7-1632 line 91052 MATCH x2e400400/mask=xbfe0fc00
# CONSTRUCT x6e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@2
# AUNIT --inst x6e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fmaxnmp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fmaxnmp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.107 FMAXNMV page C7-1634 line 91185 MATCH x2e30c800/mask=xbfbffc00
# CONSTRUCT x6e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@4
# AUNIT --inst x6e30c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmaxnmv Rd_FPR32, Rn_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fmaxnmv(Rn_VPR128.4S, 4:1);
}
# C7.2.107 FMAXNMV page C7-1634 line 91185 MATCH x0e30c800/mask=xbffffc00
# CONSTRUCT x0e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@2
# AUNIT --inst x0e30c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fmaxnmv Rd_FPR16, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_1029=0b00111000110000110010 & Rd_FPR16 & Rn_VPR64.4H & Zd
{
Rd_FPR16 = NEON_fmaxnmv(Rn_VPR64.4H, 2:1);
}
# C7.2.107 FMAXNMV page C7-1634 line 91185 MATCH x0e30c800/mask=xbffffc00
# CONSTRUCT x4e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@2
# AUNIT --inst x4e30c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fmaxnmv Rd_FPR16, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_1029=0b00111000110000110010 & Rd_FPR16 & Rn_VPR128.8H & Zd
{
Rd_FPR16 = NEON_fmaxnmv(Rn_VPR128.8H, 2:1);
}
# C7.2.108 FMAXP (scalar) page C7-1636 line 91293 MATCH x7e30f800/mask=xffbffc00
# CONSTRUCT x7e70f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@8
# AUNIT --inst x7e70f800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmaxp Rd_FPR64, Rn_VPR128.2D
is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x38 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_fmaxnmv(Rn_VPR128.2D, 8:1);
}
# C7.2.108 FMAXP (scalar) page C7-1636 line 91293 MATCH x7e30f800/mask=xffbffc00
# CONSTRUCT x7e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxp/1@4
# AUNIT --inst x7e30f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmaxp Rd_FPR32, Rn_VPR64.2S
is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fmaxp(Rn_VPR64.2S, 4:1);
}
# C7.2.108 FMAXP (scalar) page C7-1636 line 91293 MATCH x5e30f800/mask=xfffffc00
# CONSTRUCT x5e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fmaxp/1@2
# AUNIT --inst x5e30f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant
:fmaxp Rd_FPR16, vRn_VPR128^".2H"
is b_1031=0b0101111000110000111110 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd
{
Rd_FPR16 = NEON_fmaxp(Rn_FPR32, 2:1);
}
# C7.2.109 FMAXP (vector) page C7-1638 line 91397 MATCH x2e20f400/mask=xbfa0fc00
# CONSTRUCT x6e60f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@8
# AUNIT --inst x6e60f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmaxp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fmaxp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.109 FMAXP (vector) page C7-1638 line 91397 MATCH x2e20f400/mask=xbfa0fc00
# CONSTRUCT x2e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@4
# AUNIT --inst x2e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmaxp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fmaxp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.109 FMAXP (vector) page C7-1638 line 91397 MATCH x2e20f400/mask=xbfa0fc00
# CONSTRUCT x6e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@4
# AUNIT --inst x6e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmaxp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fmaxp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.109 FMAXP (vector) page C7-1638 line 91397 MATCH x2e403400/mask=xbfe0fc00
# CONSTRUCT x2e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@2
# AUNIT --inst x2e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fmaxp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fmaxp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.109 FMAXP (vector) page C7-1638 line 91397 MATCH x2e403400/mask=xbfe0fc00
# CONSTRUCT x6e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@2
# AUNIT --inst x6e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fmaxp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fmaxp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.110 FMAXV page C7-1640 line 91528 MATCH x2e30f800/mask=xbfbffc00
# CONSTRUCT x6e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxv/1@4
# AUNIT --inst x6e30f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmaxv Rd_FPR32, Rn_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fmaxv(Rn_VPR128.4S, 4:1);
}
# C7.2.110 FMAXV page C7-1640 line 91528 MATCH x0e30f800/mask=xbffffc00
# CONSTRUCT x0e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxv/1@2
# AUNIT --inst x0e30f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fmaxv Rd_FPR16, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_1029=0b00111000110000111110 & Rd_FPR16 & Rn_VPR64.4H & Zd
{
Rd_FPR16 = NEON_fmaxv(Rn_VPR64.4H, 2:1);
}
# C7.2.110 FMAXV page C7-1640 line 91528 MATCH x0e30f800/mask=xbffffc00
# CONSTRUCT x4e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxv/1@2
# AUNIT --inst x4e30f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fmaxv Rd_FPR16, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_1029=0b00111000110000111110 & Rd_FPR16 & Rn_VPR128.8H & Zd
{
Rd_FPR16 = NEON_fmaxv(Rn_VPR128.8H, 2:1);
}
# C7.2.111 FMIN (vector) page C7-1642 line 91635 MATCH x0ea0f400/mask=xbfa0fc00
# CONSTRUCT x4ee0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@8
# AUNIT --inst x4ee0f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmin Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fmin(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.111 FMIN (vector) page C7-1642 line 91635 MATCH x0ea0f400/mask=xbfa0fc00
# CONSTRUCT x0ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@4
# AUNIT --inst x0ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmin Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fmin(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.111 FMIN (vector) page C7-1642 line 91635 MATCH x0ea0f400/mask=xbfa0fc00
# CONSTRUCT x4ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@4
# AUNIT --inst x4ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmin Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fmin(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.111 FMIN (vector) page C7-1642 line 91635 MATCH x0ec03400/mask=xbfe0fc00
# CONSTRUCT x0ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@2
# AUNIT --inst x0ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fmin Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fmin(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.111 FMIN (vector) page C7-1642 line 91635 MATCH x0ec03400/mask=xbfe0fc00
# CONSTRUCT x4ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@2
# AUNIT --inst x4ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fmin Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fmin(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.112 FMIN (scalar) page C7-1644 line 91761 MATCH x1e205800/mask=xff20fc00
# CONSTRUCT x1e605800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2
# AUNIT --inst x1e605800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmin Rd_FPR64, Rn_FPR64, Rm_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x5 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_fmin(Rn_FPR64, Rm_FPR64);
}
# C7.2.112 FMIN (scalar) page C7-1644 line 91761 MATCH x1e205800/mask=xff20fc00
# CONSTRUCT x1e205800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2
# AUNIT --inst x1e205800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmin Rd_FPR32, Rn_FPR32, Rm_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x5 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fmin(Rn_FPR32, Rm_FPR32);
}
# C7.2.112 FMIN (scalar) page C7-1644 line 91761 MATCH x1e205800/mask=xff20fc00
# CONSTRUCT x1ee05800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2
# AUNIT --inst x1ee05800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
:fmin Rd_FPR16, Rn_FPR16, Rm_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x5 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_fmin(Rn_FPR16, Rm_FPR16);
}
# C7.2.113 FMINNM (vector) page C7-1646 line 91863 MATCH x0ea0c400/mask=xbfa0fc00
# CONSTRUCT x4ee0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@8
# AUNIT --inst x4ee0c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fminnm Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fminnm(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.113 FMINNM (vector) page C7-1646 line 91863 MATCH x0ea0c400/mask=xbfa0fc00
# CONSTRUCT x0ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@4
# AUNIT --inst x0ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fminnm Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fminnm(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.113 FMINNM (vector) page C7-1646 line 91863 MATCH x0ea0c400/mask=xbfa0fc00
# CONSTRUCT x4ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@4
# AUNIT --inst x4ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fminnm Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fminnm(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.113 FMINNM (vector) page C7-1646 line 91863 MATCH x0ec00400/mask=xbfe0fc00
# CONSTRUCT x0ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@2
# AUNIT --inst x0ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fminnm Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fminnm(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.113 FMINNM (vector) page C7-1646 line 91863 MATCH x0ec00400/mask=xbfe0fc00
# CONSTRUCT x4ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@2
# AUNIT --inst x4ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fminnm Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fminnm(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.114 FMINNM (scalar) page C7-1648 line 91994 MATCH x1e207800/mask=xff20fc00
# CONSTRUCT x1e607800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2
# AUNIT --inst x1e607800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fminnm Rd_FPR64, Rn_FPR64, Rm_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x7 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_fminnm(Rn_FPR64, Rm_FPR64);
}
# C7.2.114 FMINNM (scalar) page C7-1648 line 91994 MATCH x1e207800/mask=xff20fc00
# CONSTRUCT x1e207800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2
# AUNIT --inst x1e207800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fminnm Rd_FPR32, Rn_FPR32, Rm_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x7 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fminnm(Rn_FPR32, Rm_FPR32);
}
# C7.2.114 FMINNM (scalar) page C7-1648 line 91994 MATCH x1e207800/mask=xff20fc00
# CONSTRUCT x1ee07800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2
# AUNIT --inst x1ee07800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
:fminnm Rd_FPR16, Rn_FPR16, Rm_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x7 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_fminnm(Rn_FPR16, Rm_FPR16);
}
# C7.2.115 FMINNMP (scalar) page C7-1650 line 92101 MATCH x7eb0c800/mask=xffbffc00
# CONSTRUCT x7ef0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmp/1@8
# AUNIT --inst x7ef0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
:fminnmp Rd_FPR64, Rn_VPR128.2D
is b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x38 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_fminnmp(Rn_VPR128.2D, 8:1);
}
# C7.2.115 FMINNMP (scalar) page C7-1650 line 92101 MATCH x7eb0c800/mask=xffbffc00
# CONSTRUCT x7eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmp/1@4
# AUNIT --inst x7eb0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
:fminnmp Rd_FPR32, Rn_VPR64.2S
is b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fminnmp(Rn_VPR64.2S, 4:1);
}
# C7.2.115 FMINNMP (scalar) page C7-1650 line 92101 MATCH x5eb0c800/mask=xfffffc00
# CONSTRUCT x5eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fminnmp/1@2
# AUNIT --inst x5eb0c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant
:fminnmp Rd_FPR16, vRn_VPR128^".2H"
is b_1031=0b0101111010110000110010 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd
{
Rd_FPR16 = NEON_fminnmp(Rn_FPR32, 2:1);
}
# C7.2.116 FMINNMP (vector) page C7-1652 line 92205 MATCH x2ea0c400/mask=xbfa0fc00
# CONSTRUCT x6ee0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@8
# AUNIT --inst x6ee0c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fminnmp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fminnmp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.116 FMINNMP (vector) page C7-1652 line 92205 MATCH x2ea0c400/mask=xbfa0fc00
# CONSTRUCT x2ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@4
# AUNIT --inst x2ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fminnmp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fminnmp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.116 FMINNMP (vector) page C7-1652 line 92205 MATCH x2ea0c400/mask=xbfa0fc00
# CONSTRUCT x6ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@4
# AUNIT --inst x6ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fminnmp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fminnmp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.116 FMINNMP (vector) page C7-1652 line 92205 MATCH x2ec00400/mask=xbfe0fc00
# CONSTRUCT x2ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@2
# AUNIT --inst x2ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fminnmp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fminnmp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.116 FMINNMP (vector) page C7-1652 line 92205 MATCH x2ec00400/mask=xbfe0fc00
# CONSTRUCT x6ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@2
# AUNIT --inst x6ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fminnmp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fminnmp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.117 FMINNMV page C7-1654 line 92338 MATCH x2eb0c800/mask=xbfbffc00
# CONSTRUCT x6eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmv/1@4
# AUNIT --inst x6eb0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
:fminnmv Rd_FPR32, Rn_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fminnmv(Rn_VPR128.4S, 4:1);
}
# C7.2.117 FMINNMV page C7-1654 line 92338 MATCH x0eb0c800/mask=xbffffc00
# CONSTRUCT x0eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmv/1@2
# AUNIT --inst x0eb0c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fminnmv Rd_FPR16, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_1029=0b00111010110000110010 & Rd_FPR16 & Rn_VPR64.4H & Zd
{
Rd_FPR16 = NEON_fminnmv(Rn_VPR64.4H, 2:1);
}
# C7.2.117 FMINNMV page C7-1654 line 92338 MATCH x0eb0c800/mask=xbffffc00
# CONSTRUCT x4eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmv/1@2
# AUNIT --inst x4eb0c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fminnmv Rd_FPR16, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_1029=0b00111010110000110010 & Rd_FPR16 & Rn_VPR128.8H & Zd
{
Rd_FPR16 = NEON_fminnmv(Rn_VPR128.8H, 2:1);
}
# C7.2.118 FMINP (scalar) page C7-1656 line 92446 MATCH x7eb0f800/mask=xffbffc00
# CONSTRUCT x7ef0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fminp/1@8
# AUNIT --inst x7ef0f800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
:fminp Rd_FPR64, Rn_VPR128.2D
is b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x38 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_fminp(Rn_VPR128.2D, 8:1);
}
# C7.2.118 FMINP (scalar) page C7-1656 line 92446 MATCH x7eb0f800/mask=xffbffc00
# CONSTRUCT x7eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fminp/1@4
# AUNIT --inst x7eb0f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
:fminp Rd_FPR32, Rn_VPR64.2S
is b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fminp(Rn_VPR64.2S, 4:1);
}
# C7.2.118 FMINP (scalar) page C7-1656 line 92446 MATCH x5eb0f800/mask=xfffffc00
# CONSTRUCT x5eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fminp/1@2
# AUNIT --inst x5eb0f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant
:fminp Rd_FPR16, vRn_VPR128^".2H"
is b_1031=0b0101111010110000111110 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd
{
Rd_FPR16 = NEON_fminp(Rn_FPR32, 2:1);
}
# C7.2.119 FMINP (vector) page C7-1658 line 92550 MATCH x2ea0f400/mask=xbfa0fc00
# CONSTRUCT x6ee0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@8
# AUNIT --inst x6ee0f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fminp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fminp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.119 FMINP (vector) page C7-1658 line 92550 MATCH x2ea0f400/mask=xbfa0fc00
# CONSTRUCT x2ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@4
# AUNIT --inst x2ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fminp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fminp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.119 FMINP (vector) page C7-1658 line 92550 MATCH x2ea0f400/mask=xbfa0fc00
# CONSTRUCT x6ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@4
# AUNIT --inst x6ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fminp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fminp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.119 FMINP (vector) page C7-1658 line 92550 MATCH x2ec03400/mask=xbfe0fc00
# CONSTRUCT x2ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@2
# AUNIT --inst x2ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fminp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fminp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.119 FMINP (vector) page C7-1658 line 92550 MATCH x2ec03400/mask=xbfe0fc00
# CONSTRUCT x6ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@2
# AUNIT --inst x6ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fminp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fminp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.120 FMINV page C7-1660 line 92681 MATCH x2eb0f800/mask=xbfbffc00
# CONSTRUCT x6eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fminv/1@4
# AUNIT --inst x6eb0f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
:fminv Rd_FPR32, Rn_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fminv(Rn_VPR128.4S, 4:1);
}
# C7.2.120 FMINV page C7-1660 line 92681 MATCH x0eb0f800/mask=xbffffc00
# CONSTRUCT x0eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fminv/1@2
# AUNIT --inst x0eb0f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fminv Rd_FPR16, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_1029=0b00111010110000111110 & Rd_FPR16 & Rn_VPR64.4H & Zd
{
Rd_FPR16 = NEON_fminv(Rn_VPR64.4H, 2:1);
}
# C7.2.120 FMINV page C7-1660 line 92681 MATCH x0eb0f800/mask=xbffffc00
# CONSTRUCT x4eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fminv/1@2
# AUNIT --inst x4eb0f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fminv Rd_FPR16, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_1029=0b00111010110000111110 & Rd_FPR16 & Rn_VPR128.8H & Zd
{
Rd_FPR16 = NEON_fminv(Rn_VPR128.8H, 2:1);
}
# C7.2.121 FMLA (by element) page C7-1662 line 92788 MATCH x0f801000/mask=xbf80f400
# CONSTRUCT x4fc01000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f* &=$f+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@8
# AUNIT --inst x4fc01000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
:fmla Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=3 & b_2121=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & b_1215=0x1 & b_1010=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd element Re_VPR128.D[vIndex] lane size 8
local tmp1:8 = Re_VPR128.D.vIndex;
# simd infix TMPQ1 = Rn_VPR128.2D f* tmp1 on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] f* tmp1;
TMPQ1[64,64] = Rn_VPR128.2D[64,64] f* tmp1;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D f+ TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f+ TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f+ TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.121 FMLA (by element) page C7-1662 line 92788 MATCH x0f801000/mask=xbf80f400
# CONSTRUCT x0f801000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f* &=$f+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4
# AUNIT --inst x0f801000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround"
:fmla Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x1 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix TMPD1 = Rn_VPR64.2S f* tmp1 on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] f* tmp1;
TMPD1[32,32] = Rn_VPR64.2S[32,32] f* tmp1;
# simd infix Rd_VPR64.2S = Rd_VPR64.2S f+ TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f+ TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f+ TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.121 FMLA (by element) page C7-1662 line 92788 MATCH x0f801000/mask=xbf80f400
# CONSTRUCT x4f801000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f* &=$f+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4
# AUNIT --inst x4f801000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround"
:fmla Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x1 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix TMPQ1 = Rn_VPR128.4S f* tmp1 on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] f* tmp1;
TMPQ1[32,32] = Rn_VPR128.4S[32,32] f* tmp1;
TMPQ1[64,32] = Rn_VPR128.4S[64,32] f* tmp1;
TMPQ1[96,32] = Rn_VPR128.4S[96,32] f* tmp1;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S f+ TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f+ TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f+ TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f+ TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f+ TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.121 FMLA (by element) page C7-1662 line 92788 MATCH x5f001000/mask=xffc0f400
# CONSTRUCT x5f001000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f* &=f+
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2
# AUNIT --inst x5f001000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
# Scalar half-precision variant
:fmla Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
is b_2231=0b0101111100 & b_1215=0b0001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp2:2 = Rn_FPR16 f* tmp1;
Rd_FPR16 = Rd_FPR16 f+ tmp2;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.121 FMLA (by element) page C7-1662 line 92788 MATCH x5f801000/mask=xff80f400
# CONSTRUCT x5f801000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f* &=f+
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4
# AUNIT --inst x5f801000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround"
# Scalar, single-precision and double-precision variant, sz=0
:fmla Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex
is b_2331=0b010111111 & b_22=0 & b_1215=0b0001 & b_10=0 & Re_VPR128.S & vIndex & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
local tmp2:4 = Rn_FPR32 f* tmp1;
Rd_FPR32 = Rd_FPR32 f+ tmp2;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.121 FMLA (by element) page C7-1662 line 92788 MATCH x5f801000/mask=xff80f400
# CONSTRUCT x5fc01000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f* &=f+
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@8
# AUNIT --inst x5fc01000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
# Scalar, single-precision and double-precision variant, sz=1
:fmla Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex
is b_2331=0b010111111 & b_22=1 & b_21=0 & b_1215=0b0001 & b_10=0 & Re_VPR128.D & vIndex & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Zd
{
# simd element Re_VPR128.D[vIndex] lane size 8
local tmp1:8 = Re_VPR128.D.vIndex;
local tmp2:8 = Rn_FPR64 f* tmp1;
Rd_FPR64 = Rd_FPR64 f+ tmp2;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.121 FMLA (by element) page C7-1662 line 92788 MATCH x0f001000/mask=xbfc0f400
# CONSTRUCT x0f001000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f* &=$f+$@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2
# AUNIT --inst x0f001000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
# Vector, half-precision variant SIMD 4H when Q = 0
:fmla Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=0 & b_2229=0b00111100 & b_1215=0b0001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPD1 = Rn_VPR64.4H f* tmp1 on lane size 2
TMPD1[0,16] = Rn_VPR64.4H[0,16] f* tmp1;
TMPD1[16,16] = Rn_VPR64.4H[16,16] f* tmp1;
TMPD1[32,16] = Rn_VPR64.4H[32,16] f* tmp1;
TMPD1[48,16] = Rn_VPR64.4H[48,16] f* tmp1;
# simd infix Rd_VPR64.4H = Rd_VPR64.4H f+ TMPD1 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] f+ TMPD1[0,16];
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] f+ TMPD1[16,16];
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] f+ TMPD1[32,16];
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] f+ TMPD1[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.121 FMLA (by element) page C7-1662 line 92788 MATCH x0f001000/mask=xbfc0f400
# CONSTRUCT x4f001000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f* &=$f+$@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2
# AUNIT --inst x4f001000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
# Vector, half-precision variant SIMD 8H when Q = 1
:fmla Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=1 & b_2229=0b00111100 & b_1215=0b0001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPQ1 = Rn_VPR128.8H f* tmp1 on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] f* tmp1;
TMPQ1[16,16] = Rn_VPR128.8H[16,16] f* tmp1;
TMPQ1[32,16] = Rn_VPR128.8H[32,16] f* tmp1;
TMPQ1[48,16] = Rn_VPR128.8H[48,16] f* tmp1;
TMPQ1[64,16] = Rn_VPR128.8H[64,16] f* tmp1;
TMPQ1[80,16] = Rn_VPR128.8H[80,16] f* tmp1;
TMPQ1[96,16] = Rn_VPR128.8H[96,16] f* tmp1;
TMPQ1[112,16] = Rn_VPR128.8H[112,16] f* tmp1;
# simd infix Rd_VPR128.8H = Rd_VPR128.8H f+ TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] f+ TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] f+ TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] f+ TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] f+ TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] f+ TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] f+ TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] f+ TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] f+ TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.122 FMLA (vector) page C7-1666 line 93022 MATCH x0e20cc00/mask=xbfa0fc00
# CONSTRUCT x4e60cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f*@8 &=$f+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@8
# AUNIT --inst x4e60cc00/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
:fmla Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.2D & b_1115=0x19 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd infix TMPQ1 = Rn_VPR128.2D f* Rm_VPR128.2D on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] f* Rm_VPR128.2D[0,64];
TMPQ1[64,64] = Rn_VPR128.2D[64,64] f* Rm_VPR128.2D[64,64];
# simd infix Rd_VPR128.2D = Rd_VPR128.2D f+ TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f+ TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f+ TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.122 FMLA (vector) page C7-1666 line 93022 MATCH x0e20cc00/mask=xbfa0fc00
# CONSTRUCT x0e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4
# AUNIT --inst x0e20cc00/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
:fmla Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.2S & b_1115=0x19 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Re_VPR128 & Zd
{
# simd infix TMPD1 = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32];
TMPD1[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32];
# simd infix Rd_VPR64.2S = Rd_VPR64.2S f+ TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f+ TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f+ TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.122 FMLA (vector) page C7-1666 line 93022 MATCH x0e20cc00/mask=xbfa0fc00
# CONSTRUCT x4e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4
# AUNIT --inst x4e20cc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
:fmla Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.4S & b_1115=0x19 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] f* Rm_VPR128.4S[0,32];
TMPQ1[32,32] = Rn_VPR128.4S[32,32] f* Rm_VPR128.4S[32,32];
TMPQ1[64,32] = Rn_VPR128.4S[64,32] f* Rm_VPR128.4S[64,32];
TMPQ1[96,32] = Rn_VPR128.4S[96,32] f* Rm_VPR128.4S[96,32];
# simd infix Rd_VPR128.4S = Rd_VPR128.4S f+ TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f+ TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f+ TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f+ TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f+ TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.122 FMLA (vector) page C7-1666 line 93022 MATCH x0e400c00/mask=xbfe0fc00
# CONSTRUCT x0e400c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2
# AUNIT --inst x0e400c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fmla Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
# simd infix TMPD1 = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 4
TMPD1[0,32] = Rn_VPR64.4H[0,32] f* Rm_VPR64.4H[0,32];
TMPD1[32,32] = Rn_VPR64.4H[32,32] f* Rm_VPR64.4H[32,32];
# simd infix Rd_VPR64.4H = Rd_VPR64.4H f+ TMPD1 on lane size 4
Rd_VPR64.4H[0,32] = Rd_VPR64.4H[0,32] f+ TMPD1[0,32];
Rd_VPR64.4H[32,32] = Rd_VPR64.4H[32,32] f+ TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.122 FMLA (vector) page C7-1666 line 93022 MATCH x0e400c00/mask=xbfe0fc00
# CONSTRUCT x4e400c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2
# AUNIT --inst x4e400c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fmla Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 4
TMPQ1[0,32] = Rn_VPR128.8H[0,32] f* Rm_VPR128.8H[0,32];
TMPQ1[32,32] = Rn_VPR128.8H[32,32] f* Rm_VPR128.8H[32,32];
TMPQ1[64,32] = Rn_VPR128.8H[64,32] f* Rm_VPR128.8H[64,32];
TMPQ1[96,32] = Rn_VPR128.8H[96,32] f* Rm_VPR128.8H[96,32];
# simd infix Rd_VPR128.8H = Rd_VPR128.8H f+ TMPQ1 on lane size 4
Rd_VPR128.8H[0,32] = Rd_VPR128.8H[0,32] f+ TMPQ1[0,32];
Rd_VPR128.8H[32,32] = Rd_VPR128.8H[32,32] f+ TMPQ1[32,32];
Rd_VPR128.8H[64,32] = Rd_VPR128.8H[64,32] f+ TMPQ1[64,32];
Rd_VPR128.8H[96,32] = Rd_VPR128.8H[96,32] f+ TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.123 FMLAL, FMLAL2 (by element) page C7-1668 line 93140 MATCH x0f800000/mask=xbfc0f400
# CONSTRUCT x0f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[0]:4 ARG3 $f* $float2float@2:8 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@4
# AUNIT --inst x0f800000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 2S when Q = 0
:fmlal Rd_VPR64.2S, vRn_VPR64^".2H", Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=0 & b_2329=0b0011111 & b_22=0 & b_1215=0b0000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd
{
TMPS1 = Rn_VPR64[0,32];
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2
TMPS2[0,16] = TMPS1[0,16] f* tmp2;
TMPS2[16,16] = TMPS1[16,16] f* tmp2;
# simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4)
TMPD3[0,32] = float2float(TMPS2[0,16]);
TMPD3[32,32] = float2float(TMPS2[16,16]);
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD3 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD3[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD3[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.123 FMLAL, FMLAL2 (by element) page C7-1668 line 93140 MATCH x0f800000/mask=xbfc0f400
# CONSTRUCT x4f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[0]:8 ARG3 $f* $float2float@2:16 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@2
# AUNIT --inst x4f800000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 4S when Q = 1
:fmlal Rd_VPR128.4S, vRn_VPR128^".4H", Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=0 & b_1215=0b0000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd
{
TMPD1 = Rn_VPR128[0,64];
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2
TMPD2[0,16] = TMPD1[0,16] f* tmp2;
TMPD2[16,16] = TMPD1[16,16] f* tmp2;
TMPD2[32,16] = TMPD1[32,16] f* tmp2;
TMPD2[48,16] = TMPD1[48,16] f* tmp2;
# simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)
TMPQ3[0,32] = float2float(TMPD2[0,16]);
TMPQ3[32,32] = float2float(TMPD2[16,16]);
TMPQ3[64,32] = float2float(TMPD2[32,16]);
TMPQ3[96,32] = float2float(TMPD2[48,16]);
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.123 FMLAL, FMLAL2 (by element) page C7-1668 line 93140 MATCH x2f808000/mask=xbfc0f400
# CONSTRUCT x2f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:4 ARG3 $f* $float2float@2:8 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2
# AUNIT --inst x2f808000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 2S when Q = 0
:fmlal2 Rd_VPR64.2S, vRn_VPR64^".2H", Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=0 & b_2329=0b1011111 & b_22=0 & b_1215=0b1000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd
{
TMPS1 = Rn_VPR64[32,32];
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2
TMPS2[0,16] = TMPS1[0,16] f* tmp2;
TMPS2[16,16] = TMPS1[16,16] f* tmp2;
# simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4)
TMPD3[0,32] = float2float(TMPS2[0,16]);
TMPD3[32,32] = float2float(TMPS2[16,16]);
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD3 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD3[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD3[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.123 FMLAL, FMLAL2 (by element) page C7-1668 line 93140 MATCH x2f808000/mask=xbfc0f400
# CONSTRUCT x6f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 ARG3 $f* $float2float@2:16 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2
# AUNIT --inst x6f808000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 4S when Q = 1
:fmlal2 Rd_VPR128.4S, vRn_VPR128^".4H", Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=1 & b_2329=0b1011111 & b_22=0 & b_1215=0b1000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd
{
TMPD1 = Rn_VPR128[64,64];
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2
TMPD2[0,16] = TMPD1[0,16] f* tmp2;
TMPD2[16,16] = TMPD1[16,16] f* tmp2;
TMPD2[32,16] = TMPD1[32,16] f* tmp2;
TMPD2[48,16] = TMPD1[48,16] f* tmp2;
# simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)
TMPQ3[0,32] = float2float(TMPD2[0,16]);
TMPQ3[32,32] = float2float(TMPD2[16,16]);
TMPQ3[64,32] = float2float(TMPD2[32,16]);
TMPQ3[96,32] = float2float(TMPD2[48,16]);
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.124 FMLAL, FMLAL2 (vector) page C7-1670 line 93272 MATCH x0e20ec00/mask=xbfe0fc00
# CONSTRUCT x0e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[0]:4 ARG3[0]:4 $f*@2 $float2float@2:8 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@2
# AUNIT --inst x0e20ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 2S when Q = 0
:fmlal Rd_VPR64.2S, vRn_VPR64^".2H", vRm_VPR64^".2H"
is b_31=0 & b_30=0 & b_2329=0b0011100 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR64 & Rm_VPR64 & Zd
{
TMPS1 = Rn_VPR64[0,32];
TMPS2 = Rm_VPR64[0,32];
# simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2
TMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16];
TMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16];
# simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4)
TMPD4[0,32] = float2float(TMPS3[0,16]);
TMPD4[32,32] = float2float(TMPS3[16,16]);
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD4 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD4[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD4[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.124 FMLAL, FMLAL2 (vector) page C7-1670 line 93272 MATCH x0e20ec00/mask=xbfe0fc00
# CONSTRUCT x4e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[0]:8 ARG3[0]:8 $f*@2 $float2float@2:16 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@2
# AUNIT --inst x4e20ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 4S when Q = 1
:fmlal Rd_VPR128.4S, vRn_VPR128^".4H", Rm_VPR64.4H
is b_31=0 & b_30=1 & b_2329=0b0011100 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd
{
TMPD1 = Rn_VPR128[0,64];
TMPD2 = Rm_VPR64.4H[0,64];
# simd infix TMPD3 = TMPD1 f* TMPD2 on lane size 2
TMPD3[0,16] = TMPD1[0,16] f* TMPD2[0,16];
TMPD3[16,16] = TMPD1[16,16] f* TMPD2[16,16];
TMPD3[32,16] = TMPD1[32,16] f* TMPD2[32,16];
TMPD3[48,16] = TMPD1[48,16] f* TMPD2[48,16];
# simd resize TMPQ4 = float2float(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = float2float(TMPD3[0,16]);
TMPQ4[32,32] = float2float(TMPD3[16,16]);
TMPQ4[64,32] = float2float(TMPD3[32,16]);
TMPQ4[96,32] = float2float(TMPD3[48,16]);
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.124 FMLAL, FMLAL2 (vector) page C7-1670 line 93272 MATCH x2e20cc00/mask=xbfe0fc00
# CONSTRUCT x2e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:4 ARG3[1]:4 $f*@2 $float2float@2:8 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2
# AUNIT --inst x2e20cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 2S when Q = 0
:fmlal2 Rd_VPR64.2S, vRn_VPR64^".2H", vRm_VPR128^".2H"
is b_31=0 & b_30=0 & b_2329=0b1011100 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR128 & Rm_VPR128 & Zd
{
TMPS1 = Rn_VPR64[32,32];
TMPS2 = Rm_VPR128[32,32];
# simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2
TMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16];
TMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16];
# simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4)
TMPD4[0,32] = float2float(TMPS3[0,16]);
TMPD4[32,32] = float2float(TMPS3[16,16]);
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD4 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD4[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD4[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.124 FMLAL, FMLAL2 (vector) page C7-1670 line 93272 MATCH x2e20cc00/mask=xbfe0fc00
# CONSTRUCT x6e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 ARG3 $f*@2 $float2float@2:16 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2
# AUNIT --inst x6e20cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 4S when Q = 1
:fmlal2 Rd_VPR128.4S, vRn_VPR128^".4H", Rm_VPR64.4H
is b_31=0 & b_30=1 & b_2329=0b1011100 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd
{
TMPD1 = Rn_VPR128[64,64];
# simd infix TMPD2 = TMPD1 f* Rm_VPR64.4H on lane size 2
TMPD2[0,16] = TMPD1[0,16] f* Rm_VPR64.4H[0,16];
TMPD2[16,16] = TMPD1[16,16] f* Rm_VPR64.4H[16,16];
TMPD2[32,16] = TMPD1[32,16] f* Rm_VPR64.4H[32,16];
TMPD2[48,16] = TMPD1[48,16] f* Rm_VPR64.4H[48,16];
# simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)
TMPQ3[0,32] = float2float(TMPD2[0,16]);
TMPQ3[32,32] = float2float(TMPD2[16,16]);
TMPQ3[64,32] = float2float(TMPD2[32,16]);
TMPQ3[96,32] = float2float(TMPD2[48,16]);
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.125 FMLS (by element) page C7-1672 line 93397 MATCH x0f805000/mask=xbf80f400
# CONSTRUCT x4fc05000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f* &=$f-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@8
# AUNIT --inst x4fc05000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
:fmls Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=3 & b_2121=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & b_1215=0x5 & b_1010=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd element Re_VPR128.D[vIndex] lane size 8
local tmp1:8 = Re_VPR128.D.vIndex;
# simd infix TMPQ1 = Rn_VPR128.2D f* tmp1 on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] f* tmp1;
TMPQ1[64,64] = Rn_VPR128.2D[64,64] f* tmp1;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D f- TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f- TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f- TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.125 FMLS (by element) page C7-1672 line 93397 MATCH x0f805000/mask=xbf80f400
# CONSTRUCT x0f805000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f* &=$f-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4
# AUNIT --inst x0f805000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround"
:fmls Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x5 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix TMPD1 = Rn_VPR64.2S f* tmp1 on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] f* tmp1;
TMPD1[32,32] = Rn_VPR64.2S[32,32] f* tmp1;
# simd infix Rd_VPR64.2S = Rd_VPR64.2S f- TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f- TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f- TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.125 FMLS (by element) page C7-1672 line 93397 MATCH x0f805000/mask=xbf80f400
# CONSTRUCT x4f805000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f* &=$f-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4
# AUNIT --inst x4f805000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround"
:fmls Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x5 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix TMPQ1 = Rn_VPR128.4S f* tmp1 on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] f* tmp1;
TMPQ1[32,32] = Rn_VPR128.4S[32,32] f* tmp1;
TMPQ1[64,32] = Rn_VPR128.4S[64,32] f* tmp1;
TMPQ1[96,32] = Rn_VPR128.4S[96,32] f* tmp1;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S f- TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f- TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f- TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f- TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f- TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.125 FMLS (by element) page C7-1672 line 93397 MATCH x5f005000/mask=xffc0f400
# CONSTRUCT x5f005000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f* &=f-
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2
# AUNIT --inst x5f005000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
# Scalar half-precision variant
:fmls Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
is b_2231=0b0101111100 & b_1215=0b0101 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp2:2 = Rn_FPR16 f* tmp1;
Rd_FPR16 = Rd_FPR16 f- tmp2;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.125 FMLS (by element) page C7-1672 line 93397 MATCH x5f805000/mask=xff80f400
# CONSTRUCT x5f805000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f* &=f-
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4
# AUNIT --inst x5f805000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround"
# Scalar, single-precision and double-precision variant, sz=0
:fmls Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex
is b_2331=0b010111111 & b_22=0 & b_1215=0b0101 & b_10=0 & Re_VPR128.S & vIndex & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
local tmp2:4 = Rn_FPR32 f* tmp1;
Rd_FPR32 = Rd_FPR32 f- tmp2;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.125 FMLS (by element) page C7-1672 line 93397 MATCH x5f805000/mask=xff80f400
# CONSTRUCT x5fc05000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f* &=f-
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@8
# AUNIT --inst x5fc05000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
# Scalar, single-precision and double-precision variant, sz=1
:fmls Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex
is b_2331=0b010111111 & b_22=1 & b_21=0 & b_1215=0b0101 & b_10=0 & Re_VPR128.D & vIndex & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Zd
{
# simd element Re_VPR128.D[vIndex] lane size 8
local tmp1:8 = Re_VPR128.D.vIndex;
local tmp2:8 = Rn_FPR64 f* tmp1;
Rd_FPR64 = Rd_FPR64 f- tmp2;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.125 FMLS (by element) page C7-1672 line 93397 MATCH x0f005000/mask=xbfc0f400
# CONSTRUCT x0f005000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f*@2 &=$f-$@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2
# AUNIT --inst x0f005000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
# Vector, half-precision variant SIMD 4H when Q = 0
:fmls Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=0 & b_2229=0b00111100 & b_1215=0b0101 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPD1 = Rn_VPR64.4H f* tmp1 on lane size 2
TMPD1[0,16] = Rn_VPR64.4H[0,16] f* tmp1;
TMPD1[16,16] = Rn_VPR64.4H[16,16] f* tmp1;
TMPD1[32,16] = Rn_VPR64.4H[32,16] f* tmp1;
TMPD1[48,16] = Rn_VPR64.4H[48,16] f* tmp1;
# simd infix Rd_VPR64.4H = Rd_VPR64.4H f- TMPD1 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] f- TMPD1[0,16];
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] f- TMPD1[16,16];
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] f- TMPD1[32,16];
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] f- TMPD1[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.125 FMLS (by element) page C7-1672 line 93397 MATCH x0f005000/mask=xbfc0f400
# CONSTRUCT x4f005000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f*@2 &=$f-$@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2
# AUNIT --inst x4f005000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
# Vector, half-precision variant SIMD 8H when Q = 1
:fmls Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=1 & b_2229=0b00111100 & b_1215=0b0101 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPQ1 = Rn_VPR128.8H f* tmp1 on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] f* tmp1;
TMPQ1[16,16] = Rn_VPR128.8H[16,16] f* tmp1;
TMPQ1[32,16] = Rn_VPR128.8H[32,16] f* tmp1;
TMPQ1[48,16] = Rn_VPR128.8H[48,16] f* tmp1;
TMPQ1[64,16] = Rn_VPR128.8H[64,16] f* tmp1;
TMPQ1[80,16] = Rn_VPR128.8H[80,16] f* tmp1;
TMPQ1[96,16] = Rn_VPR128.8H[96,16] f* tmp1;
TMPQ1[112,16] = Rn_VPR128.8H[112,16] f* tmp1;
# simd infix Rd_VPR128.8H = Rd_VPR128.8H f- TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] f- TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] f- TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] f- TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] f- TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] f- TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] f- TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] f- TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] f- TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.126 FMLS (vector) page C7-1676 line 93631 MATCH x0ea0cc00/mask=xbfa0fc00
# CONSTRUCT x4ee0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG1 $f*@8 &=$f-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@8
# AUNIT --inst x4ee0cc00/mask=xffe0fc00 --rand dfp --status fail --comment "nofpround"
:fmls Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x19 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd infix TMPQ1 = Rn_VPR128.2D f* Rd_VPR128.2D on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] f* Rd_VPR128.2D[0,64];
TMPQ1[64,64] = Rn_VPR128.2D[64,64] f* Rd_VPR128.2D[64,64];
# simd infix Rd_VPR128.2D = Rd_VPR128.2D f- TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f- TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f- TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.126 FMLS (vector) page C7-1676 line 93631 MATCH x0ea0cc00/mask=xbfa0fc00
# CONSTRUCT x0ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f*@4 &=f-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4
# AUNIT --inst x0ea0cc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
:fmls Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x19 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix TMPD1 = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32];
TMPD1[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32];
Rd_VPR64.2S = Rd_VPR64.2S f- TMPD1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.126 FMLS (vector) page C7-1676 line 93631 MATCH x0ea0cc00/mask=xbfa0fc00
# CONSTRUCT x4ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4
# AUNIT --inst x4ea0cc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
:fmls Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x19 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] f* Rm_VPR128.4S[0,32];
TMPQ1[32,32] = Rn_VPR128.4S[32,32] f* Rm_VPR128.4S[32,32];
TMPQ1[64,32] = Rn_VPR128.4S[64,32] f* Rm_VPR128.4S[64,32];
TMPQ1[96,32] = Rn_VPR128.4S[96,32] f* Rm_VPR128.4S[96,32];
# simd infix Rd_VPR128.4S = Rd_VPR128.4S f- TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f- TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f- TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f- TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f- TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.126 FMLS (vector) page C7-1676 line 93631 MATCH x0ec00c00/mask=xbfe0fc00
# CONSTRUCT x0ec00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2
# AUNIT --inst x0ec00c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fmls Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b000011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
# simd infix TMPD1 = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 4
TMPD1[0,32] = Rn_VPR64.4H[0,32] f* Rm_VPR64.4H[0,32];
TMPD1[32,32] = Rn_VPR64.4H[32,32] f* Rm_VPR64.4H[32,32];
# simd infix Rd_VPR64.4H = Rd_VPR64.4H f- TMPD1 on lane size 4
Rd_VPR64.4H[0,32] = Rd_VPR64.4H[0,32] f- TMPD1[0,32];
Rd_VPR64.4H[32,32] = Rd_VPR64.4H[32,32] f- TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.126 FMLS (vector) page C7-1676 line 93631 MATCH x0ec00c00/mask=xbfe0fc00
# CONSTRUCT x4ec00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2
# AUNIT --inst x4ec00c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fmls Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b000011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 4
TMPQ1[0,32] = Rn_VPR128.8H[0,32] f* Rm_VPR128.8H[0,32];
TMPQ1[32,32] = Rn_VPR128.8H[32,32] f* Rm_VPR128.8H[32,32];
TMPQ1[64,32] = Rn_VPR128.8H[64,32] f* Rm_VPR128.8H[64,32];
TMPQ1[96,32] = Rn_VPR128.8H[96,32] f* Rm_VPR128.8H[96,32];
# simd infix Rd_VPR128.8H = Rd_VPR128.8H f- TMPQ1 on lane size 4
Rd_VPR128.8H[0,32] = Rd_VPR128.8H[0,32] f- TMPQ1[0,32];
Rd_VPR128.8H[32,32] = Rd_VPR128.8H[32,32] f- TMPQ1[32,32];
Rd_VPR128.8H[64,32] = Rd_VPR128.8H[64,32] f- TMPQ1[64,32];
Rd_VPR128.8H[96,32] = Rd_VPR128.8H[96,32] f- TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.127 FMLSL, FMLSL2 (by element) page C7-1678 line 93750 MATCH x0f804000/mask=xbfc0f400
# CONSTRUCT x0f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[0]:4 ARG3 $f* $float2float@2:8 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2
# AUNIT --inst x0f804000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 2S when Q = 0
:fmlsl Rd_VPR64.2S, vRn_VPR64^".2H", Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=0 & b_2329=0b0011111 & b_22=0 & b_1215=0b0100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd
{
TMPS1 = Rn_VPR64[0,32];
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2
TMPS2[0,16] = TMPS1[0,16] f* tmp2;
TMPS2[16,16] = TMPS1[16,16] f* tmp2;
# simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4)
TMPD3[0,32] = float2float(TMPS2[0,16]);
TMPD3[32,32] = float2float(TMPS2[16,16]);
# simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD3 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD3[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD3[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.127 FMLSL, FMLSL2 (by element) page C7-1678 line 93750 MATCH x0f804000/mask=xbfc0f400
# CONSTRUCT x4f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[0]:8 ARG3 $f* $float2float@2:16 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2
# AUNIT --inst x4f804000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 4S when Q = 1
:fmlsl Rd_VPR128.4S, vRn_VPR128^".4H", Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=0 & b_1215=0b0100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd
{
TMPD1 = Rn_VPR128[0,64];
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2
TMPD2[0,16] = TMPD1[0,16] f* tmp2;
TMPD2[16,16] = TMPD1[16,16] f* tmp2;
TMPD2[32,16] = TMPD1[32,16] f* tmp2;
TMPD2[48,16] = TMPD1[48,16] f* tmp2;
# simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)
TMPQ3[0,32] = float2float(TMPD2[0,16]);
TMPQ3[32,32] = float2float(TMPD2[16,16]);
TMPQ3[64,32] = float2float(TMPD2[32,16]);
TMPQ3[96,32] = float2float(TMPD2[48,16]);
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.127 FMLSL, FMLSL2 (by element) page C7-1678 line 93750 MATCH x2f80c000/mask=xbfc0f400
# CONSTRUCT x2f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:4 ARG3 $f* $float2float@2:8 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2
# AUNIT --inst x2f80c000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 2S when Q = 0
:fmlsl2 Rd_VPR64.2S, vRn_VPR64^".2H", Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=0 & b_2329=0b1011111 & b_22=0 & b_1215=0b1100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd
{
TMPS1 = Rn_VPR64[32,32];
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2
TMPS2[0,16] = TMPS1[0,16] f* tmp2;
TMPS2[16,16] = TMPS1[16,16] f* tmp2;
# simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4)
TMPD3[0,32] = float2float(TMPS2[0,16]);
TMPD3[32,32] = float2float(TMPS2[16,16]);
# simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD3 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD3[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD3[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.127 FMLSL, FMLSL2 (by element) page C7-1678 line 93750 MATCH x2f80c000/mask=xbfc0f400
# CONSTRUCT x6f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 ARG3 $f* $float2float@2:16 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2
# AUNIT --inst x6f80c000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 4S when Q = 1
:fmlsl2 Rd_VPR128.4S, vRn_VPR128^".4H", Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=1 & b_2329=0b1011111 & b_22=0 & b_1215=0b1100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd
{
TMPD1 = Rn_VPR128[64,64];
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2
TMPD2[0,16] = TMPD1[0,16] f* tmp2;
TMPD2[16,16] = TMPD1[16,16] f* tmp2;
TMPD2[32,16] = TMPD1[32,16] f* tmp2;
TMPD2[48,16] = TMPD1[48,16] f* tmp2;
# simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)
TMPQ3[0,32] = float2float(TMPD2[0,16]);
TMPQ3[32,32] = float2float(TMPD2[16,16]);
TMPQ3[64,32] = float2float(TMPD2[32,16]);
TMPQ3[96,32] = float2float(TMPD2[48,16]);
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.128 FMLSL, FMLSL2 (vector) page C7-1680 line 93882 MATCH x0ea0ec00/mask=xbfe0fc00
# CONSTRUCT x0ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[0]:4 ARG3[0]:4 $f*@2 $float2float@2:8 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2
# AUNIT --inst x0ea0ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 2S when Q = 0
:fmlsl Rd_VPR64.2S, vRn_VPR64^".2H", vRm_VPR64^".2H"
is b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR64 & Rm_VPR64 & Zd
{
TMPS1 = Rn_VPR64[0,32];
TMPS2 = Rm_VPR64[0,32];
# simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2
TMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16];
TMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16];
# simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4)
TMPD4[0,32] = float2float(TMPS3[0,16]);
TMPD4[32,32] = float2float(TMPS3[16,16]);
# simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD4 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD4[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD4[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.128 FMLSL, FMLSL2 (vector) page C7-1680 line 93882 MATCH x0ea0ec00/mask=xbfe0fc00
# CONSTRUCT x4ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[0]:8 ARG3[0]:8 $f*@2 $float2float@2:16 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2
# AUNIT --inst x4ea0ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 4S when Q = 1
:fmlsl Rd_VPR128.4S, vRn_VPR128^".4H", Rm_VPR64.4H
is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd
{
TMPD1 = Rn_VPR128[0,64];
TMPD2 = Rm_VPR64.4H[0,64];
# simd infix TMPD3 = TMPD1 f* TMPD2 on lane size 2
TMPD3[0,16] = TMPD1[0,16] f* TMPD2[0,16];
TMPD3[16,16] = TMPD1[16,16] f* TMPD2[16,16];
TMPD3[32,16] = TMPD1[32,16] f* TMPD2[32,16];
TMPD3[48,16] = TMPD1[48,16] f* TMPD2[48,16];
# simd resize TMPQ4 = float2float(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = float2float(TMPD3[0,16]);
TMPQ4[32,32] = float2float(TMPD3[16,16]);
TMPQ4[64,32] = float2float(TMPD3[32,16]);
TMPQ4[96,32] = float2float(TMPD3[48,16]);
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ4[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ4[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ4[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.128 FMLSL, FMLSL2 (vector) page C7-1680 line 93882 MATCH x2ea0cc00/mask=xbfe0fc00
# CONSTRUCT x2ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:4 ARG3[1]:4 $f*@2 $float2float@2:8 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2
# AUNIT --inst x2ea0cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 2S when Q = 0
:fmlsl2 Rd_VPR64.2S, vRn_VPR64^".2H", vRm_VPR128^".2H"
is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR128 & Rm_VPR128 & Zd
{
TMPS1 = Rn_VPR64[32,32];
TMPS2 = Rm_VPR128[32,32];
# simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2
TMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16];
TMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16];
# simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4)
TMPD4[0,32] = float2float(TMPS3[0,16]);
TMPD4[32,32] = float2float(TMPS3[16,16]);
# simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD4 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD4[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD4[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.128 FMLSL, FMLSL2 (vector) page C7-1680 line 93882 MATCH x2ea0cc00/mask=xbfe0fc00
# CONSTRUCT x6ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 ARG3 $f*@2 $float2float@2:16 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2
# AUNIT --inst x6ea0cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
# SIMD 4S when Q = 1
:fmlsl2 Rd_VPR128.4S, vRn_VPR128^".4H", Rm_VPR64.4H
is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd
{
TMPD1 = Rn_VPR128[64,64];
# simd infix TMPD2 = TMPD1 f* Rm_VPR64.4H on lane size 2
TMPD2[0,16] = TMPD1[0,16] f* Rm_VPR64.4H[0,16];
TMPD2[16,16] = TMPD1[16,16] f* Rm_VPR64.4H[16,16];
TMPD2[32,16] = TMPD1[32,16] f* Rm_VPR64.4H[32,16];
TMPD2[48,16] = TMPD1[48,16] f* Rm_VPR64.4H[48,16];
# simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)
TMPQ3[0,32] = float2float(TMPD2[0,16]);
TMPQ3[32,32] = float2float(TMPD2[16,16]);
TMPQ3[64,32] = float2float(TMPD2[32,16]);
TMPQ3[96,32] = float2float(TMPD2[48,16]);
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.129 FMOV (vector, immediate) page C7-1682 line 94007 MATCH x0f00f400/mask=x9ff8fc00
# C7.2.20 BIC (vector, immediate) page C7-1428 line 79003 MATCH x2f001400/mask=xbff81c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# CONSTRUCT x6f00f400/mask=xfff8fc00 MATCHED 4 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@8
# AUNIT --inst x6f00f400/mask=xfff8fc00 --rand dfp --status nopcodeop
:fmov Rd_VPR128.2D, Imm_neon_uimm8Shift
is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & cmode=0xf & b_1011=1 & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fmov(Imm_neon_uimm8Shift, 8:1);
}
# C7.2.129 FMOV (vector, immediate) page C7-1682 line 94007 MATCH x0f00f400/mask=x9ff8fc00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.212 ORR (vector, immediate) page C7-1880 line 105389 MATCH x0f001400/mask=xbff81c00
# CONSTRUCT x0f00f400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2:4 =NEON_fmov/1@4
# AUNIT --inst x0f00f400/mask=xfff8fc00 --rand dfp --status nopcodeop
:fmov Rd_VPR64.2S, Imm_neon_uimm8Shift
is b_3131=0 & q=0 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & cmode=0xf & b_1011=1 & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fmov(Imm_neon_uimm8Shift:4, 4:1);
}
# C7.2.129 FMOV (vector, immediate) page C7-1682 line 94007 MATCH x0f00f400/mask=x9ff8fc00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.212 ORR (vector, immediate) page C7-1880 line 105389 MATCH x0f001400/mask=xbff81c00
# CONSTRUCT x4f00f400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2:4 =NEON_fmov/1@4
# AUNIT --inst x4f00f400/mask=xfff8fc00 --rand sfp --status nopcodeop
:fmov Rd_VPR128.4S, Imm_neon_uimm8Shift
is b_3131=0 & q=1 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & cmode=0xf & b_1011=1 & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fmov(Imm_neon_uimm8Shift:4, 4:1);
}
# C7.2.129 FMOV (vector, immediate) page C7-1682 line 94007 MATCH x0f00fc00/mask=xbff8fc00
# C7.2.89 FCVTZS (vector, fixed-point) page C7-1595 line 88905 MATCH x0f00fc00/mask=xbf80fc00
# CONSTRUCT x0f00fc00/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 int2float:2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@2
# AUNIT --inst x0f00fc00/mask=xfff8fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 4H when Q = 0
:fmov Rd_VPR64.4H, Imm_neon_uimm8Shift
is b_31=0 & b_30=0 & b_1929=0b00111100000 & b_1015=0b111111 & Rd_VPR64.4H & Imm_neon_uimm8Shift & Zd
{
local tmp1:2 = int2float(Imm_neon_uimm8Shift);
# simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2)
Rd_VPR64.4H[0,16] = tmp1;
Rd_VPR64.4H[16,16] = tmp1;
Rd_VPR64.4H[32,16] = tmp1;
Rd_VPR64.4H[48,16] = tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.129 FMOV (vector, immediate) page C7-1682 line 94007 MATCH x0f00fc00/mask=xbff8fc00
# C7.2.89 FCVTZS (vector, fixed-point) page C7-1595 line 88905 MATCH x0f00fc00/mask=xbf80fc00
# CONSTRUCT x4f00fc00/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 int2float:2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@2
# AUNIT --inst x4f00fc00/mask=xfff8fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant SIMD 8H when Q = 1
:fmov Rd_VPR128.8H, Imm_neon_uimm8Shift
is b_31=0 & b_30=1 & b_1929=0b00111100000 & b_1015=0b111111 & Rd_VPR128.8H & Imm_neon_uimm8Shift & Zd
{
local tmp1:2 = int2float(Imm_neon_uimm8Shift);
# simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2)
Rd_VPR128.8H[0,16] = tmp1;
Rd_VPR128.8H[16,16] = tmp1;
Rd_VPR128.8H[32,16] = tmp1;
Rd_VPR128.8H[48,16] = tmp1;
Rd_VPR128.8H[64,16] = tmp1;
Rd_VPR128.8H[80,16] = tmp1;
Rd_VPR128.8H[96,16] = tmp1;
Rd_VPR128.8H[112,16] = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.130 FMOV (register) page C7-1684 line 94119 MATCH x1e204000/mask=xff3ffc00
# CONSTRUCT x1ee04000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x1ee04000/mask=xfffffc00 --rand hfp --status noqemu
# Half-precision variant when type == 11 arg1=Rd_FPR16 arg2=Rn_FPR16
:fmov Rd_FPR16, Rn_FPR16
is b_2431=0b00011110 & b_2223=0b11 & b_1021=0b100000010000 & Rd_FPR16 & Rn_FPR16 & Rd_FPR64 & Zd
{
Rd_FPR16 = Rn_FPR16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.130 FMOV (register) page C7-1684 line 94119 MATCH x1e204000/mask=xff3ffc00
# CONSTRUCT x1e204000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x1e204000/mask=xfffffc00 --rand sfp --status pass
# Single-precision variant when type == 00 arg1=Rd_FPR32 arg2=Rn_FPR32
:fmov Rd_FPR32, Rn_FPR32
is b_2431=0b00011110 & b_2223=0b00 & b_1021=0b100000010000 & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = Rn_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.130 FMOV (register) page C7-1684 line 94119 MATCH x1e204000/mask=xff3ffc00
# CONSTRUCT x1e604000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x1e604000/mask=xfffffc00 --rand dfp --status pass
# Double-precision variant when type == 01 arg1=Rd_FPR64 arg2=Rn_FPR64
:fmov Rd_FPR64, Rn_FPR64
is b_2431=0b00011110 & b_2223=0b01 & b_1021=0b100000010000 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = Rn_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x1e660000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x1e660000/mask=xfffffc00 --rand dfp --status noqemu --comment "nofpround"
# UNDOCUMENTED Double-precision to 32-bit variant when sf == 0 && type == 01 && rmode == 00 && opcode = 110 arg1=Rd_GPR32 arg2=Rn_FPR64
:fmov Rd_GPR32, Rn_FPR64
is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR32 & Rn_FPR64 & Rd_GPR64
{
Rd_GPR32 = float2float(Rn_FPR64);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x9e260000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x9e260000/mask=xfffffc00 --rand sfp --status noqemu --comment "nofpround"
# UNDOCUMENTED Single-precision to 64-bit variant when sf == 1 && type == 00 && rmode == 00 && opcode = 110 arg1=Rd_GPR64 arg2=Rn_FPR32
:fmov Rd_GPR64, Rn_FPR32
is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & Rn_FPR32
{
Rd_GPR64 = float2float(Rn_FPR32);
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x1e670000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x1e670000/mask=xfffffc00 --rand dfp --status noqemu --comment "nofpround"
# UNDOCUMENTED 32-bit to Double-precision variant when sf == 0 && type == 01 && rmode == 00 && opcode = 111 arg1=Rd_FPR64 arg2=Rn_GPR32
:fmov Rd_FPR64, Rn_GPR32
is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR64 & Rn_GPR32 & Zd
{
Rd_FPR64 = float2float(Rn_GPR32);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x9e270000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x9e270000/mask=xfffffc00 --rand sfp --status noqemu --comment "nofpround"
# UNDOCUMENTED 64-bit to single-precision variant when sf == 1 && type == 00 && rmode == 00 && opcode = 111 arg1=Rd_FPR32 arg2=Rn_GPR64
:fmov Rd_FPR32, Rn_GPR64
is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR32 & Rn_GPR64 & Zd
{
Rd_FPR32 = float2float(Rn_GPR64);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x1ee60000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x1ee60000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision to 32-bit variant when sf == 0 && type == 11 && rmode == 00 && opcode == 110 arg1=Rd_GPR32 arg2=Rn_FPR16
:fmov Rd_GPR32, Rn_FPR16
is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR32 & Rn_FPR16 & Rd_GPR64
{
Rd_GPR32 = float2float(Rn_FPR16);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x9ee60000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x9ee60000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision to 64-bit variant when sf == 1 && type == 11 && rmode == 00 && opcode == 110 arg1=Rd_GPR64 arg2=Rn_FPR16
:fmov Rd_GPR64, Rn_FPR16
is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & Rn_FPR16
{
Rd_GPR64 = float2float(Rn_FPR16);
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x1ee70000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x1ee70000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# 32-bit to half-precision variant when sf == 0 && type == 11 && rmode == 00 && opcode == 111 arg1=Rd_FPR16 arg2=Rn_GPR32
:fmov Rd_FPR16, Rn_GPR32
is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR16 & Rn_GPR32 & Zd
{
Rd_FPR16 = float2float(Rn_GPR32);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x1e270000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x1e270000/mask=xfffffc00 --rand sfp --status pass --comment "nofpround"
# 32-bit to single-precision variant when sf == 0 && type == 00 && rmode == 00 && opcode == 111 arg1=Rd_FPR32 arg2=Rn_GPR32
:fmov Rd_FPR32, Rn_GPR32
is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR32 & Rn_GPR32 & Zd
{
Rd_FPR32 = Rn_GPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x1e260000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x1e260000/mask=xfffffc00 --rand sfp --status pass --comment "nofpround"
# Single-precision to 32-bit variant when sf == 0 && type == 00 && rmode == 00 && opcode == 110 arg1=Rd_GPR32 arg2=Rn_FPR32
:fmov Rd_GPR32, Rn_FPR32
is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR32 & Rn_FPR32 & Rd_GPR64
{
Rd_GPR32 = Rn_FPR32;
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x9ee70000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =float2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x9ee70000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# 64-bit to half-precision variant when sf == 1 && type == 11 && rmode == 00 && opcode == 111 arg1=Rd_FPR16 arg2=Rn_GPR64
:fmov Rd_FPR16, Rn_GPR64
is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR16 & Rn_GPR64 & Zd
{
Rd_FPR16 = float2float(Rn_GPR64);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x9e670000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x9e670000/mask=xfffffc00 --rand dfp --status pass --comment "nofpround"
# 64-bit to double-precision variant when sf == 1 && type == 01 && rmode == 00 && opcode == 111 arg1=Rd_FPR64 arg2=Rn_GPR64
:fmov Rd_FPR64, Rn_GPR64
is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR64 & Rn_GPR64 & Zd
{
Rd_FPR64 = Rn_GPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x9eaf0000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 1:1 &=$copy@8
# SMACRO(pseudo) ARG1 ARG2 &=NEON_fmov/2
# AUNIT --inst x9eaf0000/mask=xfffffc00 --rand dfp --status pass --comment "nofpround"
# 64-bit to top half of 128-bit variant when sf == 1 && type == 10 && rmode == 01 && opcode == 111 arg1=vRd_VPR128^".D[1]" arg2=Rn_GPR64
:fmov vRd_VPR128^".D[1]", Rn_GPR64
is b_31=1 & b_2430=0b0011110 & b_2223=0b10 & b_21=1 & b_1920=0b01 & b_1618=0b111 & b_1015=0b000000 & vRd_VPR128 & Rd_VPR128 & Rn_GPR64 & Zd
{
# simd copy Rd_VPR128 element 1:1 = Rn_GPR64 (lane size 8)
Rd_VPR128[64,64] = Rn_GPR64;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x9e660000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x9e660000/mask=xfffffc00 --rand dfp --status pass --comment "nofpround"
# Double-precision to 64-bit variant when sf == 1 && type == 01 && rmode == 00 && opcode == 110 arg1=Rd_GPR64 arg2=Rn_FPR64
:fmov Rd_GPR64, Rn_FPR64
is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & Rn_FPR64
{
Rd_GPR64 = Rn_FPR64;
}
# C7.2.131 FMOV (general) page C7-1686 line 94209 MATCH x1e260000/mask=x7f36fc00
# CONSTRUCT x9eae0000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 =ARG2[1]:8
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@8
# AUNIT --inst x9eae0000/mask=xfffffc00 --rand dfp --status pass --comment "nofpround"
# Top half of 128-bit to 64-bit variant when sf == 1 && type == 10 && rmode == 01 && opcode == 110 arg1=Rd_GPR64 arg2=vRd_VPR128^".D[1]"
:fmov Rd_GPR64, vRn_VPR128^".D[1]"
is b_31=1 & b_2430=0b0011110 & b_2223=0b10 & b_21=1 & b_1920=0b01 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & vRn_VPR128 & Rn_VPR128
{
Rd_GPR64 = Rn_VPR128[64,64];
}
# C7.2.132 FMOV (scalar, immediate) page C7-1689 line 94427 MATCH x1e201000/mask=xff201fe0
# CONSTRUCT x1e601001/mask=xffe01fe1 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x1e601001/mask=xffe01fe1 --rand dfp --status pass
:fmov Rd_FPR64, Imm8_fmov64_operand
is ImmS_ImmR_TestSet=1 & m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Imm8_fmov64_operand & b_1012=4 & imm5=0x0 & Rd_FPR64 & Zd
{
Rd_FPR64 = Imm8_fmov64_operand:8;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.132 FMOV (scalar, immediate) page C7-1689 line 94427 MATCH x1e201000/mask=xff201fe0
# CONSTRUCT x1e201000/mask=xffe01fe0 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x1e201000/mask=xffe01fe0 --rand sfp --status pass
:fmov Rd_FPR32, Imm8_fmov32_operand
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Imm8_fmov32_operand & b_1012=4 & imm5=0x0 & Rd_FPR32 & Zd
{
Rd_FPR32 = Imm8_fmov32_operand:4;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.132 FMOV (scalar, immediate) page C7-1689 line 94427 MATCH x1e201000/mask=xff201fe0
# CONSTRUCT x1ee01000/mask=xffe01fe0 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
# AUNIT --inst x1ee01000/mask=xffe01fe0 --rand hfp --status noqemu
:fmov Rd_FPR16, Imm8_fmov16_operand
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Imm8_fmov16_operand & b_1012=4 & imm5=0x0 & Rd_FPR16 & Zd
{
Rd_FPR16 = Imm8_fmov16_operand:2;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.133 FMSUB page C7-1691 line 94515 MATCH x1f008000/mask=xff208000
# CONSTRUCT x1f408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmsub/3
# AUNIT --inst x1f408000/mask=xffe08000 --rand dfp --status nopcodeop --comment "nofpround"
:fmsub Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=1 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_fmsub(Rn_FPR64, Rm_FPR64, Ra_FPR64);
}
# C7.2.133 FMSUB page C7-1691 line 94515 MATCH x1f008000/mask=xff208000
# CONSTRUCT x1f008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmsub/3
# AUNIT --inst x1f008000/mask=xffe08000 --rand sfp --status nopcodeop --comment "nofpround"
:fmsub Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=1 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fmsub(Rn_FPR32, Rm_FPR32, Ra_FPR32);
}
# C7.2.133 FMSUB page C7-1691 line 94515 MATCH x1f008000/mask=xff208000
# CONSTRUCT x1fc08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmsub/3
# AUNIT --inst x1fc08000/mask=xffe08000 --rand hfp --status noqemu --comment "nofpround"
:fmsub Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=0 & Rm_FPR16 & b_15=1 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_fmsub(Rn_FPR16, Rm_FPR16, Ra_FPR16);
}
# C7.2.134 FMUL (by element) page C7-1693 line 94639 MATCH x5f009000/mask=xffc0f400
# CONSTRUCT x5f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2
# AUNIT --inst x5f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
# FMUL (by element) Scalar, half-precision
:fmul Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
is b_2231=0b0101111100 & b_1215=0b1001 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
Rd_FPR16 = Rn_FPR16 f* tmp1;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.134 FMUL (by element) page C7-1693 line 94639 MATCH x5f809000/mask=xff80f400
# CONSTRUCT x5f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4
# AUNIT --inst x5f809000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround"
# FMUL (by element) Scalar, single-precision and double-precision sz=0
:fmul Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex
is b_2331=0b010111111 & b_22=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.S & vIndex & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
Rd_FPR32 = Rn_FPR32 f* tmp1;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.134 FMUL (by element) page C7-1693 line 94639 MATCH x5f809000/mask=xff80f400
# CONSTRUCT x5fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@8
# AUNIT --inst x5fc09000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
# FMUL (by element) Scalar, single-precision and double-precision sz=1
:fmul Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex
is b_2331=0b010111111 & b_22=1 & b_21=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.D & vIndex & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Zd
{
# simd element Re_VPR128.D[vIndex] lane size 8
local tmp1:8 = Re_VPR128.D.vIndex;
Rd_FPR64 = Rn_FPR64 f* tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.134 FMUL (by element) page C7-1693 line 94639 MATCH x0f009000/mask=xbfc0f400
# CONSTRUCT x0f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2
# AUNIT --inst x0f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
# FMUL (by element) Vector, half-precision, Q=0
:fmul Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_31=0 &b_30=0 & b_2229=0b00111100 & b_1215=0b1001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix Rd_VPR64.4H = Rn_VPR64.4H f* tmp1 on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* tmp1;
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* tmp1;
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* tmp1;
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.134 FMUL (by element) page C7-1693 line 94639 MATCH x0f009000/mask=xbfc0f400
# CONSTRUCT x4f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2
# AUNIT --inst x4f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
# FMUL (by element) Vector, half-precision, Q=1
:fmul Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_31=0 &b_30=1 & b_2229=0b00111100 & b_1215=0b1001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix Rd_VPR128.8H = Rn_VPR128.8H f* tmp1 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* tmp1;
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* tmp1;
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* tmp1;
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* tmp1;
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* tmp1;
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* tmp1;
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* tmp1;
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.134 FMUL (by element) page C7-1693 line 94639 MATCH x0f809000/mask=xbf80f400
# CONSTRUCT x4fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@8
# AUNIT --inst x4fc09000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
# Vector, single-precision and double-precision Q=1 and sz:L=10
:fmul Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex
is b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=1 & b_21=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd element Re_VPR128.D[vIndex] lane size 8
local tmp1:8 = Re_VPR128.D.vIndex;
# simd infix Rd_VPR128.2D = Rn_VPR128.2D f* tmp1 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f* tmp1;
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f* tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.134 FMUL (by element) page C7-1693 line 94639 MATCH x0f809000/mask=xbf80f400
# CONSTRUCT x0f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4
# AUNIT --inst x0f809000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround"
# Vector, single-precision and double-precision Q=0 and sz:L=0x
:fmul Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_31=0 & b_30=0 & b_2329=0b0011111 & b_22=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix Rd_VPR64.2S = Rn_VPR64.2S f* tmp1 on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f* tmp1;
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f* tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.134 FMUL (by element) page C7-1693 line 94639 MATCH x0f809000/mask=xbf80f400
# CONSTRUCT x4f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4
# AUNIT --inst x4f809000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround"
# Vector, single-precision and double-precision Q=1 and sz:L=0x
:fmul Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix Rd_VPR128.4S = Rn_VPR128.4S f* tmp1 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f* tmp1;
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f* tmp1;
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f* tmp1;
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f* tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.135 FMUL (vector) page C7-1697 line 94875 MATCH x2e20dc00/mask=xbfa0fc00
# CONSTRUCT x6e60dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@8
# AUNIT --inst x6e60dc00/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
:fmul Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1b & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd infix Rd_VPR128.2D = Rn_VPR128.2D f* Rm_VPR128.2D on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f* Rm_VPR128.2D[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f* Rm_VPR128.2D[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.135 FMUL (vector) page C7-1697 line 94875 MATCH x2e20dc00/mask=xbfa0fc00
# CONSTRUCT x2e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4
# AUNIT --inst x2e20dc00/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
:fmul Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1b & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix Rd_VPR64.2S = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32];
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.135 FMUL (vector) page C7-1697 line 94875 MATCH x2e20dc00/mask=xbfa0fc00
# CONSTRUCT x6e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4
# AUNIT --inst x6e20dc00/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
:fmul Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1b & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd infix Rd_VPR128.4S = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f* Rm_VPR128.4S[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f* Rm_VPR128.4S[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f* Rm_VPR128.4S[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f* Rm_VPR128.4S[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.135 FMUL (vector) page C7-1697 line 94875 MATCH x2e401c00/mask=xbfe0fc00
# CONSTRUCT x2e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2
# AUNIT --inst x2e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant when Q=0 suf=VPR64.4H
:fmul Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b000111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
# simd infix Rd_VPR64.4H = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* Rm_VPR64.4H[0,16];
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* Rm_VPR64.4H[16,16];
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* Rm_VPR64.4H[32,16];
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* Rm_VPR64.4H[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.135 FMUL (vector) page C7-1697 line 94875 MATCH x2e401c00/mask=xbfe0fc00
# CONSTRUCT x6e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2
# AUNIT --inst x6e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant when Q=1 suf=VPR128.8H
:fmul Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b000111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
# simd infix Rd_VPR128.8H = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* Rm_VPR128.8H[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* Rm_VPR128.8H[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* Rm_VPR128.8H[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* Rm_VPR128.8H[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* Rm_VPR128.8H[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* Rm_VPR128.8H[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* Rm_VPR128.8H[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* Rm_VPR128.8H[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.136 FMUL (scalar) page C7-1699 line 94990 MATCH x1e200800/mask=xff20fc00
# CONSTRUCT x1e600800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2
# AUNIT --inst x1e600800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
:fmul Rd_FPR64, Rn_FPR64, Rm_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x0 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = Rn_FPR64 f* Rm_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.136 FMUL (scalar) page C7-1699 line 94990 MATCH x1e200800/mask=xff20fc00
# CONSTRUCT x1e200800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2
# AUNIT --inst x1e200800/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
:fmul Rd_FPR32, Rn_FPR32, Rm_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x0 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = Rn_FPR32 f* Rm_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.136 FMUL (scalar) page C7-1699 line 94990 MATCH x1e200800/mask=xff20fc00
# CONSTRUCT x1ee00800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2
# AUNIT --inst x1ee00800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
:fmul Rd_FPR16, Rn_FPR16, Rm_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x0 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = Rn_FPR16 f* Rm_FPR16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.137 FMULX (by element) page C7-1701 line 95093 MATCH x2f809000/mask=xbf80f400
# CONSTRUCT x6fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@8
# AUNIT --inst x6fc09000/mask=xffe0f400 --rand dfp --status nopcodeop --comment "nofpround"
:fmulx Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex
is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=3 & b_2121=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & b_1215=0x9 & b_1010=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
local tmp1:8 = SIMD_PIECE(Re_VPR128.D, vIndex:1);
Rd_VPR128.2D = NEON_fmulx(Rn_VPR128.2D, tmp1, 8:1);
}
# C7.2.137 FMULX (by element) page C7-1701 line 95093 MATCH x2f809000/mask=xbf80f400
# CONSTRUCT x2f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4
# AUNIT --inst x2f809000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround"
:fmulx Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x9 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix Rd_VPR64.2S = Rn_VPR64.2S f* tmp1 on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f* tmp1;
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f* tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.137 FMULX (by element) page C7-1701 line 95093 MATCH x2f809000/mask=xbf80f400
# CONSTRUCT x6f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4
# AUNIT --inst x6f809000/mask=xffc0f400 --rand sfp --status nopcodeop --comment "nofpround"
:fmulx Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x9 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
Rd_VPR128.4S = NEON_fmulx(Rn_VPR128.4S, tmp1, 4:1);
}
# C7.2.137 FMULX (by element) page C7-1701 line 95093 MATCH x7f009000/mask=xffc0f400
# CONSTRUCT x7f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2
# AUNIT --inst x7f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
# Scalar, half-precision variant
:fmulx Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
is b_2231=0b0111111100 & b_1215=0b1001 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
Rd_FPR16 = Rn_FPR16 f* tmp1;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.137 FMULX (by element) page C7-1701 line 95093 MATCH x7f809000/mask=xff80f400
# CONSTRUCT x7f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4
# AUNIT --inst x7f809000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround"
# Scalar, single-precision and double-precision variant when sz=0 Ts=S V=32
:fmulx Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex
is b_2331=0b011111111 & b_22=0 & b_1215=0b1001 & b_10=0 & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
Rd_FPR32 = Rn_FPR32 f* tmp1;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.137 FMULX (by element) page C7-1701 line 95093 MATCH x7f809000/mask=xff80f400
# CONSTRUCT x7fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@8
# AUNIT --inst x7fc09000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
# Scalar, single-precision and double-precision variant when sz=1 Ts=D V=64
:fmulx Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex
is b_2331=0b011111111 & b_22=1 & b_21=0 & b_1215=0b1001 & b_10=0 & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Re_VPR128.D & vIndex & Zd
{
# simd element Re_VPR128.D[vIndex] lane size 8
local tmp1:8 = Re_VPR128.D.vIndex;
Rd_FPR64 = Rn_FPR64 f* tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.137 FMULX (by element) page C7-1701 line 95093 MATCH x2f009000/mask=xbfc0f400
# CONSTRUCT x2f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2
# AUNIT --inst x2f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
# Vector, half-precision variant when Q = 0 suf=64.4H
:fmulx Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=0 & b_2229=0b10111100 & b_1215=0b1001 & b_10=0 & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix Rd_VPR64.4H = Rn_VPR64.4H f* tmp1 on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* tmp1;
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* tmp1;
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* tmp1;
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.137 FMULX (by element) page C7-1701 line 95093 MATCH x2f009000/mask=xbfc0f400
# CONSTRUCT x6f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2
# AUNIT --inst x6f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
# Vector, half-precision variant when Q = 1 suf=128.8H
:fmulx Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=1 & b_2229=0b10111100 & b_1215=0b1001 & b_10=0 & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix Rd_VPR128.8H = Rn_VPR128.8H f* tmp1 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* tmp1;
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* tmp1;
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* tmp1;
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* tmp1;
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* tmp1;
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* tmp1;
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* tmp1;
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.138 FMULX page C7-1705 line 95331 MATCH x5e20dc00/mask=xffa0fc00
# CONSTRUCT x5e60dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2
# AUNIT --inst x5e60dc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmulx Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=3 & Rm_FPR64 & b_1115=0x1b & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_fmulx(Rn_FPR64, Rm_FPR64);
}
# C7.2.138 FMULX page C7-1705 line 95331 MATCH x5e20dc00/mask=xffa0fc00
# CONSTRUCT x5e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2
# AUNIT --inst x5e20dc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmulx Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=1 & Rm_FPR32 & b_1115=0x1b & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fmulx(Rn_FPR32, Rm_FPR32);
}
# C7.2.138 FMULX page C7-1705 line 95331 MATCH x0e20dc00/mask=xbfa0fc00
# CONSTRUCT x4e60dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@8
# AUNIT --inst x4e60dc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:fmulx Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1b & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fmulx(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.138 FMULX page C7-1705 line 95331 MATCH x0e20dc00/mask=xbfa0fc00
# CONSTRUCT x0e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4
# AUNIT --inst x0e20dc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmulx Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1b & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fmulx(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.138 FMULX page C7-1705 line 95331 MATCH x0e20dc00/mask=xbfa0fc00
# CONSTRUCT x4e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4
# AUNIT --inst x4e20dc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:fmulx Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1b & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fmulx(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.138 FMULX page C7-1705 line 95331 MATCH x5e401c00/mask=xffe0fc00
# CONSTRUCT x5e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2
# AUNIT --inst x5e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Scalar half precision variant
:fmulx Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_2131=0b01011110010 & b_1015=0b000111 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
{
Rd_FPR16 = Rn_FPR16 f* Rm_FPR16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.138 FMULX page C7-1705 line 95331 MATCH x0e401c00/mask=xbfe0fc00
# CONSTRUCT x0e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2
# AUNIT --inst x0e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant when Q=0 suf=64.4H
:fmulx Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
# simd infix Rd_VPR64.4H = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* Rm_VPR64.4H[0,16];
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* Rm_VPR64.4H[16,16];
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* Rm_VPR64.4H[32,16];
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* Rm_VPR64.4H[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.138 FMULX page C7-1705 line 95331 MATCH x0e401c00/mask=xbfe0fc00
# CONSTRUCT x4e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f*@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2
# AUNIT --inst x4e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant when Q=1 suf=128.8H
:fmulx Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
# simd infix Rd_VPR128.8H = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* Rm_VPR128.8H[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* Rm_VPR128.8H[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* Rm_VPR128.8H[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* Rm_VPR128.8H[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* Rm_VPR128.8H[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* Rm_VPR128.8H[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* Rm_VPR128.8H[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* Rm_VPR128.8H[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.139 FNEG (vector) page C7-1708 line 95520 MATCH x2ea0f800/mask=xbfbffc00
# CONSTRUCT x6ee0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$fneg@8
# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@8
# AUNIT --inst x6ee0f800/mask=xfffffc00 --rand dfp --status pass
:fneg Rd_VPR128.2D, Rn_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd unary Rd_VPR128.2D = f-(Rn_VPR128.2D) on lane size 8
Rd_VPR128.2D[0,64] = f-(Rn_VPR128.2D[0,64]);
Rd_VPR128.2D[64,64] = f-(Rn_VPR128.2D[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.139 FNEG (vector) page C7-1708 line 95520 MATCH x2ea0f800/mask=xbfbffc00
# CONSTRUCT x2ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$fneg@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@4
# AUNIT --inst x2ea0f800/mask=xfffffc00 --rand sfp --status pass
:fneg Rd_VPR64.2S, Rn_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd unary Rd_VPR64.2S = f-(Rn_VPR64.2S) on lane size 4
Rd_VPR64.2S[0,32] = f-(Rn_VPR64.2S[0,32]);
Rd_VPR64.2S[32,32] = f-(Rn_VPR64.2S[32,32]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.139 FNEG (vector) page C7-1708 line 95520 MATCH x2ea0f800/mask=xbfbffc00
# CONSTRUCT x6ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$fneg@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@4
# AUNIT --inst x6ea0f800/mask=xfffffc00 --rand sfp --status pass
:fneg Rd_VPR128.4S, Rn_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd unary Rd_VPR128.4S = f-(Rn_VPR128.4S) on lane size 4
Rd_VPR128.4S[0,32] = f-(Rn_VPR128.4S[0,32]);
Rd_VPR128.4S[32,32] = f-(Rn_VPR128.4S[32,32]);
Rd_VPR128.4S[64,32] = f-(Rn_VPR128.4S[64,32]);
Rd_VPR128.4S[96,32] = f-(Rn_VPR128.4S[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.139 FNEG (vector) page C7-1708 line 95520 MATCH x2ef8f800/mask=xbffffc00
# CONSTRUCT x2ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$fneg@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@2
# AUNIT --inst x2ef8f800/mask=xfffffc00 --rand hfp --status noqemu
# Half-precision variant when Q=0 suf=64.4H
:fneg Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_1029=0b10111011111000111110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
# simd unary Rd_VPR64.4H = f-(Rn_VPR64.4H) on lane size 2
Rd_VPR64.4H[0,16] = f-(Rn_VPR64.4H[0,16]);
Rd_VPR64.4H[16,16] = f-(Rn_VPR64.4H[16,16]);
Rd_VPR64.4H[32,16] = f-(Rn_VPR64.4H[32,16]);
Rd_VPR64.4H[48,16] = f-(Rn_VPR64.4H[48,16]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.139 FNEG (vector) page C7-1708 line 95520 MATCH x2ef8f800/mask=xbffffc00
# CONSTRUCT x6ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$fneg@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@2
# AUNIT --inst x6ef8f800/mask=xfffffc00 --rand hfp --status noqemu
# Half-precision variant when Q=1 suf=128.8H
:fneg Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_1029=0b10111011111000111110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
# simd unary Rd_VPR128.8H = f-(Rn_VPR128.8H) on lane size 2
Rd_VPR128.8H[0,16] = f-(Rn_VPR128.8H[0,16]);
Rd_VPR128.8H[16,16] = f-(Rn_VPR128.8H[16,16]);
Rd_VPR128.8H[32,16] = f-(Rn_VPR128.8H[32,16]);
Rd_VPR128.8H[48,16] = f-(Rn_VPR128.8H[48,16]);
Rd_VPR128.8H[64,16] = f-(Rn_VPR128.8H[64,16]);
Rd_VPR128.8H[80,16] = f-(Rn_VPR128.8H[80,16]);
Rd_VPR128.8H[96,16] = f-(Rn_VPR128.8H[96,16]);
Rd_VPR128.8H[112,16] = f-(Rn_VPR128.8H[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.140 FNEG (scalar) page C7-1710 line 95628 MATCH x1e214000/mask=xff3ffc00
# CONSTRUCT x1e614000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =fneg
# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1
# AUNIT --inst x1e614000/mask=xfffffc00 --rand dfp --status pass
:fneg Rd_FPR64, Rn_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x2 & b_1014=0x10 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = f- Rn_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.140 FNEG (scalar) page C7-1710 line 95628 MATCH x1e214000/mask=xff3ffc00
# CONSTRUCT x1e214000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =fneg
# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1
# AUNIT --inst x1e214000/mask=xfffffc00 --rand sfp --status pass
:fneg Rd_FPR32, Rn_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x2 & b_1014=0x10 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = f- Rn_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.140 FNEG (scalar) page C7-1710 line 95628 MATCH x1e214000/mask=xff3ffc00
# CONSTRUCT x1ee14000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =fneg
# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1
# AUNIT --inst x1ee14000/mask=xfffffc00 --rand hfp --status noqemu
:fneg Rd_FPR16, Rn_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x2 & b_1014=0x10 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = f- Rn_FPR16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.141 FNMADD page C7-1712 line 95720 MATCH x1f200000/mask=xff208000
# CONSTRUCT x1f600000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 fneg =NEON_fnmadd/3
# AUNIT --inst x1f600000/mask=xffe08000 --rand dfp --status nopcodeop --comment "nofpround"
:fnmadd Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=1 & Rm_FPR64 & b_15=0 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd
{
local tmp1:8 = f- Ra_FPR64;
Rd_FPR64 = NEON_fnmadd(Rn_FPR64, Rm_FPR64, tmp1);
}
# C7.2.141 FNMADD page C7-1712 line 95720 MATCH x1f200000/mask=xff208000
# CONSTRUCT x1f200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 fneg =NEON_fnmadd/3
# AUNIT --inst x1f200000/mask=xffe08000 --rand sfp --status nopcodeop --comment "nofpround"
:fnmadd Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=1 & Rm_FPR32 & b_15=0 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd
{
local tmp1:4 = f- Ra_FPR32;
Rd_FPR32 = NEON_fnmadd(Rn_FPR32, Rm_FPR32, tmp1);
}
# C7.2.141 FNMADD page C7-1712 line 95720 MATCH x1f200000/mask=xff208000
# CONSTRUCT x1fe00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 fneg =NEON_fnmadd/3
# AUNIT --inst x1fe00000/mask=xffe08000 --rand hfp --status noqemu --comment "nofpround"
:fnmadd Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=1 & Rm_FPR16 & b_15=0 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd
{
local tmp1:2 = f- Ra_FPR16;
Rd_FPR16 = NEON_fnmadd(Rn_FPR16, Rm_FPR16, tmp1);
}
# C7.2.142 FNMSUB page C7-1714 line 95845 MATCH x1f208000/mask=xff208000
# CONSTRUCT x1f608000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fnmsub/3
# AUNIT --inst x1f608000/mask=xffe08000 --rand dfp --status nopcodeop --comment "nofpround"
:fnmsub Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=1 & Rm_FPR64 & b_15=1 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_fnmsub(Rn_FPR64, Rm_FPR64, Ra_FPR64);
}
# C7.2.142 FNMSUB page C7-1714 line 95845 MATCH x1f208000/mask=xff208000
# CONSTRUCT x1f208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fnmsub/3
# AUNIT --inst x1f208000/mask=xffe08000 --rand sfp --status nopcodeop --comment "nofpround"
:fnmsub Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=1 & Rm_FPR32 & b_15=1 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_fnmsub(Rn_FPR32, Rm_FPR32, Ra_FPR32);
}
# C7.2.142 FNMSUB page C7-1714 line 95845 MATCH x1f208000/mask=xff208000
# CONSTRUCT x1fe08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fnmsub/3
# AUNIT --inst x1fe08000/mask=xffe08000 --rand hfp --status noqemu --comment "nofpround"
:fnmsub Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=1 & Rm_FPR16 & b_15=1 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_fnmsub(Rn_FPR16, Rm_FPR16, Ra_FPR16);
}
# C7.2.143 FNMUL (scalar) page C7-1716 line 95969 MATCH x1e208800/mask=xff20fc00
# CONSTRUCT x1e608800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f* =fneg
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fnmul/2
# AUNIT --inst x1e608800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
:fnmul Rd_FPR64, Rn_FPR64, Rm_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x8 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
{
local tmp1:8 = Rn_FPR64 f* Rm_FPR64;
Rd_FPR64 = f- tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.143 FNMUL (scalar) page C7-1716 line 95969 MATCH x1e208800/mask=xff20fc00
# CONSTRUCT x1e208800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f* =fneg
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fnmul/2
# AUNIT --inst x1e208800/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
:fnmul Rd_FPR32, Rn_FPR32, Rm_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x8 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
{
local tmp1:4 = Rn_FPR32 f* Rm_FPR32;
Rd_FPR32 = f- tmp1;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.143 FNMUL (scalar) page C7-1716 line 95969 MATCH x1e208800/mask=xff20fc00
# CONSTRUCT x1ee08800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 f* =fneg
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fnmul/2
# AUNIT --inst x1ee08800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
:fnmul Rd_FPR16, Rn_FPR16, Rm_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x8 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
{
local tmp1:2 = Rn_FPR16 f* Rm_FPR16;
Rd_FPR16 = f- tmp1;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.144 FRECPE page C7-1718 line 96074 MATCH x0ea1d800/mask=xbfbffc00
# CONSTRUCT x4ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@8
# AUNIT --inst x4ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
:frecpe Rd_VPR128.2D, Rn_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=1 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_frecpe(Rn_VPR128.2D, 8:1);
}
# C7.2.144 FRECPE page C7-1718 line 96074 MATCH x0ea1d800/mask=xbfbffc00
# CONSTRUCT x0ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@4
# AUNIT --inst x0ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
:frecpe Rd_VPR64.2S, Rn_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & size_high=1 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_frecpe(Rn_VPR64.2S, 4:1);
}
# C7.2.144 FRECPE page C7-1718 line 96074 MATCH x0ea1d800/mask=xbfbffc00
# CONSTRUCT x4ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@4
# AUNIT --inst x4ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
:frecpe Rd_VPR128.4S, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=1 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_frecpe(Rn_VPR128.4S, 4:1);
}
# C7.2.144 FRECPE page C7-1718 line 96074 MATCH x5ea1d800/mask=xffbffc00
# CONSTRUCT x5ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1
# AUNIT --inst x5ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
:frecpe Rd_FPR64, Rn_FPR64
is b_3031=1 & u=0 & b_2428=0x1e & size_high=1 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_frecpe(Rn_FPR64);
}
# C7.2.144 FRECPE page C7-1718 line 96074 MATCH x5ea1d800/mask=xffbffc00
# CONSTRUCT x5ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1
# AUNIT --inst x5ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
:frecpe Rd_FPR32, Rn_FPR32
is b_3031=1 & u=0 & b_2428=0x1e & size_high=1 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_frecpe(Rn_FPR32);
}
# C7.2.144 FRECPE page C7-1718 line 96074 MATCH x5ef9d800/mask=xfffffc00
# CONSTRUCT x5ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1
# AUNIT --inst x5ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Scalar half precision variant
:frecpe Rd_FPR16, Rn_FPR16
is b_1031=0b0101111011111001110110 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = NEON_frecpe(Rn_FPR16);
}
# C7.2.144 FRECPE page C7-1718 line 96074 MATCH x0ef9d800/mask=xbffffc00
# CONSTRUCT x0ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@2
# AUNIT --inst x0ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant when Q=0 suf=64.4H
:frecpe Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_1029=0b00111011111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_frecpe(Rn_VPR64.4H, 2:1);
}
# C7.2.144 FRECPE page C7-1718 line 96074 MATCH x0ef9d800/mask=xbffffc00
# CONSTRUCT x4ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@2
# AUNIT --inst x4ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant when Q=1 suf=128.8H
:frecpe Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_1029=0b00111011111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_frecpe(Rn_VPR128.8H, 2:1);
}
# C7.2.145 FRECPS page C7-1721 line 96253 MATCH x5e20fc00/mask=xffa0fc00
# CONSTRUCT x5e60fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2
# AUNIT --inst x5e60fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:frecps Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=3 & Rm_FPR64 & b_1115=0x1f & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_frecps(Rn_FPR64, Rm_FPR64);
}
# C7.2.145 FRECPS page C7-1721 line 96253 MATCH x5e20fc00/mask=xffa0fc00
# CONSTRUCT x5e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2
# AUNIT --inst x5e20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:frecps Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=1 & Rm_FPR32 & b_1115=0x1f & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_frecps(Rn_FPR32, Rm_FPR32);
}
# C7.2.145 FRECPS page C7-1721 line 96253 MATCH x0e20fc00/mask=xbfa0fc00
# CONSTRUCT x4e60fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@8
# AUNIT --inst x4e60fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
:frecps Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1f & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_frecps(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.145 FRECPS page C7-1721 line 96253 MATCH x0e20fc00/mask=xbfa0fc00
# CONSTRUCT x0e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@4
# AUNIT --inst x0e20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:frecps Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1f & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_frecps(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.145 FRECPS page C7-1721 line 96253 MATCH x0e20fc00/mask=xbfa0fc00
# CONSTRUCT x4e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@4
# AUNIT --inst x4e20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
:frecps Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1f & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_frecps(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.145 FRECPS page C7-1721 line 96253 MATCH x5e403c00/mask=xffe0fc00
# CONSTRUCT x5e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2
# AUNIT --inst x5e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Scalar half precision variant
:frecps Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_2131=0b01011110010 & b_1015=0b001111 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
{
Rd_FPR16 = NEON_frecps(Rn_FPR16, Rm_FPR16);
}
# C7.2.145 FRECPS page C7-1721 line 96253 MATCH x0e403c00/mask=xbfe0fc00
# CONSTRUCT x0e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@2
# AUNIT --inst x0e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant when Q=0 suf=64.4H
:frecps Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b001111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_frecps(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.145 FRECPS page C7-1721 line 96253 MATCH x0e403c00/mask=xbfe0fc00
# CONSTRUCT x4e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@2
# AUNIT --inst x4e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant when Q=1 suf=128.8H
:frecps Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b001111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_frecps(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.146 FRECPX page C7-1724 line 96442 MATCH x5ef9f800/mask=xfffffc00
# CONSTRUCT x5ef9f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpx/1
# AUNIT --inst x5ef9f800/mask=xfffffc00 --rand hfp --status noqemu
# Half-precision variant
:frecpx Rd_FPR16, Rn_FPR16
is b_1031=0b0101111011111001111110 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = NEON_frecpx(Rn_FPR16);
}
# C7.2.146 FRECPX page C7-1724 line 96442 MATCH x5ea1f800/mask=xffbffc00
# CONSTRUCT x5ea1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpx/1
# AUNIT --inst x5ea1f800/mask=xfffffc00 --rand sfp --status nopcodeop
# Single-precision and double-precision variant when sz=0 suf=32
:frecpx Rd_FPR32, Rn_FPR32
is b_2331=0b010111101 & b_22=0 & b_1021=0b100001111110 & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = NEON_frecpx(Rn_FPR32);
}
# C7.2.146 FRECPX page C7-1724 line 96442 MATCH x5ea1f800/mask=xffbffc00
# CONSTRUCT x5ee1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpx/1
# AUNIT --inst x5ee1f800/mask=xfffffc00 --rand dfp --status nopcodeop
# Single-precision and double-precision variant when sz=1 suf=64
:frecpx Rd_FPR64, Rn_FPR64
is b_2331=0b010111101 & b_22=1 & b_1021=0b100001111110 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_frecpx(Rn_FPR64);
}
# C7.2.140 FRINTA (vector) page C7-1313 line 76386 KEEPWITH
frint_vmode: "a" is b_29=1 & b_23=0 & b_12=0 { }
frint_vmode: "i" is b_29=1 & b_23=1 & b_12=1 { }
frint_vmode: "m" is b_29=0 & b_23=0 & b_12=1 { }
frint_vmode: "n" is b_29=0 & b_23=0 & b_12=0 { }
frint_vmode: "p" is b_29=0 & b_23=1 & b_12=0 { }
frint_vmode: "x" is b_29=1 & b_23=0 & b_12=1 { }
frint_vmode: "z" is b_29=0 & b_23=1 & b_12=1 { }
# C7.2.155 FRINTA (vector) page C7-1742 line 97273 MATCH x2e798800/mask=xbffffc00
# C7.2.157 FRINTI (vector) page C7-1746 line 97503 MATCH x2ef99800/mask=xbffffc00
# C7.2.159 FRINTM (vector) page C7-1750 line 97735 MATCH x0e799800/mask=xbffffc00
# C7.2.161 FRINTN (vector) page C7-1754 line 97967 MATCH x0e798800/mask=xbffffc00
# C7.2.163 FRINTP (vector) page C7-1758 line 98199 MATCH x0ef98800/mask=xbffffc00
# C7.2.165 FRINTX (vector) page C7-1762 line 98431 MATCH x2e799800/mask=xbffffc00
# C7.2.167 FRINTZ (vector) page C7-1766 line 98666 MATCH x0ef99800/mask=xbffffc00
# CONSTRUCT x0e798800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@2
# AUNIT --inst x0e798800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant when Q=0 suf=64.4H
:frint^frint_vmode Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_29 & b_2428=0b01110 & b_23 & b_1322=0b1111001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
# simd unary Rd_VPR64.4H = trunc(Rn_VPR64.4H) on lane size 2
Rd_VPR64.4H[0,16] = trunc(Rn_VPR64.4H[0,16]);
Rd_VPR64.4H[16,16] = trunc(Rn_VPR64.4H[16,16]);
Rd_VPR64.4H[32,16] = trunc(Rn_VPR64.4H[32,16]);
Rd_VPR64.4H[48,16] = trunc(Rn_VPR64.4H[48,16]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.155 FRINTA (vector) page C7-1742 line 97273 MATCH x2e798800/mask=xbffffc00
# C7.2.157 FRINTI (vector) page C7-1746 line 97503 MATCH x2ef99800/mask=xbffffc00
# C7.2.159 FRINTM (vector) page C7-1750 line 97735 MATCH x0e799800/mask=xbffffc00
# C7.2.161 FRINTN (vector) page C7-1754 line 97967 MATCH x0e798800/mask=xbffffc00
# C7.2.163 FRINTP (vector) page C7-1758 line 98199 MATCH x0ef98800/mask=xbffffc00
# C7.2.165 FRINTX (vector) page C7-1762 line 98431 MATCH x2e799800/mask=xbffffc00
# C7.2.167 FRINTZ (vector) page C7-1766 line 98666 MATCH x0ef99800/mask=xbffffc00
# CONSTRUCT x4e798800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@2
# AUNIT --inst x4e798800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant when Q=1 suf=128.8H
:frint^frint_vmode Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_29 & b_2428=0b01110 & b_23 & b_1322=0b1111001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
# simd unary Rd_VPR128.8H = trunc(Rn_VPR128.8H) on lane size 2
Rd_VPR128.8H[0,16] = trunc(Rn_VPR128.8H[0,16]);
Rd_VPR128.8H[16,16] = trunc(Rn_VPR128.8H[16,16]);
Rd_VPR128.8H[32,16] = trunc(Rn_VPR128.8H[32,16]);
Rd_VPR128.8H[48,16] = trunc(Rn_VPR128.8H[48,16]);
Rd_VPR128.8H[64,16] = trunc(Rn_VPR128.8H[64,16]);
Rd_VPR128.8H[80,16] = trunc(Rn_VPR128.8H[80,16]);
Rd_VPR128.8H[96,16] = trunc(Rn_VPR128.8H[96,16]);
Rd_VPR128.8H[112,16] = trunc(Rn_VPR128.8H[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.155 FRINTA (vector) page C7-1742 line 97273 MATCH x2e218800/mask=xbfbffc00
# C7.2.157 FRINTI (vector) page C7-1746 line 97503 MATCH x2ea19800/mask=xbfbffc00
# C7.2.159 FRINTM (vector) page C7-1750 line 97735 MATCH x0e219800/mask=xbfbffc00
# C7.2.161 FRINTN (vector) page C7-1754 line 97967 MATCH x0e218800/mask=xbfbffc00
# C7.2.163 FRINTP (vector) page C7-1758 line 98199 MATCH x0ea18800/mask=xbfbffc00
# C7.2.165 FRINTX (vector) page C7-1762 line 98431 MATCH x2e219800/mask=xbfbffc00
# C7.2.167 FRINTZ (vector) page C7-1766 line 98666 MATCH x0ea19800/mask=xbfbffc00
# CONSTRUCT x0e218800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@4
# AUNIT --inst x0e218800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround"
# Single-precision and double-precision variant when sz=0 Q=0 suf=64.2S
:frint^frint_vmode Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_29 & b_2428=0b01110 & b_23 & b_22=0b0 & b_1321=0b100001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
# simd unary Rd_VPR64.2S = trunc(Rn_VPR64.2S) on lane size 4
Rd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]);
Rd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.155 FRINTA (vector) page C7-1742 line 97273 MATCH x2e218800/mask=xbfbffc00
# C7.2.157 FRINTI (vector) page C7-1746 line 97503 MATCH x2ea19800/mask=xbfbffc00
# C7.2.159 FRINTM (vector) page C7-1750 line 97735 MATCH x0e219800/mask=xbfbffc00
# C7.2.161 FRINTN (vector) page C7-1754 line 97967 MATCH x0e218800/mask=xbfbffc00
# C7.2.163 FRINTP (vector) page C7-1758 line 98199 MATCH x0ea18800/mask=xbfbffc00
# C7.2.165 FRINTX (vector) page C7-1762 line 98431 MATCH x2e219800/mask=xbfbffc00
# C7.2.167 FRINTZ (vector) page C7-1766 line 98666 MATCH x0ea19800/mask=xbfbffc00
# CONSTRUCT x4e218800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@4
# AUNIT --inst x4e218800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround"
# Single-precision and double-precision variant when sz=0 Q=1 suf=128.4S
:frint^frint_vmode Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_29 & b_2428=0b01110 & b_23 & b_22=0b0 & b_1321=0b100001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
# simd unary Rd_VPR128.4S = trunc(Rn_VPR128.4S) on lane size 4
Rd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]);
Rd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]);
Rd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]);
Rd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.155 FRINTA (vector) page C7-1742 line 97273 MATCH x2e218800/mask=xbfbffc00
# C7.2.157 FRINTI (vector) page C7-1746 line 97503 MATCH x2ea19800/mask=xbfbffc00
# C7.2.159 FRINTM (vector) page C7-1750 line 97735 MATCH x0e219800/mask=xbfbffc00
# C7.2.161 FRINTN (vector) page C7-1754 line 97967 MATCH x0e218800/mask=xbfbffc00
# C7.2.163 FRINTP (vector) page C7-1758 line 98199 MATCH x0ea18800/mask=xbfbffc00
# C7.2.165 FRINTX (vector) page C7-1762 line 98431 MATCH x2e219800/mask=xbfbffc00
# C7.2.167 FRINTZ (vector) page C7-1766 line 98666 MATCH x0ea19800/mask=xbfbffc00
# CONSTRUCT x4e618800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$trunc@8
# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@8
# AUNIT --inst x4e618800/mask=xdf7fec00 --rand dfp --status fail --comment "nofpround"
# Single-precision and double-precision variant when sz=1 Q=1 suf=128.2D
:frint^frint_vmode Rd_VPR128.2D, Rn_VPR128.2D
is b_31=0 & b_30=1 & b_29 & b_2428=0b01110 & b_23 & b_22=0b1 & b_1321=0b100001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR128.2D & Rn_VPR128.2D & Zd
{
# simd unary Rd_VPR128.2D = trunc(Rn_VPR128.2D) on lane size 8
Rd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]);
Rd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.141 FRINTA (scalar) page C7-1315 line 76515 KEEPWITH
# FP rounding instruction (not implemented)
frint_smode: "a" is b_1517=0b100 { }
frint_smode: "i" is b_1517=0b111 { }
frint_smode: "m" is b_1517=0b010 { }
frint_smode: "n" is b_1517=0b000 { }
frint_smode: "p" is b_1517=0b001 { }
frint_smode: "x" is b_1517=0b110 { }
frint_smode: "z" is b_1517=0b011 { }
# C7.2.156 FRINTA (scalar) page C7-1744 line 97402 MATCH x1e264000/mask=xff3ffc00
# C7.2.158 FRINTI (scalar) page C7-1748 line 97632 MATCH x1e27c000/mask=xff3ffc00
# C7.2.160 FRINTM (scalar) page C7-1752 line 97864 MATCH x1e254000/mask=xff3ffc00
# C7.2.162 FRINTN (scalar) page C7-1756 line 98096 MATCH x1e244000/mask=xff3ffc00
# C7.2.164 FRINTP (scalar) page C7-1760 line 98328 MATCH x1e24c000/mask=xff3ffc00
# C7.2.166 FRINTX (scalar) page C7-1764 line 98561 MATCH x1e274000/mask=xff3ffc00
# C7.2.168 FRINTZ (scalar) page C7-1768 line 98795 MATCH x1e25c000/mask=xff3ffc00
# CONSTRUCT x1ee44000/mask=xfffc7c00 MATCHED 7 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1
# AUNIT --inst x1ee44000/mask=xfffc7c00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant when type = 11 suf=16
:frint^frint_smode Rd_FPR16, Rn_FPR16
is b_2431=0b00011110 & b_2223=0b11 & b_1821=0b1001 & b_1517 & b_1014=0b10000 & frint_smode & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = trunc(Rn_FPR16);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.156 FRINTA (scalar) page C7-1744 line 97402 MATCH x1e264000/mask=xff3ffc00
# C7.2.158 FRINTI (scalar) page C7-1748 line 97632 MATCH x1e27c000/mask=xff3ffc00
# C7.2.160 FRINTM (scalar) page C7-1752 line 97864 MATCH x1e254000/mask=xff3ffc00
# C7.2.162 FRINTN (scalar) page C7-1756 line 98096 MATCH x1e244000/mask=xff3ffc00
# C7.2.164 FRINTP (scalar) page C7-1760 line 98328 MATCH x1e24c000/mask=xff3ffc00
# C7.2.166 FRINTX (scalar) page C7-1764 line 98561 MATCH x1e274000/mask=xff3ffc00
# C7.2.168 FRINTZ (scalar) page C7-1768 line 98795 MATCH x1e25c000/mask=xff3ffc00
# CONSTRUCT x1e244000/mask=xfffc7c00 MATCHED 7 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1
# AUNIT --inst x1e244000/mask=xfffc7c00 --rand sfp --status fail --comment "nofpround"
# Single-precision variant when type = 00 suf=32
:frint^frint_smode Rd_FPR32, Rn_FPR32
is b_2431=0b00011110 & b_2223=0b00 & b_1821=0b1001 & b_1517 & b_1014=0b10000 & frint_smode & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = trunc(Rn_FPR32);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.156 FRINTA (scalar) page C7-1744 line 97402 MATCH x1e264000/mask=xff3ffc00
# C7.2.158 FRINTI (scalar) page C7-1748 line 97632 MATCH x1e27c000/mask=xff3ffc00
# C7.2.160 FRINTM (scalar) page C7-1752 line 97864 MATCH x1e254000/mask=xff3ffc00
# C7.2.162 FRINTN (scalar) page C7-1756 line 98096 MATCH x1e244000/mask=xff3ffc00
# C7.2.164 FRINTP (scalar) page C7-1760 line 98328 MATCH x1e24c000/mask=xff3ffc00
# C7.2.166 FRINTX (scalar) page C7-1764 line 98561 MATCH x1e274000/mask=xff3ffc00
# C7.2.168 FRINTZ (scalar) page C7-1768 line 98795 MATCH x1e25c000/mask=xff3ffc00
# CONSTRUCT x1e644000/mask=xfffc7c00 MATCHED 7 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =trunc
# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1
# AUNIT --inst x1e644000/mask=xfffc7c00 --rand dfp --status fail --comment "nofpround"
# Double-precision variant when type = 01 suf=64
:frint^frint_smode Rd_FPR64, Rn_FPR64
is b_2431=0b00011110 & b_2223=0b01 & b_1821=0b1001 & b_1517 & b_1014=0b10000 & frint_smode & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = trunc(Rn_FPR64);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.169 FRSQRTE page C7-1770 line 98898 MATCH x7ef9d800/mask=xfffffc00
# CONSTRUCT x7ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1
# AUNIT --inst x7ef9d800/mask=xfffffc00 --status noqemu --comment "nofpround"
# Scalar half precision variant when Q=1 sz=1 ba=11 bb=111 V=FPR16 esize=
:frsqrte Rd_FPR16, Rn_FPR16
is b_31=0 & b_30=1 & b_2329=0b1111101 & b_22=1 & b_1021=0b111001110110 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = NEON_frsqrte(Rn_FPR16);
}
# C7.2.169 FRSQRTE page C7-1770 line 98898 MATCH x7ea1d800/mask=xffbffc00
# CONSTRUCT x7ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1
# AUNIT --inst x7ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
# Scalar single-precision and double-precision variant when Q=1 sz=0 ba=11 bb=100 V=FPR32 esize=
:frsqrte Rd_FPR32, Rn_FPR32
is b_31=0 & b_30=1 & b_2329=0b1111101 & b_22=0 & b_1021=0b100001110110 & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = NEON_frsqrte(Rn_FPR32);
}
# C7.2.169 FRSQRTE page C7-1770 line 98898 MATCH x7ea1d800/mask=xffbffc00
# CONSTRUCT x7ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1
# AUNIT --inst x7ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
# Scalar single-precision and double-precision variant when Q=1 sz=1 ba=11 bb=100 V=FPR64 esize=
:frsqrte Rd_FPR64, Rn_FPR64
is b_31=0 & b_30=1 & b_2329=0b1111101 & b_22=1 & b_1021=0b100001110110 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_frsqrte(Rn_FPR64);
}
# C7.2.169 FRSQRTE page C7-1770 line 98898 MATCH x2ef9d800/mask=xbffffc00
# CONSTRUCT x2ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@2
# AUNIT --inst x2ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant when Q=0 sz=1 ba=10 bb=111 V=VPR64.4H esize=@2
:frsqrte Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_frsqrte(Rn_VPR64.4H, 2:1);
}
# C7.2.169 FRSQRTE page C7-1770 line 98898 MATCH x2ef9d800/mask=xbffffc00
# CONSTRUCT x6ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@2
# AUNIT --inst x6ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant when Q=1 sz=1 ba=10 bb=111 V=VPR128.8H esize=@2
:frsqrte Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_frsqrte(Rn_VPR128.8H, 2:1);
}
# C7.2.169 FRSQRTE page C7-1770 line 98898 MATCH x2ea1d800/mask=xbfbffc00
# CONSTRUCT x2ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@4
# AUNIT --inst x2ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
# Vector single-precision and double-precision variant when Q=0 sz=0 ba=10 bb=100 V=VPR64.2S esize=@4
:frsqrte Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_frsqrte(Rn_VPR64.2S, 4:1);
}
# C7.2.169 FRSQRTE page C7-1770 line 98898 MATCH x2ea1d800/mask=xbfbffc00
# CONSTRUCT x6ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@4
# AUNIT --inst x6ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
# Vector single-precision and double-precision variant when Q=1 sz=0 ba=10 bb=100 V=VPR128.4S esize=@4
:frsqrte Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_frsqrte(Rn_VPR128.4S, 4:1);
}
# C7.2.169 FRSQRTE page C7-1770 line 98898 MATCH x2ea1d800/mask=xbfbffc00
# CONSTRUCT x6ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@8
# AUNIT --inst x6ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
# Vector single-precision and double-precision variant when Q=1 sz=1 ba=10 bb=100 V=VPR128.2D esize=@8
:frsqrte Rd_VPR128.2D, Rn_VPR128.2D
is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b100001110110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_frsqrte(Rn_VPR128.2D, 8:1);
}
# C7.2.170 FRSQRTS page C7-1773 line 99077 MATCH x5ec03c00/mask=xffe0fc00
# CONSTRUCT x5ec03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrts/1
# AUNIT --inst x5ec03c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Scalar half precision variant when Q=1 sz=1 ba=01 bb=0 bc=00 V=FPR16 esize=
:frsqrts Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_31=0 & b_30=1 & b_2329=0b0111101 & b_22=1 & b_21=0 & b_1015=0b001111 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
{
Rd_FPR16 = NEON_frsqrts(Rn_FPR16);
}
# C7.2.170 FRSQRTS page C7-1773 line 99077 MATCH x5ea0fc00/mask=xffa0fc00
# CONSTRUCT x5ea0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2
# AUNIT --inst x5ea0fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
# Scalar single-precision and double-precision variant when Q=1 sz=0 ba=01 bb=1 bc=11 V=FPR32 esize=
:frsqrts Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_31=0 & b_30=1 & b_2329=0b0111101 & b_22=0 & b_21=1 & b_1015=0b111111 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
{
Rd_FPR32 = NEON_frsqrts(Rn_FPR32, Rm_FPR32);
}
# C7.2.170 FRSQRTS page C7-1773 line 99077 MATCH x5ea0fc00/mask=xffa0fc00
# CONSTRUCT x5ee0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2
# AUNIT --inst x5ee0fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
# Scalar single-precision and double-precision variant when Q=1 sz=1 ba=01 bb=1 bc=11 V=FPR64 esize=
:frsqrts Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_31=0 & b_30=1 & b_2329=0b0111101 & b_22=1 & b_21=1 & b_1015=0b111111 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
{
Rd_FPR64 = NEON_frsqrts(Rn_FPR64, Rm_FPR64);
}
# C7.2.170 FRSQRTS page C7-1773 line 99077 MATCH x0ec03c00/mask=xbfe0fc00
# CONSTRUCT x0ec03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@2
# AUNIT --inst x0ec03c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant when Q=0 sz=1 ba=00 bb=0 bc=00 V=VPR64.4H esize=@2
:frsqrts Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=1 & b_21=0 & b_1015=0b001111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_frsqrts(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.170 FRSQRTS page C7-1773 line 99077 MATCH x0ec03c00/mask=xbfe0fc00
# CONSTRUCT x4ec03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@2
# AUNIT --inst x4ec03c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Vector half precision variant when Q=1 sz=1 ba=00 bb=0 bc=00 V=VPR128.8H esize=@2
:frsqrts Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=1 & b_21=0 & b_1015=0b001111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_frsqrts(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.170 FRSQRTS page C7-1773 line 99077 MATCH x0ea0fc00/mask=xbfa0fc00
# CONSTRUCT x0ea0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@4
# AUNIT --inst x0ea0fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
# Vector single-precision and double-precision variant when Q=0 sz=0 ba=00 bb=1 bc=11 V=VPR64.2S esize=@4
:frsqrts Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111111 & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_frsqrts(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.170 FRSQRTS page C7-1773 line 99077 MATCH x0ea0fc00/mask=xbfa0fc00
# CONSTRUCT x4ea0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@4
# AUNIT --inst x4ea0fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
# Vector single-precision and double-precision variant when Q=1 sz=0 ba=00 bb=1 bc=11 V=VPR128.4S esize=@4
:frsqrts Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111111 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_frsqrts(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.170 FRSQRTS page C7-1773 line 99077 MATCH x0ea0fc00/mask=xbfa0fc00
# CONSTRUCT x4ee0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@8
# AUNIT --inst x4ee0fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
# Vector single-precision and double-precision variant when Q=1 sz=1 ba=00 bb=1 bc=11 V=VPR128.2D esize=@8
:frsqrts Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=1 & b_21=1 & b_1015=0b111111 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_frsqrts(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.171 FSQRT (vector) page C7-1776 line 99266 MATCH x2ef9f800/mask=xbffffc00
# CONSTRUCT x2ef9f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@2
# AUNIT --inst x2ef9f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant when Q=0 sz=1 ba=111 esize=2 suf=VPR64.4H
:fsqrt Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001111110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_fsqrt(Rn_VPR64.4H, 2:1);
}
# C7.2.171 FSQRT (vector) page C7-1776 line 99266 MATCH x2ef9f800/mask=xbffffc00
# CONSTRUCT x6ef9f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@2
# AUNIT --inst x6ef9f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant when Q=1 sz=1 ba=111 esize=2 suf=VPR128.8H
:fsqrt Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001111110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_fsqrt(Rn_VPR128.8H, 2:1);
}
# C7.2.171 FSQRT (vector) page C7-1776 line 99266 MATCH x2ea1f800/mask=xbfbffc00
# CONSTRUCT x2ea1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@4
# AUNIT --inst x2ea1f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
# Single-precision and double-precision variant when Q=0 sz=0 ba=100 esize=4 suf=VPR64.2S
:fsqrt Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001111110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_fsqrt(Rn_VPR64.2S, 4:1);
}
# C7.2.171 FSQRT (vector) page C7-1776 line 99266 MATCH x2ea1f800/mask=xbfbffc00
# CONSTRUCT x6ea1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@4
# AUNIT --inst x6ea1f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
# Single-precision and double-precision variant when Q=1 sz=0 ba=100 esize=4 suf=VPR128.4S
:fsqrt Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001111110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_fsqrt(Rn_VPR128.4S, 4:1);
}
# C7.2.171 FSQRT (vector) page C7-1776 line 99266 MATCH x2ea1f800/mask=xbfbffc00
# CONSTRUCT x6ee1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@8
# AUNIT --inst x6ee1f800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
# Single-precision and double-precision variant when Q=1 sz=1 ba=100 esize=8 suf=VPR128.2D
:fsqrt Rd_VPR128.2D, Rn_VPR128.2D
is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b100001111110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_fsqrt(Rn_VPR128.2D, 8:1);
}
# C7.2.172 FSQRT (scalar) page C7-1778 line 99375 MATCH x1e21c000/mask=xff3ffc00
# CONSTRUCT x1ee1c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =sqrt/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1
# AUNIT --inst x1ee1c000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant
:fsqrt Rd_FPR16, Rn_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x3 & b_1014=0x10 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = sqrt(Rn_FPR16);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.172 FSQRT (scalar) page C7-1778 line 99375 MATCH x1e21c000/mask=xff3ffc00
# CONSTRUCT x1e21c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =sqrt/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1
# AUNIT --inst x1e21c000/mask=xfffffc00 --rand sfp --status fail --comment "nofpround"
# Single-precision variant
:fsqrt Rd_FPR32, Rn_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x3 & b_1014=0x10 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = sqrt(Rn_FPR32);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.172 FSQRT (scalar) page C7-1778 line 99375 MATCH x1e21c000/mask=xff3ffc00
# CONSTRUCT x1e61c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =sqrt/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1
# AUNIT --inst x1e61c000/mask=xfffffc00 --rand dfp --status fail --comment "nofpround"
# Double-precision variant
:fsqrt Rd_FPR64, Rn_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x3 & b_1014=0x10 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = sqrt(Rn_FPR64);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.173 FSUB (vector) page C7-1780 line 99472 MATCH x0ea0d400/mask=xbfa0fc00
# CONSTRUCT x4ee0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@8
# AUNIT --inst x4ee0d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
:fsub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1a & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd infix Rd_VPR128.2D = Rn_VPR128.2D f- Rm_VPR128.2D on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f- Rm_VPR128.2D[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f- Rm_VPR128.2D[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.173 FSUB (vector) page C7-1780 line 99472 MATCH x0ea0d400/mask=xbfa0fc00
# CONSTRUCT x0ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@4
# AUNIT --inst x0ea0d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
:fsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1a & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix Rd_VPR64.2S = Rn_VPR64.2S f- Rm_VPR64.2S on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f- Rm_VPR64.2S[0,32];
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f- Rm_VPR64.2S[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.173 FSUB (vector) page C7-1780 line 99472 MATCH x0ea0d400/mask=xbfa0fc00
# CONSTRUCT x4ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@4
# AUNIT --inst x4ea0d400/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
:fsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1a & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd infix Rd_VPR128.4S = Rn_VPR128.4S f- Rm_VPR128.4S on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f- Rm_VPR128.4S[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f- Rm_VPR128.4S[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f- Rm_VPR128.4S[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f- Rm_VPR128.4S[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.173 FSUB (vector) page C7-1780 line 99472 MATCH x0ec01400/mask=xbfe0fc00
# CONSTRUCT x0ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@2
# AUNIT --inst x0ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant when Q=0 suf=VPR64.4H
:fsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
{
# simd infix Rd_VPR64.4H = Rn_VPR64.4H f- Rm_VPR64.4H on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f- Rm_VPR64.4H[0,16];
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f- Rm_VPR64.4H[16,16];
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f- Rm_VPR64.4H[32,16];
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f- Rm_VPR64.4H[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.173 FSUB (vector) page C7-1780 line 99472 MATCH x0ec01400/mask=xbfe0fc00
# CONSTRUCT x4ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$f-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@2
# AUNIT --inst x4ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
# Half-precision variant when Q=1 suf=VPR128.8H
:fsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
{
# simd infix Rd_VPR128.8H = Rn_VPR128.8H f- Rm_VPR128.8H on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f- Rm_VPR128.8H[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f- Rm_VPR128.8H[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f- Rm_VPR128.8H[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f- Rm_VPR128.8H[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f- Rm_VPR128.8H[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f- Rm_VPR128.8H[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f- Rm_VPR128.8H[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f- Rm_VPR128.8H[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.174 FSUB (scalar) page C7-1782 line 99588 MATCH x1e203800/mask=xff20fc00
# CONSTRUCT x1e603800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f-
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2
# AUNIT --inst x1e603800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
:fsub Rd_FPR64, Rn_FPR64, Rm_FPR64
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x3 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = Rn_FPR64 f- Rm_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.174 FSUB (scalar) page C7-1782 line 99588 MATCH x1e203800/mask=xff20fc00
# CONSTRUCT x1e203800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f-
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2
# AUNIT --inst x1e203800/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
:fsub Rd_FPR32, Rn_FPR32, Rm_FPR32
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x3 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = Rn_FPR32 f- Rm_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.174 FSUB (scalar) page C7-1782 line 99588 MATCH x1e203800/mask=xff20fc00
# CONSTRUCT x1ee03800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =f-
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2
# AUNIT --inst x1ee03800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
:fsub Rd_FPR16, Rn_FPR16, Rm_FPR16
is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x3 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = Rn_FPR16 f- Rm_FPR16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.189 LDNP (SIMD&FP) page C7-1829 line 102510 MATCH x2c400000/mask=x3fc00000
# CONSTRUCT x2c400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 4 +:8 =load ext
# SMACRO(pseudo) ARG1 ARG3 =NEON_ldnp1/1 ARG2 ARG3 =NEON_ldnp2/1
# AUNIT --inst x2c400000/mask=xffc00000 --status nomem
:ldnp Rt_FPR32, Rt2_FPR32, addrPairIndexed
is b_3031=0b00 & b_2229=0b10110001 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32 & Zt & Zt2
{
Rt_FPR32 = * addrPairIndexed;
zext_zs(Zt); # zero upper 28 bytes of Zt
local tmp1:8 = addrPairIndexed + 4;
Rt2_FPR32 = * tmp1;
zext_zs(Zt2); # zero upper 28 bytes of Zt2
}
# C7.2.189 LDNP (SIMD&FP) page C7-1829 line 102510 MATCH x2c400000/mask=x3fc00000
# CONSTRUCT x6c400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 8 +:8 =load ext
# SMACRO(pseudo) ARG1 ARG3 =NEON_ldnp1/1 ARG2 ARG3 =NEON_ldnp2/1
# AUNIT --inst x6c400000/mask=xffc00000 --status nomem
:ldnp Rt_FPR64, Rt2_FPR64, addrPairIndexed
is b_3031=0b01 & b_2229=0b10110001 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64 & Zt & Zt2
{
Rt_FPR64 = * addrPairIndexed;
zext_zd(Zt); # zero upper 24 bytes of Zt
local tmp1:8 = addrPairIndexed + 8;
Rt2_FPR64 = * tmp1;
zext_zd(Zt2); # zero upper 24 bytes of Zt2
}
# C7.2.189 LDNP (SIMD&FP) page C7-1829 line 102510 MATCH x2c400000/mask=x3fc00000
# CONSTRUCT xac400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 16 +:8 =load ext
# SMACRO(pseudo) ARG1 ARG3 =NEON_ldnp1/1 ARG2 ARG3 =NEON_ldnp2/1
# AUNIT --inst xac400000/mask=xffc00000 --status nomem
:ldnp Rt_FPR128, Rt2_FPR128, addrPairIndexed
is b_3031=0b10 & b_2229=0b10110001 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128 & Zt & Zt2
{
Rt_FPR128 = * addrPairIndexed;
zext_zq(Zt); # zero upper 16 bytes of Zt
local tmp1:8 = addrPairIndexed + 16;
Rt2_FPR128 = * tmp1;
zext_zq(Zt2); # zero upper 16 bytes of Zt2
}
# C7.2.190 LDP (SIMD&FP) page C7-1831 line 102650 MATCH x2cc00000/mask=x3fc00000
# C7.2.190 LDP (SIMD&FP) page C7-1831 line 102650 MATCH x2dc00000/mask=x3fc00000
# C7.2.190 LDP (SIMD&FP) page C7-1831 line 102650 MATCH x2d400000/mask=x3fc00000
# C7.2.189 LDNP (SIMD&FP) page C7-1829 line 102510 MATCH x2c400000/mask=x3fc00000
# CONSTRUCT xac400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 16 +:8 =load ext
# SMACRO(pseudo) ARG1 ARG3 =NEON_ldp1/1 ARG2 ARG3 =NEON_ldp2/1
# AUNIT --inst xac400000/mask=xfe400000 --status nomem
:ldp Rt_FPR128, Rt2_FPR128, addrPairIndexed
is b_3031=0b10 & b_2529=0b10110 & b_22=0b1 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128 & Zt & Zt2
{
Rt_FPR128 = * addrPairIndexed;
zext_zq(Zt); # zero upper 16 bytes of Zt
local tmp1:8 = addrPairIndexed + 16;
Rt2_FPR128 = * tmp1;
zext_zq(Zt2); # zero upper 16 bytes of Zt2
}
# C7.2.190 LDP (SIMD&FP) page C7-1831 line 102650 MATCH x2cc00000/mask=x3fc00000
# C7.2.190 LDP (SIMD&FP) page C7-1831 line 102650 MATCH x2dc00000/mask=x3fc00000
# C7.2.190 LDP (SIMD&FP) page C7-1831 line 102650 MATCH x2d400000/mask=x3fc00000
# C7.2.189 LDNP (SIMD&FP) page C7-1829 line 102510 MATCH x2c400000/mask=x3fc00000
# CONSTRUCT x2c400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 4 +:8 =load ext
# SMACRO(pseudo) ARG1 ARG3 =NEON_ldp1/1 ARG2 ARG3 =NEON_ldp2/1
# AUNIT --inst x2c400000/mask=xfe400000 --status nomem
:ldp Rt_FPR32, Rt2_FPR32, addrPairIndexed
is b_3031=0b00 & b_2529=0b10110 & b_22=0b1 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32 & Zt & Zt2
{
Rt_FPR32 = * addrPairIndexed;
zext_zs(Zt); # zero upper 28 bytes of Zt
local tmp1:8 = addrPairIndexed + 4;
Rt2_FPR32 = * tmp1;
zext_zs(Zt2); # zero upper 28 bytes of Zt2
}
# C7.2.190 LDP (SIMD&FP) page C7-1831 line 102650 MATCH x2cc00000/mask=x3fc00000
# C7.2.190 LDP (SIMD&FP) page C7-1831 line 102650 MATCH x2dc00000/mask=x3fc00000
# C7.2.190 LDP (SIMD&FP) page C7-1831 line 102650 MATCH x2d400000/mask=x3fc00000
# C7.2.189 LDNP (SIMD&FP) page C7-1829 line 102510 MATCH x2c400000/mask=x3fc00000
# CONSTRUCT x6c400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 8 +:8 =load ext
# SMACRO(pseudo) ARG1 ARG3 =NEON_ldp1/1 ARG2 ARG3 =NEON_ldp2/1
# AUNIT --inst x6c400000/mask=xfe400000 --status nomem
:ldp Rt_FPR64, Rt2_FPR64, addrPairIndexed
is b_3031=0b01 & b_2529=0b10110 & b_22=0b1 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64 & Zt & Zt2
{
Rt_FPR64 = * addrPairIndexed;
zext_zd(Zt); # zero upper 24 bytes of Zt
local tmp1:8 = addrPairIndexed + 8;
Rt2_FPR64 = * tmp1;
zext_zd(Zt2); # zero upper 24 bytes of Zt2
}
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3c400400/mask=x3f600c00
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3c400c00/mask=x3f600c00
# CONSTRUCT x3c400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst x3c400400/mask=xffe00400 --status nomem
# Post- and Pre-index 8-bit variant when size==00 && opc==01 F=FPR8
:ldr Rt_FPR8, addrIndexed
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR8 & addrIndexed & Zt
{
Rt_FPR8 = * addrIndexed;
zext_zb(Zt); # zero upper 31 bytes of Zt
}
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3c400400/mask=x3f600c00
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3c400c00/mask=x3f600c00
# CONSTRUCT x7c400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst x7c400400/mask=xffe00400 --status nomem
# Post- and Pre-index 16-bit variant when size==01 && opc==01 F=FPR16
:ldr Rt_FPR16, addrIndexed
is b_3031=0b01 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR16 & addrIndexed & Zt
{
Rt_FPR16 = * addrIndexed;
zext_zh(Zt); # zero upper 30 bytes of Zt
}
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3c400400/mask=x3f600c00
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3c400c00/mask=x3f600c00
# CONSTRUCT xbc400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst xbc400400/mask=xffe00400 --status nomem
# Post- and Pre-index 32-bit variant when size==10 && opc==01 F=FPR32
:ldr Rt_FPR32, addrIndexed
is b_3031=0b10 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR32 & addrIndexed & Zt
{
Rt_FPR32 = * addrIndexed;
zext_zs(Zt); # zero upper 28 bytes of Zt
}
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3c400400/mask=x3f600c00
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3c400c00/mask=x3f600c00
# CONSTRUCT xfc400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst xfc400400/mask=xffe00400 --status nomem
# Post- and Pre-index 64-bit variant when size==11 && opc==01 F=FPR64
:ldr Rt_FPR64, addrIndexed
is b_3031=0b11 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR64 & addrIndexed & Zt
{
Rt_FPR64 = * addrIndexed;
zext_zd(Zt); # zero upper 24 bytes of Zt
}
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3c400400/mask=x3f600c00
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3c400c00/mask=x3f600c00
# CONSTRUCT x3cc00400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst x3cc00400/mask=xffe00400 --status nomem
# Post- and Pre-index 128-bit variant when size==00 && opc==11 F=FPR128
:ldr Rt_FPR128, addrIndexed
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b11 & b_21=0 & b_10=1 & Rt_FPR128 & addrIndexed & Zt
{
Rt_FPR128 = * addrIndexed;
zext_zq(Zt); # zero upper 16 bytes of Zt
}
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3d400000/mask=x3f400000
# CONSTRUCT x3d400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst x3d400000/mask=xffc00000 --status nomem
# Unsigned offset 8-bit variant when size == 00 && opc == 01 F=FPR8
:ldr Rt_FPR8, addrUIMM
is b_3031=0b00 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR8 & addrUIMM & Zt
{
Rt_FPR8 = * addrUIMM;
zext_zb(Zt); # zero upper 31 bytes of Zt
}
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3d400000/mask=x3f400000
# CONSTRUCT x7d400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst x7d400000/mask=xffc00000 --status nomem
# Unsigned offset 16-bit variant when size == 01 && opc == 01 F=FPR16
:ldr Rt_FPR16, addrUIMM
is b_3031=0b01 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR16 & addrUIMM & Zt
{
Rt_FPR16 = * addrUIMM;
zext_zh(Zt); # zero upper 30 bytes of Zt
}
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3d400000/mask=x3f400000
# CONSTRUCT xbd400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst xbd400000/mask=xffc00000 --status nomem
# Unsigned offset 32-bit variant when size == 10 && opc == 01 F=FPR32
:ldr Rt_FPR32, addrUIMM
is b_3031=0b10 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR32 & addrUIMM & Zt
{
Rt_FPR32 = * addrUIMM;
zext_zs(Zt); # zero upper 28 bytes of Zt
}
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3d400000/mask=x3f400000
# CONSTRUCT xfd400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst xfd400000/mask=xffc00000 --status nomem
# Unsigned offset 64-bit variant when size == 11 && opc == 01 F=FPR64
:ldr Rt_FPR64, addrUIMM
is b_3031=0b11 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR64 & addrUIMM & Zt
{
Rt_FPR64 = * addrUIMM;
zext_zd(Zt); # zero upper 24 bytes of Zt
}
# C7.2.191 LDR (immediate, SIMD&FP) page C7-1835 line 102884 MATCH x3d400000/mask=x3f400000
# CONSTRUCT x3dc00000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst x3dc00000/mask=xffc00000 --status nomem
# Unsigned offset 128-bit variant when size == 00 && opc == 11 F=FPR128
:ldr Rt_FPR128, addrUIMM
is b_3031=0b00 & b_2429=0b111101 & b_2223=0b11 & Rt_FPR128 & addrUIMM & Zt
{
Rt_FPR128 = * addrUIMM;
zext_zq(Zt); # zero upper 16 bytes of Zt
}
# C7.2.192 LDR (literal, SIMD&FP) page C7-1839 line 103142 MATCH x1c000000/mask=x3f000000
# CONSTRUCT x5c000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load:8
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst x5c000000/mask=xff000000 --status nomem
:ldr Rt_FPR64, AddrLoc19
is size.ldstr=1 & b_2729=3 & v=1 & b_2425=0 & AddrLoc19 & Rt_FPR64 & Zt
{
Rt_FPR64 = *:8 AddrLoc19;
zext_zd(Zt); # zero upper 24 bytes of Zt
}
# C7.2.192 LDR (literal, SIMD&FP) page C7-1839 line 103142 MATCH x1c000000/mask=x3f000000
# CONSTRUCT x9c000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load:16
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst x9c000000/mask=xff000000 --status nomem
:ldr Rt_FPR128, AddrLoc19
is size.ldstr=2 & b_2729=3 & v=1 & b_2425=0 & AddrLoc19 & Rt_FPR128 & Zt
{
Rt_FPR128 = *:16 AddrLoc19;
zext_zq(Zt); # zero upper 16 bytes of Zt
}
# C7.2.192 LDR (literal, SIMD&FP) page C7-1839 line 103142 MATCH x1c000000/mask=x3f000000
# CONSTRUCT x1c000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load:4
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
# AUNIT --inst x1c000000/mask=xff000000 --status nomem
:ldr Rt_FPR32, AddrLoc19
is size.ldstr=0 & b_2729=3 & v=1 & b_2425=0 & AddrLoc19 & Rt_FPR32 & Zt
{
Rt_FPR32 = *:4 AddrLoc19;
zext_zs(Zt); # zero upper 28 bytes of Zt
}
# C7.2.178 LDR (register, SIMD&FP) page C7-1411 line 82199 KEEPWITH
extend_amount: "" is b_3031=0b00 & b_23=0 & b_12=0 { export 0:1; }
extend_amount: " #0" is b_3031=0b00 & b_23=0 & b_12=1 { export 0:1; }
extend_amount: "" is b_3031=0b01 & b_23=0 & b_12=0 { export 0:1; }
extend_amount: " #1" is b_3031=0b01 & b_23=0 & b_12=1 { export 1:1; }
extend_amount: "" is b_3031=0b10 & b_23=0 & b_12=0 { export 0:1; }
extend_amount: " #2" is b_3031=0b10 & b_23=0 & b_12=1 { export 2:1; }
extend_amount: "" is b_3031=0b11 & b_23=0 & b_12=0 { export 0:1; }
extend_amount: " #3" is b_3031=0b11 & b_23=0 & b_12=1 { export 3:1; }
extend_amount: "" is b_3031=0b00 & b_23=1 & b_12=0 { export 0:1; }
extend_amount: " #4" is b_3031=0b00 & b_23=1 & b_12=1 { export 4:1; }
extend_spec: ", uxtw" is b_1315=0b010 & Rm_GPR32 { local tmp:8 = zext(Rm_GPR32); export tmp; }
extend_spec: ", sxtw" is b_1315=0b110 & Rm_GPR32 { local tmp:8 = sext(Rm_GPR32); export tmp; }
extend_spec: ", sxtx" is b_1315=0b111 & Rm_GPR64 { export Rm_GPR64; }
extend_spec: ", lsl" is b_1315=0b011 & b_12=1 & Rm_GPR64 { export Rm_GPR64; } # same as uxtx
extend_spec: "" is b_1315=0b011 & b_12=0 & Rm_GPR64 { export Rm_GPR64; } # same as uxtx
# C7.2.193 LDR (register, SIMD&FP) page C7-1841 line 103241 MATCH x3c600800/mask=x3f600c00
# CONSTRUCT x3c600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
# AUNIT --inst x3c600800/mask=xffe02c00 --status nomem
# 8-fsreg,LDR-8-fsreg variant when size == 00 && opc == 01 && option is not 011 bb=b_13 option=0 F=FPR8 G=GPR32
:ldr Rt_FPR8, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
Rt_FPR8 = * tmp2;
zext_zb(Zt); # zero upper 31 bytes of Zt
}
# C7.2.193 LDR (register, SIMD&FP) page C7-1841 line 103241 MATCH x3c600800/mask=x3f600c00
# CONSTRUCT x3c602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
# AUNIT --inst x3c602800/mask=xffe02c00 --status nomem
# 8-fsreg,LDR-8-fsreg variant when size == 00 && opc == 01 && option is not 011 bb=b_13 option=1 F=FPR8 G=GPR64
:ldr Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
Rt_FPR8 = * tmp2;
zext_zb(Zt); # zero upper 31 bytes of Zt
}
# C7.2.193 LDR (register, SIMD&FP) page C7-1841 line 103241 MATCH x3c600800/mask=x3f600c00
# CONSTRUCT x3c606800/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
# AUNIT --inst x3c606800/mask=xffe0ec00 --status nomem
# 8-fsreg,LDR-8-fsreg variant when size == 00 && opc == 01 && option is 011 bb=b_1315 option=0b011 F=FPR8 G=GPR64
:ldr Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_1315=0b011 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
Rt_FPR8 = * tmp2;
zext_zb(Zt); # zero upper 31 bytes of Zt
}
# C7.2.193 LDR (register, SIMD&FP) page C7-1841 line 103241 MATCH x3c600800/mask=x3f600c00
# CONSTRUCT x7c600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
# AUNIT --inst x7c600800/mask=xffe02c00 --status nomem
# 16-fsreg,LDR-16-fsreg variant when size == 01 && opc == 01 bb=b_13 option=0 F=FPR16 G=GPR32
:ldr Rt_FPR16, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
is b_3031=0b01 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
Rt_FPR16 = * tmp2;
zext_zh(Zt); # zero upper 30 bytes of Zt
}
# C7.2.193 LDR (register, SIMD&FP) page C7-1841 line 103241 MATCH x3c600800/mask=x3f600c00
# CONSTRUCT x7c602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
# AUNIT --inst x7c602800/mask=xffe02c00 --status nomem
# 16-fsreg,LDR-16-fsreg variant when size == 01 && opc == 01 bb=b_13 option=1 F=FPR16 G=GPR64
:ldr Rt_FPR16, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
is b_3031=0b01 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
Rt_FPR16 = * tmp2;
zext_zh(Zt); # zero upper 30 bytes of Zt
}
# C7.2.193 LDR (register, SIMD&FP) page C7-1841 line 103241 MATCH x3c600800/mask=x3f600c00
# CONSTRUCT xbc600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
# AUNIT --inst xbc600800/mask=xffe02c00 --status nomem
# 32-fsreg,LDR-32-fsreg variant when size == 10 && opc == 01 bb=b_13 option=0 F=FPR32 G=GPR32
:ldr Rt_FPR32, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
is b_3031=0b10 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
Rt_FPR32 = * tmp2;
zext_zs(Zt); # zero upper 28 bytes of Zt
}
# C7.2.193 LDR (register, SIMD&FP) page C7-1841 line 103241 MATCH x3c600800/mask=x3f600c00
# CONSTRUCT xbc602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
# AUNIT --inst xbc602800/mask=xffe02c00 --status nomem
# 32-fsreg,LDR-32-fsreg variant when size == 10 && opc == 01 bb=b_13 option=1 F=FPR32 G=GPR64
:ldr Rt_FPR32, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
is b_3031=0b10 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
Rt_FPR32 = * tmp2;
zext_zs(Zt); # zero upper 28 bytes of Zt
}
# C7.2.193 LDR (register, SIMD&FP) page C7-1841 line 103241 MATCH x3c600800/mask=x3f600c00
# CONSTRUCT xfc600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
# AUNIT --inst xfc600800/mask=xffe02c00 --status nomem
# 64-fsreg,LDR-64-fsreg variant when size == 11 && opc == 01 bb=b_13 option=0 F=FPR64 G=GPR32
:ldr Rt_FPR64, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
is b_3031=0b11 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
Rt_FPR64 = * tmp2;
zext_zd(Zt); # zero upper 24 bytes of Zt
}
# C7.2.193 LDR (register, SIMD&FP) page C7-1841 line 103241 MATCH x3c600800/mask=x3f600c00
# CONSTRUCT xfc602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
# AUNIT --inst xfc602800/mask=xffe02c00 --status nomem
# 64-fsreg,LDR-64-fsreg variant when size == 11 && opc == 01 bb=b_13 option=1 F=FPR64 G=GPR64
:ldr Rt_FPR64, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
is b_3031=0b11 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
Rt_FPR64 = * tmp2;
zext_zd(Zt); # zero upper 24 bytes of Zt
}
# C7.2.193 LDR (register, SIMD&FP) page C7-1841 line 103241 MATCH x3c600800/mask=x3f600c00
# CONSTRUCT x3ce00800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
# AUNIT --inst x3ce00800/mask=xffe02c00 --status nomem
# 128-fsreg,LDR-128-fsreg variant when size == 00 && opc == 11 bb=b_13 option=0 F=FPR128 G=GPR32
:ldr Rt_FPR128, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b11 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
Rt_FPR128 = * tmp2;
zext_zq(Zt); # zero upper 16 bytes of Zt
}
# C7.2.193 LDR (register, SIMD&FP) page C7-1841 line 103241 MATCH x3c600800/mask=x3f600c00
# CONSTRUCT x3ce02800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
# AUNIT --inst x3ce02800/mask=xffe02c00 --status nomem
# 128-fsreg,LDR-128-fsreg variant when size == 00 && opc == 11 bb=b_13 option=1 F=FPR128 G=GPR64
:ldr Rt_FPR128, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b11 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
Rt_FPR128 = * tmp2;
zext_zq(Zt); # zero upper 16 bytes of Zt
}
# C7.2.194 LDUR (SIMD&FP) page C7-1844 line 103424 MATCH x3c400000/mask=x3f600c00
# CONSTRUCT x3cc00000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1
# AUNIT --inst x3cc00000/mask=xffe00c00 --status nomem
:ldur Rt_FPR128, addrIndexed
is size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=1 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR128 & Zt
{
Rt_FPR128 = * addrIndexed;
zext_zq(Zt); # zero upper 16 bytes of Zt
}
# C7.2.194 LDUR (SIMD&FP) page C7-1844 line 103424 MATCH x3c400000/mask=x3f600c00
# CONSTRUCT x7c400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1
# AUNIT --inst x7c400000/mask=xffe00c00 --status nomem
:ldur Rt_FPR16, addrIndexed
is size.ldstr=1 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR16 & Zt
{
Rt_FPR16 = * addrIndexed;
zext_zh(Zt); # zero upper 30 bytes of Zt
}
# C7.2.194 LDUR (SIMD&FP) page C7-1844 line 103424 MATCH x3c400000/mask=x3f600c00
# CONSTRUCT xbc400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1
# AUNIT --inst xbc400000/mask=xffe00c00 --status nomem
:ldur Rt_FPR32, addrIndexed
is size.ldstr=2 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR32 & Zt
{
Rt_FPR32 = * addrIndexed;
zext_zs(Zt); # zero upper 28 bytes of Zt
}
# C7.2.194 LDUR (SIMD&FP) page C7-1844 line 103424 MATCH x3c400000/mask=x3f600c00
# CONSTRUCT xfc400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1
# AUNIT --inst xfc400000/mask=xffe00c00 --status nomem
:ldur Rt_FPR64, addrIndexed
is size.ldstr=3 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR64 & Zt
{
Rt_FPR64 = * addrIndexed;
zext_zd(Zt); # zero upper 24 bytes of Zt
}
# C7.2.194 LDUR (SIMD&FP) page C7-1844 line 103424 MATCH x3c400000/mask=x3f600c00
# CONSTRUCT x3c400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =load
# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1
# AUNIT --inst x3c400000/mask=xffe00c00 --status nomem
:ldur Rt_FPR8, addrIndexed
is size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR8 & Zt
{
Rt_FPR8 = * addrIndexed;
zext_zb(Zt); # zero upper 31 bytes of Zt
}
# C7.2.195 MLA (by element) page C7-1846 line 103549 MATCH x2f000000/mask=xbf00f400
# CONSTRUCT x2f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $* &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4
# AUNIT --inst x2f800000/mask=xffc0f400 --status pass
:mla Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & vIndex & Re_VPR128.S & b_1215=0x0 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix TMPD1 = Rn_VPR64.2S * tmp1 on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] * tmp1;
TMPD1[32,32] = Rn_VPR64.2S[32,32] * tmp1;
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.195 MLA (by element) page C7-1846 line 103549 MATCH x2f000000/mask=xbf00f400
# CONSTRUCT x2f400000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $* &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2
# AUNIT --inst x2f400000/mask=xffc0f400 --status pass
:mla Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x0 & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPD1 = Rn_VPR64.4H * tmp1 on lane size 2
TMPD1[0,16] = Rn_VPR64.4H[0,16] * tmp1;
TMPD1[16,16] = Rn_VPR64.4H[16,16] * tmp1;
TMPD1[32,16] = Rn_VPR64.4H[32,16] * tmp1;
TMPD1[48,16] = Rn_VPR64.4H[48,16] * tmp1;
# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.195 MLA (by element) page C7-1846 line 103549 MATCH x2f000000/mask=xbf00f400
# CONSTRUCT x6f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $* &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4
# AUNIT --inst x6f800000/mask=xffc0f400 --status pass
:mla Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x0 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix TMPQ1 = Rn_VPR128.4S * tmp1 on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] * tmp1;
TMPQ1[32,32] = Rn_VPR128.4S[32,32] * tmp1;
TMPQ1[64,32] = Rn_VPR128.4S[64,32] * tmp1;
TMPQ1[96,32] = Rn_VPR128.4S[96,32] * tmp1;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.195 MLA (by element) page C7-1846 line 103549 MATCH x2f000000/mask=xbf00f400
# CONSTRUCT x6f400000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $* &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2
# AUNIT --inst x6f400000/mask=xffc0f400 --status pass
:mla Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x0 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPQ1 = Rn_VPR128.8H * tmp1 on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] * tmp1;
TMPQ1[16,16] = Rn_VPR128.8H[16,16] * tmp1;
TMPQ1[32,16] = Rn_VPR128.8H[32,16] * tmp1;
TMPQ1[48,16] = Rn_VPR128.8H[48,16] * tmp1;
TMPQ1[64,16] = Rn_VPR128.8H[64,16] * tmp1;
TMPQ1[80,16] = Rn_VPR128.8H[80,16] * tmp1;
TMPQ1[96,16] = Rn_VPR128.8H[96,16] * tmp1;
TMPQ1[112,16] = Rn_VPR128.8H[112,16] * tmp1;
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.196 MLA (vector) page C7-1848 line 103681 MATCH x0e209400/mask=xbf20fc00
# CONSTRUCT x4e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $*@1 &=$+@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@1
# AUNIT --inst x4e209400/mask=xffe0fc00 --status pass
:mla Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x12 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix TMPQ1 = Rn_VPR128.16B * Rm_VPR128.16B on lane size 1
TMPQ1[0,8] = Rn_VPR128.16B[0,8] * Rm_VPR128.16B[0,8];
TMPQ1[8,8] = Rn_VPR128.16B[8,8] * Rm_VPR128.16B[8,8];
TMPQ1[16,8] = Rn_VPR128.16B[16,8] * Rm_VPR128.16B[16,8];
TMPQ1[24,8] = Rn_VPR128.16B[24,8] * Rm_VPR128.16B[24,8];
TMPQ1[32,8] = Rn_VPR128.16B[32,8] * Rm_VPR128.16B[32,8];
TMPQ1[40,8] = Rn_VPR128.16B[40,8] * Rm_VPR128.16B[40,8];
TMPQ1[48,8] = Rn_VPR128.16B[48,8] * Rm_VPR128.16B[48,8];
TMPQ1[56,8] = Rn_VPR128.16B[56,8] * Rm_VPR128.16B[56,8];
TMPQ1[64,8] = Rn_VPR128.16B[64,8] * Rm_VPR128.16B[64,8];
TMPQ1[72,8] = Rn_VPR128.16B[72,8] * Rm_VPR128.16B[72,8];
TMPQ1[80,8] = Rn_VPR128.16B[80,8] * Rm_VPR128.16B[80,8];
TMPQ1[88,8] = Rn_VPR128.16B[88,8] * Rm_VPR128.16B[88,8];
TMPQ1[96,8] = Rn_VPR128.16B[96,8] * Rm_VPR128.16B[96,8];
TMPQ1[104,8] = Rn_VPR128.16B[104,8] * Rm_VPR128.16B[104,8];
TMPQ1[112,8] = Rn_VPR128.16B[112,8] * Rm_VPR128.16B[112,8];
TMPQ1[120,8] = Rn_VPR128.16B[120,8] * Rm_VPR128.16B[120,8];
# simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1
Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];
Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];
Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];
Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];
Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];
Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];
Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];
Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];
Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];
Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];
Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];
Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];
Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];
Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];
Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];
Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.196 MLA (vector) page C7-1848 line 103681 MATCH x0e209400/mask=xbf20fc00
# CONSTRUCT x0ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $*@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4
# AUNIT --inst x0ea09400/mask=xffe0fc00 --status pass
:mla Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x12 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix TMPD1 = Rn_VPR64.2S * Rm_VPR64.2S on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] * Rm_VPR64.2S[0,32];
TMPD1[32,32] = Rn_VPR64.2S[32,32] * Rm_VPR64.2S[32,32];
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.196 MLA (vector) page C7-1848 line 103681 MATCH x0e209400/mask=xbf20fc00
# CONSTRUCT x0e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $*@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2
# AUNIT --inst x0e609400/mask=xffe0fc00 --status pass
:mla Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x12 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd infix TMPD1 = Rn_VPR64.4H * Rm_VPR64.4H on lane size 2
TMPD1[0,16] = Rn_VPR64.4H[0,16] * Rm_VPR64.4H[0,16];
TMPD1[16,16] = Rn_VPR64.4H[16,16] * Rm_VPR64.4H[16,16];
TMPD1[32,16] = Rn_VPR64.4H[32,16] * Rm_VPR64.4H[32,16];
TMPD1[48,16] = Rn_VPR64.4H[48,16] * Rm_VPR64.4H[48,16];
# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.196 MLA (vector) page C7-1848 line 103681 MATCH x0e209400/mask=xbf20fc00
# CONSTRUCT x4ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $*@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4
# AUNIT --inst x4ea09400/mask=xffe0fc00 --status pass
:mla Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S * Rm_VPR128.4S on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] * Rm_VPR128.4S[0,32];
TMPQ1[32,32] = Rn_VPR128.4S[32,32] * Rm_VPR128.4S[32,32];
TMPQ1[64,32] = Rn_VPR128.4S[64,32] * Rm_VPR128.4S[64,32];
TMPQ1[96,32] = Rn_VPR128.4S[96,32] * Rm_VPR128.4S[96,32];
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.196 MLA (vector) page C7-1848 line 103681 MATCH x0e209400/mask=xbf20fc00
# CONSTRUCT x0e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $*@1 &=$+@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@1
# AUNIT --inst x0e209400/mask=xffe0fc00 --status pass
:mla Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x12 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix TMPD1 = Rn_VPR64.8B * Rm_VPR64.8B on lane size 1
TMPD1[0,8] = Rn_VPR64.8B[0,8] * Rm_VPR64.8B[0,8];
TMPD1[8,8] = Rn_VPR64.8B[8,8] * Rm_VPR64.8B[8,8];
TMPD1[16,8] = Rn_VPR64.8B[16,8] * Rm_VPR64.8B[16,8];
TMPD1[24,8] = Rn_VPR64.8B[24,8] * Rm_VPR64.8B[24,8];
TMPD1[32,8] = Rn_VPR64.8B[32,8] * Rm_VPR64.8B[32,8];
TMPD1[40,8] = Rn_VPR64.8B[40,8] * Rm_VPR64.8B[40,8];
TMPD1[48,8] = Rn_VPR64.8B[48,8] * Rm_VPR64.8B[48,8];
TMPD1[56,8] = Rn_VPR64.8B[56,8] * Rm_VPR64.8B[56,8];
# simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1
Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];
Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];
Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];
Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];
Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];
Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];
Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];
Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.196 MLA (vector) page C7-1848 line 103681 MATCH x0e209400/mask=xbf20fc00
# CONSTRUCT x4e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $*@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2
# AUNIT --inst x4e609400/mask=xffe0fc00 --status pass
:mla Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H * Rm_VPR128.8H on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] * Rm_VPR128.8H[0,16];
TMPQ1[16,16] = Rn_VPR128.8H[16,16] * Rm_VPR128.8H[16,16];
TMPQ1[32,16] = Rn_VPR128.8H[32,16] * Rm_VPR128.8H[32,16];
TMPQ1[48,16] = Rn_VPR128.8H[48,16] * Rm_VPR128.8H[48,16];
TMPQ1[64,16] = Rn_VPR128.8H[64,16] * Rm_VPR128.8H[64,16];
TMPQ1[80,16] = Rn_VPR128.8H[80,16] * Rm_VPR128.8H[80,16];
TMPQ1[96,16] = Rn_VPR128.8H[96,16] * Rm_VPR128.8H[96,16];
TMPQ1[112,16] = Rn_VPR128.8H[112,16] * Rm_VPR128.8H[112,16];
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.197 MLS (by element) page C7-1850 line 103784 MATCH x2f004000/mask=xbf00f400
# CONSTRUCT x2f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $* &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4
# AUNIT --inst x2f804000/mask=xffc0f400 --status pass
:mls Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x4 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix TMPD1 = Rn_VPR64.2S * tmp1 on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] * tmp1;
TMPD1[32,32] = Rn_VPR64.2S[32,32] * tmp1;
# simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.197 MLS (by element) page C7-1850 line 103784 MATCH x2f004000/mask=xbf00f400
# CONSTRUCT x2f404000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $* &=$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2
# AUNIT --inst x2f404000/mask=xffc0f400 --status pass
:mls Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x4 & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPD1 = Rn_VPR64.4H * tmp1 on lane size 2
TMPD1[0,16] = Rn_VPR64.4H[0,16] * tmp1;
TMPD1[16,16] = Rn_VPR64.4H[16,16] * tmp1;
TMPD1[32,16] = Rn_VPR64.4H[32,16] * tmp1;
TMPD1[48,16] = Rn_VPR64.4H[48,16] * tmp1;
# simd infix Rd_VPR64.4H = Rd_VPR64.4H - TMPD1 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] - TMPD1[0,16];
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] - TMPD1[16,16];
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] - TMPD1[32,16];
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] - TMPD1[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.197 MLS (by element) page C7-1850 line 103784 MATCH x2f004000/mask=xbf00f400
# CONSTRUCT x6f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $* &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4
# AUNIT --inst x6f804000/mask=xffc0f400 --status pass
:mls Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x4 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix TMPQ1 = Rn_VPR128.4S * tmp1 on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] * tmp1;
TMPQ1[32,32] = Rn_VPR128.4S[32,32] * tmp1;
TMPQ1[64,32] = Rn_VPR128.4S[64,32] * tmp1;
TMPQ1[96,32] = Rn_VPR128.4S[96,32] * tmp1;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.197 MLS (by element) page C7-1850 line 103784 MATCH x2f004000/mask=xbf00f400
# CONSTRUCT x6f404000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $* &=$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2
# AUNIT --inst x6f404000/mask=xffc0f400 --status pass
:mls Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x4 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix TMPQ1 = Rn_VPR128.8H * tmp1 on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] * tmp1;
TMPQ1[16,16] = Rn_VPR128.8H[16,16] * tmp1;
TMPQ1[32,16] = Rn_VPR128.8H[32,16] * tmp1;
TMPQ1[48,16] = Rn_VPR128.8H[48,16] * tmp1;
TMPQ1[64,16] = Rn_VPR128.8H[64,16] * tmp1;
TMPQ1[80,16] = Rn_VPR128.8H[80,16] * tmp1;
TMPQ1[96,16] = Rn_VPR128.8H[96,16] * tmp1;
TMPQ1[112,16] = Rn_VPR128.8H[112,16] * tmp1;
# simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.198 MLS (vector) page C7-1852 line 103916 MATCH x2e209400/mask=xbf20fc00
# CONSTRUCT x6e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $*@1 &=$-@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@1
# AUNIT --inst x6e209400/mask=xffe0fc00 --status pass
:mls Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x12 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix TMPQ1 = Rn_VPR128.16B * Rm_VPR128.16B on lane size 1
TMPQ1[0,8] = Rn_VPR128.16B[0,8] * Rm_VPR128.16B[0,8];
TMPQ1[8,8] = Rn_VPR128.16B[8,8] * Rm_VPR128.16B[8,8];
TMPQ1[16,8] = Rn_VPR128.16B[16,8] * Rm_VPR128.16B[16,8];
TMPQ1[24,8] = Rn_VPR128.16B[24,8] * Rm_VPR128.16B[24,8];
TMPQ1[32,8] = Rn_VPR128.16B[32,8] * Rm_VPR128.16B[32,8];
TMPQ1[40,8] = Rn_VPR128.16B[40,8] * Rm_VPR128.16B[40,8];
TMPQ1[48,8] = Rn_VPR128.16B[48,8] * Rm_VPR128.16B[48,8];
TMPQ1[56,8] = Rn_VPR128.16B[56,8] * Rm_VPR128.16B[56,8];
TMPQ1[64,8] = Rn_VPR128.16B[64,8] * Rm_VPR128.16B[64,8];
TMPQ1[72,8] = Rn_VPR128.16B[72,8] * Rm_VPR128.16B[72,8];
TMPQ1[80,8] = Rn_VPR128.16B[80,8] * Rm_VPR128.16B[80,8];
TMPQ1[88,8] = Rn_VPR128.16B[88,8] * Rm_VPR128.16B[88,8];
TMPQ1[96,8] = Rn_VPR128.16B[96,8] * Rm_VPR128.16B[96,8];
TMPQ1[104,8] = Rn_VPR128.16B[104,8] * Rm_VPR128.16B[104,8];
TMPQ1[112,8] = Rn_VPR128.16B[112,8] * Rm_VPR128.16B[112,8];
TMPQ1[120,8] = Rn_VPR128.16B[120,8] * Rm_VPR128.16B[120,8];
# simd infix Rd_VPR128.16B = Rd_VPR128.16B - TMPQ1 on lane size 1
Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] - TMPQ1[0,8];
Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] - TMPQ1[8,8];
Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] - TMPQ1[16,8];
Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] - TMPQ1[24,8];
Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] - TMPQ1[32,8];
Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] - TMPQ1[40,8];
Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] - TMPQ1[48,8];
Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] - TMPQ1[56,8];
Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] - TMPQ1[64,8];
Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] - TMPQ1[72,8];
Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] - TMPQ1[80,8];
Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] - TMPQ1[88,8];
Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] - TMPQ1[96,8];
Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] - TMPQ1[104,8];
Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] - TMPQ1[112,8];
Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] - TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.198 MLS (vector) page C7-1852 line 103916 MATCH x2e209400/mask=xbf20fc00
# CONSTRUCT x2ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $*@4 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4
# AUNIT --inst x2ea09400/mask=xffe0fc00 --status pass
:mls Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x12 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix TMPD1 = Rn_VPR64.2S * Rm_VPR64.2S on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] * Rm_VPR64.2S[0,32];
TMPD1[32,32] = Rn_VPR64.2S[32,32] * Rm_VPR64.2S[32,32];
# simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.198 MLS (vector) page C7-1852 line 103916 MATCH x2e209400/mask=xbf20fc00
# CONSTRUCT x2e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $*@2 &=$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2
# AUNIT --inst x2e609400/mask=xffe0fc00 --status pass
:mls Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x12 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd infix TMPD1 = Rn_VPR64.4H * Rm_VPR64.4H on lane size 2
TMPD1[0,16] = Rn_VPR64.4H[0,16] * Rm_VPR64.4H[0,16];
TMPD1[16,16] = Rn_VPR64.4H[16,16] * Rm_VPR64.4H[16,16];
TMPD1[32,16] = Rn_VPR64.4H[32,16] * Rm_VPR64.4H[32,16];
TMPD1[48,16] = Rn_VPR64.4H[48,16] * Rm_VPR64.4H[48,16];
# simd infix Rd_VPR64.4H = Rd_VPR64.4H - TMPD1 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] - TMPD1[0,16];
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] - TMPD1[16,16];
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] - TMPD1[32,16];
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] - TMPD1[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.198 MLS (vector) page C7-1852 line 103916 MATCH x2e209400/mask=xbf20fc00
# CONSTRUCT x6ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $*@4 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4
# AUNIT --inst x6ea09400/mask=xffe0fc00 --status pass
:mls Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S * Rm_VPR128.4S on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] * Rm_VPR128.4S[0,32];
TMPQ1[32,32] = Rn_VPR128.4S[32,32] * Rm_VPR128.4S[32,32];
TMPQ1[64,32] = Rn_VPR128.4S[64,32] * Rm_VPR128.4S[64,32];
TMPQ1[96,32] = Rn_VPR128.4S[96,32] * Rm_VPR128.4S[96,32];
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.198 MLS (vector) page C7-1852 line 103916 MATCH x2e209400/mask=xbf20fc00
# CONSTRUCT x2e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $*@1 &=$-@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@1
# AUNIT --inst x2e209400/mask=xffe0fc00 --status pass
:mls Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x12 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix TMPD1 = Rn_VPR64.8B * Rm_VPR64.8B on lane size 1
TMPD1[0,8] = Rn_VPR64.8B[0,8] * Rm_VPR64.8B[0,8];
TMPD1[8,8] = Rn_VPR64.8B[8,8] * Rm_VPR64.8B[8,8];
TMPD1[16,8] = Rn_VPR64.8B[16,8] * Rm_VPR64.8B[16,8];
TMPD1[24,8] = Rn_VPR64.8B[24,8] * Rm_VPR64.8B[24,8];
TMPD1[32,8] = Rn_VPR64.8B[32,8] * Rm_VPR64.8B[32,8];
TMPD1[40,8] = Rn_VPR64.8B[40,8] * Rm_VPR64.8B[40,8];
TMPD1[48,8] = Rn_VPR64.8B[48,8] * Rm_VPR64.8B[48,8];
TMPD1[56,8] = Rn_VPR64.8B[56,8] * Rm_VPR64.8B[56,8];
# simd infix Rd_VPR64.8B = Rd_VPR64.8B - TMPD1 on lane size 1
Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] - TMPD1[0,8];
Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] - TMPD1[8,8];
Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] - TMPD1[16,8];
Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] - TMPD1[24,8];
Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] - TMPD1[32,8];
Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] - TMPD1[40,8];
Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] - TMPD1[48,8];
Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] - TMPD1[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.198 MLS (vector) page C7-1852 line 103916 MATCH x2e209400/mask=xbf20fc00
# CONSTRUCT x6e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $*@2 &=$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2
# AUNIT --inst x6e609400/mask=xffe0fc00 --status pass
:mls Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H * Rm_VPR128.8H on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] * Rm_VPR128.8H[0,16];
TMPQ1[16,16] = Rn_VPR128.8H[16,16] * Rm_VPR128.8H[16,16];
TMPQ1[32,16] = Rn_VPR128.8H[32,16] * Rm_VPR128.8H[32,16];
TMPQ1[48,16] = Rn_VPR128.8H[48,16] * Rm_VPR128.8H[48,16];
TMPQ1[64,16] = Rn_VPR128.8H[64,16] * Rm_VPR128.8H[64,16];
TMPQ1[80,16] = Rn_VPR128.8H[80,16] * Rm_VPR128.8H[80,16];
TMPQ1[96,16] = Rn_VPR128.8H[96,16] * Rm_VPR128.8H[96,16];
TMPQ1[112,16] = Rn_VPR128.8H[112,16] * Rm_VPR128.8H[112,16];
# simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.200 MOV (element) page C7-1856 line 104111 MATCH x6e000400/mask=xffe08400
# C7.2.175 INS (element) page C7-1784 line 99692 MATCH x6e000400/mask=xffe08400
# CONSTRUCT x6e010400/mask=xffe18400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO Rd_VPR128 ARG2 imm_neon_uimm4:1 &=$copy
# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm4:1 &=NEON_mov/3@1
# AUNIT --inst x6e010400/mask=xffe18400 --status pass
:mov Rd_VPR128.B.imm_neon_uimm4, Rn_VPR128.B.immN_neon_uimm4
is b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & Rn_VPR128.B.immN_neon_uimm4 & immN_neon_uimm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd
{
# simd element Rn_VPR128[immN_neon_uimm4] lane size 1
local tmp1:1 = Rn_VPR128.B.immN_neon_uimm4;
# simd copy Rd_VPR128 element imm_neon_uimm4:1 = tmp1 (lane size 1)
Rd_VPR128.B.imm_neon_uimm4 = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.200 MOV (element) page C7-1856 line 104111 MATCH x6e000400/mask=xffe08400
# C7.2.175 INS (element) page C7-1784 line 99692 MATCH x6e000400/mask=xffe08400
# CONSTRUCT x6e080400/mask=xffef8400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO Rd_VPR128 ARG2 imm_neon_uimm1:1 &=$copy
# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm1:1 &=NEON_mov/3@8
# AUNIT --inst x6e080400/mask=xffef8400 --status pass
:mov Rd_VPR128.D.imm_neon_uimm1, Rn_VPR128.D.immN_neon_uimm1
is b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & Rn_VPR128.D.immN_neon_uimm1 & immN_neon_uimm1 & Imm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd
{
# simd element Rn_VPR128[immN_neon_uimm1] lane size 8
local tmp1:8 = Rn_VPR128.D.immN_neon_uimm1;
# simd copy Rd_VPR128 element imm_neon_uimm1:1 = tmp1 (lane size 8)
Rd_VPR128.D.imm_neon_uimm1 = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.200 MOV (element) page C7-1856 line 104111 MATCH x6e000400/mask=xffe08400
# C7.2.175 INS (element) page C7-1784 line 99692 MATCH x6e000400/mask=xffe08400
# CONSTRUCT x6e020400/mask=xffe38400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO Rd_VPR128 ARG2 imm_neon_uimm3:1 &=$copy
# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm3:1 &=NEON_mov/3@2
# AUNIT --inst x6e020400/mask=xffe38400 --status pass
:mov Rd_VPR128.H.imm_neon_uimm3, Rn_VPR128.H.immN_neon_uimm3
is b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & Rn_VPR128.H.immN_neon_uimm3 & immN_neon_uimm3 & Imm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd
{
# simd element Rn_VPR128[immN_neon_uimm3] lane size 2
local tmp1:2 = Rn_VPR128.H.immN_neon_uimm3;
# simd copy Rd_VPR128 element imm_neon_uimm3:1 = tmp1 (lane size 2)
Rd_VPR128.H.imm_neon_uimm3 = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.200 MOV (element) page C7-1856 line 104111 MATCH x6e000400/mask=xffe08400
# C7.2.175 INS (element) page C7-1784 line 99692 MATCH x6e000400/mask=xffe08400
# CONSTRUCT x6e040400/mask=xffe78400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO Rd_VPR128 ARG2 imm_neon_uimm2:1 &=$copy
# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm2:1 &=NEON_mov/3@4
# AUNIT --inst x6e040400/mask=xffe78400 --status pass
:mov Rd_VPR128.S.imm_neon_uimm2, Rn_VPR128.S.immN_neon_uimm2
is b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & Rn_VPR128.S.immN_neon_uimm2 & immN_neon_uimm2 & Imm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd
{
# simd element Rn_VPR128[immN_neon_uimm2] lane size 4
local tmp1:4 = Rn_VPR128.S.immN_neon_uimm2;
# simd copy Rd_VPR128 element imm_neon_uimm2:1 = tmp1 (lane size 4)
Rd_VPR128.S.imm_neon_uimm2 = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.201 MOV (from general) page C7-1858 line 104209 MATCH x4e001c00/mask=xffe0fc00
# C7.2.176 INS (general) page C7-1786 line 99801 MATCH x4e001c00/mask=xffe0fc00
# CONSTRUCT x4e011c00/mask=xffe1fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO Rd_VPR128 ARG2[0]:1 imm_neon_uimm4:1 &=$copy
# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm4:1 &=NEON_mov/3@1
# AUNIT --inst x4e011c00/mask=xffe1fc00 --status pass
:mov Rd_VPR128.B.imm_neon_uimm4, Rn_GPR32
is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR32 & Rd_VPR128 & Zd
{
local tmp1:1 = Rn_GPR32[0,8];
# simd copy Rd_VPR128 element imm_neon_uimm4:1 = tmp1 (lane size 1)
Rd_VPR128.B.imm_neon_uimm4 = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.201 MOV (from general) page C7-1858 line 104209 MATCH x4e001c00/mask=xffe0fc00
# C7.2.176 INS (general) page C7-1786 line 99801 MATCH x4e001c00/mask=xffe0fc00
# CONSTRUCT x4e081c00/mask=xffeffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO Rd_VPR128 ARG2 imm_neon_uimm1:1 &=$copy
# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm1:1 &=NEON_mov/3@8
# AUNIT --inst x4e081c00/mask=xffeffc00 --status pass
:mov Rd_VPR128.D.imm_neon_uimm1, Rn_GPR64
is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR64 & Rd_VPR128 & Zd
{
# simd copy Rd_VPR128 element imm_neon_uimm1:1 = Rn_GPR64 (lane size 8)
Rd_VPR128.D.imm_neon_uimm1 = Rn_GPR64;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.201 MOV (from general) page C7-1858 line 104209 MATCH x4e001c00/mask=xffe0fc00
# C7.2.176 INS (general) page C7-1786 line 99801 MATCH x4e001c00/mask=xffe0fc00
# CONSTRUCT x4e021c00/mask=xffe3fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO Rd_VPR128 ARG2[0]:2 imm_neon_uimm3:1 &=$copy
# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm3:1 &=NEON_mov/3@2
# AUNIT --inst x4e021c00/mask=xffe3fc00 --status pass
:mov Rd_VPR128.H.imm_neon_uimm3, Rn_GPR32
is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR32 & Rd_VPR128 & Zd
{
local tmp1:2 = Rn_GPR32[0,16];
# simd copy Rd_VPR128 element imm_neon_uimm3:1 = tmp1 (lane size 2)
Rd_VPR128.H.imm_neon_uimm3 = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.201 MOV (from general) page C7-1858 line 104209 MATCH x4e001c00/mask=xffe0fc00
# C7.2.176 INS (general) page C7-1786 line 99801 MATCH x4e001c00/mask=xffe0fc00
# CONSTRUCT x4e041c00/mask=xffe7fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO(force-primitive) Rd_VPR128 ARG2 imm_neon_uimm2:1 &=$copy
# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm2:1 &=NEON_mov/3@2
# AUNIT --inst x4e041c00/mask=xffe7fc00 --status pass
:mov Rd_VPR128.S.imm_neon_uimm2, Rn_GPR32
is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR32 & Rd_VPR128 & Zd
{
# simd copy Rd_VPR128 element imm_neon_uimm2:1 = Rn_GPR32 (lane size 4)
Rd_VPR128.S.imm_neon_uimm2 = Rn_GPR32;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.202 MOV (vector) page C7-1860 line 104306 MATCH x0ea01c00/mask=xbfe0fc00
# C7.2.213 ORR (vector, register) page C7-1882 line 105515 MATCH x0ea01c00/mask=xbfe0fc00
# CONSTRUCT x4ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@1
# AUNIT --inst x4ea01c00/mask=xffe0fc00 --status pass
:mov Rd_VPR128.16B, Rn_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Rn=Rm & Zd
{
Rd_VPR128.16B = Rn_VPR128.16B;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.202 MOV (vector) page C7-1860 line 104306 MATCH x0ea01c00/mask=xbfe0fc00
# C7.2.213 ORR (vector, register) page C7-1882 line 105515 MATCH x0ea01c00/mask=xbfe0fc00
# CONSTRUCT x0ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@1
# AUNIT --inst x0ea01c00/mask=xffe0fc00 --status pass
:mov Rd_VPR64.8B, Rn_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Rn=Rm & Zd
{
Rd_VPR64.8B = Rn_VPR64.8B;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.203 MOV (to general) page C7-1861 line 104373 MATCH x0e003c00/mask=xbfe3fc00
# C7.2.371 UMOV page C7-2236 line 125692 MATCH x0e003c00/mask=xbfe0fc00
# CONSTRUCT x0e043c00/mask=xffe7fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO(force-primitive) ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@4
# AUNIT --inst x0e043c00/mask=xffe7fc00 --status pass
:mov Rd_GPR32, Rn_VPR128.S.imm_neon_uimm2
is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64 & Rd_VPR128
{
# simd element Rn_VPR128[imm_neon_uimm2] lane size 4
local tmp1:4 = Rn_VPR128.S.imm_neon_uimm2;
Rd_GPR32 = tmp1;
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.203 MOV (to general) page C7-1861 line 104373 MATCH x0e003c00/mask=xbfe3fc00
# C7.2.371 UMOV page C7-2236 line 125692 MATCH x0e003c00/mask=xbfe0fc00
# CONSTRUCT x4e083c00/mask=xffeffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@8
# AUNIT --inst x4e083c00/mask=xffeffc00 --status pass
:mov Rd_GPR64, Rn_VPR128.D.imm_neon_uimm1
is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR64
{
# simd element Rn_VPR128[imm_neon_uimm1] lane size 8
local tmp1:8 = Rn_VPR128.D.imm_neon_uimm1;
Rd_GPR64 = tmp1;
}
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# C7.2.352 UCVTF (vector, fixed-point) page C7-2195 line 123484 MATCH x2f00e400/mask=xbf80fc00
# CONSTRUCT x2f00e400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1
# AUNIT --inst x2f00e400/mask=xfff8fc00 --status pass
# MOVI 64-bit scalar variant when datasize=64 q == 0 && op == 1 && cmode == 1110
:movi Rd_FPR64, Imm_neon_uimm8Shift
is b_31=0 & b_30=0 & b_29=1 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_FPR64 & Zd
{
Rd_FPR64 = Imm_neon_uimm8Shift:8;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.233 SCVTF (vector, fixed-point) page C7-1921 line 107690 MATCH x0f00e400/mask=xbf80fc00
# CONSTRUCT x4f00e400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:1 &=$dup
# SMACRO(pseudo) ARG1 ARG2:1 =NEON_movi/1@1
# AUNIT --inst x4f00e400/mask=xfff8fc00 --status pass
# MOVI 8-bit variant when datasize=128 q == 1 && op == 0 && cmode == 0b1110
:movi Rd_VPR128.16B, Imm_neon_uimm8Shift
is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.16B & Zd
{
# simd duplicate Rd_VPR128.16B = all elements Imm_neon_uimm8Shift:1 (lane size 1)
Rd_VPR128.16B[0,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[8,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[16,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[24,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[32,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[40,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[48,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[56,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[64,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[72,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[80,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[88,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[96,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[104,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[112,8] = Imm_neon_uimm8Shift:1;
Rd_VPR128.16B[120,8] = Imm_neon_uimm8Shift:1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# C7.2.352 UCVTF (vector, fixed-point) page C7-2195 line 123484 MATCH x2f00e400/mask=xbf80fc00
# CONSTRUCT x6f00e400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES
# SMACRO(force-primitive) ARG1 ARG2 =var:8 &=$dup
# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@8
# AUNIT --inst x6f00e400/mask=xfff8fc00 --status pass
# MOVI 64-bit vector variant when datasize=128 q == 1 && op == 1 && cmode == 1110
:movi Rd_VPR128.2D, Imm_neon_uimm8Shift
is b_31=0 & b_30=1 & b_29=1 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.2D & Zd
{
local tmp1:8 = Imm_neon_uimm8Shift;
# simd duplicate Rd_VPR128.2D = all elements tmp1 (lane size 8)
Rd_VPR128.2D[0,64] = tmp1;
Rd_VPR128.2D[64,64] = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.233 SCVTF (vector, fixed-point) page C7-1921 line 107690 MATCH x0f00e400/mask=xbf80fc00
# CONSTRUCT x0f00e400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@1
# AUNIT --inst x0f00e400/mask=xfff8fc00 --status pass
# MOVI 8-bit variant when datasize=64 q == 0 && op == 0 && cmode == 1110
:movi Rd_VPR64.8B, Imm_neon_uimm8Shift
is b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = Imm_neon_uimm8Shift:8;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.313 SRSHR page C7-2097 line 117624 MATCH x0f002400/mask=xbf80fc00
# C7.2.317 SSHR page C7-2106 line 118183 MATCH x0f000400/mask=xbf80fc00
# CONSTRUCT x0f000400/mask=xfff89c00 MATCHED 3 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@4
# AUNIT --inst x0f000400/mask=xfff89c00 --status pass
# MOVI 32-bit shifted immediate variant when datasize=64 q == 0 && op == 0 && cmode == 0xx0
:movi Rd_VPR64.2S, Imm_neon_uimm8Shift
is b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_15=0 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = Imm_neon_uimm8Shift:8;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.256 SHRN, SHRN2 page C7-1959 line 109821 MATCH x0f008400/mask=xbf80fc00
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# CONSTRUCT x0f008400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@2
# AUNIT --inst x0f008400/mask=xfff8dc00 --status pass
# MOVI 16-bit shifted immediate variant when datasize=64 q == 0 && op == 0 && cmode == 10x0
:movi Rd_VPR64.4H, Imm_neon_uimm8Shift
is b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_1415=0b10 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = Imm_neon_uimm8Shift:8;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.313 SRSHR page C7-2097 line 117624 MATCH x0f002400/mask=xbf80fc00
# C7.2.317 SSHR page C7-2106 line 118183 MATCH x0f000400/mask=xbf80fc00
# CONSTRUCT x4f000400/mask=xfff89c00 MATCHED 3 DOCUMENTED OPCODES
# SMACRO(force-primitive) ARG1 ARG2:4 &=$dup
# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@4
# AUNIT --inst x4f000400/mask=xfff89c00 --status pass
# MOVI 32-bit shifted immediate variant when datasize=128 q == 1 && op == 0 && cmode == 0xx0
:movi Rd_VPR128.4S, Imm_neon_uimm8Shift
is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_15=0 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.4S & Zd
{
# simd duplicate Rd_VPR128.4S = all elements Imm_neon_uimm8Shift:4 (lane size 4)
Rd_VPR128.4S[0,32] = Imm_neon_uimm8Shift:4;
Rd_VPR128.4S[32,32] = Imm_neon_uimm8Shift:4;
Rd_VPR128.4S[64,32] = Imm_neon_uimm8Shift:4;
Rd_VPR128.4S[96,32] = Imm_neon_uimm8Shift:4;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.256 SHRN, SHRN2 page C7-1959 line 109821 MATCH x0f008400/mask=xbf80fc00
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# CONSTRUCT x4f008400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:2 &=$dup
# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@2
# AUNIT --inst x4f008400/mask=xfff8dc00 --status pass
# MOVI 16-bit shifted immediate variant when datasize=128 q == 1 && op == 0 && cmode == 10x0
:movi Rd_VPR128.8H, Imm_neon_uimm8Shift
is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_1415=0b10 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.8H & Zd
{
# simd duplicate Rd_VPR128.8H = all elements Imm_neon_uimm8Shift:2 (lane size 2)
Rd_VPR128.8H[0,16] = Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[16,16] = Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[32,16] = Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[48,16] = Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[64,16] = Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[80,16] = Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[96,16] = Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[112,16] = Imm_neon_uimm8Shift:2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.212 ORR (vector, immediate) page C7-1880 line 105389 MATCH x0f001400/mask=xbff81c00
# CONSTRUCT x0f00c400/mask=xfff8ec00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =
# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@4
# AUNIT --inst x0f00c400/mask=xfff8ec00 --status pass
# MOVI 32-bit shifting ones variant when datasize=64 q == 0 && op == 0 && cmode == 110x
:movi Rd_VPR64.2S, Imm_neon_uimm8Shift
is b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_1315=0b110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = Imm_neon_uimm8Shift:8;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.212 ORR (vector, immediate) page C7-1880 line 105389 MATCH x0f001400/mask=xbff81c00
# CONSTRUCT x4f00c400/mask=xfff8ec00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:4 &=$dup
# SMACRO(pseudo) ARG1 ARG2:4 =NEON_movi/1@4
# AUNIT --inst x4f00c400/mask=xfff8ec00 --status pass
# MOVI 32-bit shifting ones variant when datasize=128 q == 1 && op == 0 && cmode == 110x
:movi Rd_VPR128.4S, Imm_neon_uimm8Shift
is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_1315=0b110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.4S & Zd
{
# simd duplicate Rd_VPR128.4S = all elements Imm_neon_uimm8Shift:4 (lane size 4)
Rd_VPR128.4S[0,32] = Imm_neon_uimm8Shift:4;
Rd_VPR128.4S[32,32] = Imm_neon_uimm8Shift:4;
Rd_VPR128.4S[64,32] = Imm_neon_uimm8Shift:4;
Rd_VPR128.4S[96,32] = Imm_neon_uimm8Shift:4;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.205 MUL (by element) page C7-1866 line 104646 MATCH x0f008000/mask=xbf00f400
# CONSTRUCT x0f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4
# AUNIT --inst x0f808000/mask=xffc0f400 --status pass
:mul Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x8 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix Rd_VPR64.2S = Rn_VPR64.2S * tmp1 on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] * tmp1;
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] * tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.205 MUL (by element) page C7-1866 line 104646 MATCH x0f008000/mask=xbf00f400
# CONSTRUCT x0f408000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2
# AUNIT --inst x0f408000/mask=xffc0f400 --status pass
:mul Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x8 & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix Rd_VPR64.4H = Rn_VPR64.4H * tmp1 on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] * tmp1;
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] * tmp1;
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] * tmp1;
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] * tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.205 MUL (by element) page C7-1866 line 104646 MATCH x0f008000/mask=xbf00f400
# CONSTRUCT x4f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4
# AUNIT --inst x4f808000/mask=xffc0f400 --status pass
:mul Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x8 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp1:4 = Re_VPR128.S.vIndex;
# simd infix Rd_VPR128.4S = Rn_VPR128.4S * tmp1 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] * tmp1;
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] * tmp1;
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] * tmp1;
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] * tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.205 MUL (by element) page C7-1866 line 104646 MATCH x0f008000/mask=xbf00f400
# CONSTRUCT x4f408000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2
# AUNIT --inst x4f408000/mask=xffc0f400 --status pass
:mul Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x8 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
# simd infix Rd_VPR128.8H = Rn_VPR128.8H * tmp1 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] * tmp1;
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] * tmp1;
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] * tmp1;
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] * tmp1;
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] * tmp1;
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] * tmp1;
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] * tmp1;
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] * tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.206 MUL (vector) page C7-1868 line 104774 MATCH x0e209c00/mask=xbf20fc00
# CONSTRUCT x4e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$*@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@1
# AUNIT --inst x4e209c00/mask=xffe0fc00 --status pass
:mul Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x13 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix Rd_VPR128.16B = Rn_VPR128.16B * Rm_VPR128.16B on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] * Rm_VPR128.16B[0,8];
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] * Rm_VPR128.16B[8,8];
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] * Rm_VPR128.16B[16,8];
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] * Rm_VPR128.16B[24,8];
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] * Rm_VPR128.16B[32,8];
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] * Rm_VPR128.16B[40,8];
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] * Rm_VPR128.16B[48,8];
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] * Rm_VPR128.16B[56,8];
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] * Rm_VPR128.16B[64,8];
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] * Rm_VPR128.16B[72,8];
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] * Rm_VPR128.16B[80,8];
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] * Rm_VPR128.16B[88,8];
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] * Rm_VPR128.16B[96,8];
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] * Rm_VPR128.16B[104,8];
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] * Rm_VPR128.16B[112,8];
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] * Rm_VPR128.16B[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.206 MUL (vector) page C7-1868 line 104774 MATCH x0e209c00/mask=xbf20fc00
# CONSTRUCT x0ea09c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$*@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4
# AUNIT --inst x0ea09c00/mask=xffe0fc00 --status pass
:mul Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x13 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix Rd_VPR64.2S = Rn_VPR64.2S * Rm_VPR64.2S on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] * Rm_VPR64.2S[0,32];
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] * Rm_VPR64.2S[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.206 MUL (vector) page C7-1868 line 104774 MATCH x0e209c00/mask=xbf20fc00
# CONSTRUCT x0e609c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$*@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2
# AUNIT --inst x0e609c00/mask=xffe0fc00 --status pass
:mul Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x13 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd infix Rd_VPR64.4H = Rn_VPR64.4H * Rm_VPR64.4H on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] * Rm_VPR64.4H[0,16];
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] * Rm_VPR64.4H[16,16];
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] * Rm_VPR64.4H[32,16];
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] * Rm_VPR64.4H[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.206 MUL (vector) page C7-1868 line 104774 MATCH x0e209c00/mask=xbf20fc00
# CONSTRUCT x4ea09c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$*@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4
# AUNIT --inst x4ea09c00/mask=xffe0fc00 --status pass
:mul Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd infix Rd_VPR128.4S = Rn_VPR128.4S * Rm_VPR128.4S on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] * Rm_VPR128.4S[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] * Rm_VPR128.4S[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] * Rm_VPR128.4S[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] * Rm_VPR128.4S[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.206 MUL (vector) page C7-1868 line 104774 MATCH x0e209c00/mask=xbf20fc00
# CONSTRUCT x0e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$*@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@1
# AUNIT --inst x0e209c00/mask=xffe0fc00 --status pass
:mul Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x13 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix Rd_VPR64.8B = Rn_VPR64.8B * Rm_VPR64.8B on lane size 1
Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] * Rm_VPR64.8B[0,8];
Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] * Rm_VPR64.8B[8,8];
Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] * Rm_VPR64.8B[16,8];
Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] * Rm_VPR64.8B[24,8];
Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] * Rm_VPR64.8B[32,8];
Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] * Rm_VPR64.8B[40,8];
Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] * Rm_VPR64.8B[48,8];
Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] * Rm_VPR64.8B[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.206 MUL (vector) page C7-1868 line 104774 MATCH x0e209c00/mask=xbf20fc00
# CONSTRUCT x4e609c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$*@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2
# AUNIT --inst x4e609c00/mask=xffe0fc00 --status pass
:mul Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd infix Rd_VPR128.8H = Rn_VPR128.8H * Rm_VPR128.8H on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] * Rm_VPR128.8H[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] * Rm_VPR128.8H[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] * Rm_VPR128.8H[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] * Rm_VPR128.8H[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] * Rm_VPR128.8H[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] * Rm_VPR128.8H[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] * Rm_VPR128.8H[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] * Rm_VPR128.8H[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.207 MVN page C7-1870 line 104876 MATCH x2e205800/mask=xbffffc00
# C7.2.210 NOT page C7-1876 line 105222 MATCH x2e205800/mask=xbffffc00
# CONSTRUCT x6e205800/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$~@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_mvn/1@1
# AUNIT --inst x6e205800/mask=xfffffc00 --status pass
:mvn Rd_VPR128.16B, Rn_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=16 & b_1216=5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd unary Rd_VPR128.16B = ~(Rn_VPR128.16B) on lane size 1
Rd_VPR128.16B[0,8] = ~(Rn_VPR128.16B[0,8]);
Rd_VPR128.16B[8,8] = ~(Rn_VPR128.16B[8,8]);
Rd_VPR128.16B[16,8] = ~(Rn_VPR128.16B[16,8]);
Rd_VPR128.16B[24,8] = ~(Rn_VPR128.16B[24,8]);
Rd_VPR128.16B[32,8] = ~(Rn_VPR128.16B[32,8]);
Rd_VPR128.16B[40,8] = ~(Rn_VPR128.16B[40,8]);
Rd_VPR128.16B[48,8] = ~(Rn_VPR128.16B[48,8]);
Rd_VPR128.16B[56,8] = ~(Rn_VPR128.16B[56,8]);
Rd_VPR128.16B[64,8] = ~(Rn_VPR128.16B[64,8]);
Rd_VPR128.16B[72,8] = ~(Rn_VPR128.16B[72,8]);
Rd_VPR128.16B[80,8] = ~(Rn_VPR128.16B[80,8]);
Rd_VPR128.16B[88,8] = ~(Rn_VPR128.16B[88,8]);
Rd_VPR128.16B[96,8] = ~(Rn_VPR128.16B[96,8]);
Rd_VPR128.16B[104,8] = ~(Rn_VPR128.16B[104,8]);
Rd_VPR128.16B[112,8] = ~(Rn_VPR128.16B[112,8]);
Rd_VPR128.16B[120,8] = ~(Rn_VPR128.16B[120,8]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.207 MVN page C7-1870 line 104876 MATCH x2e205800/mask=xbffffc00
# C7.2.210 NOT page C7-1876 line 105222 MATCH x2e205800/mask=xbffffc00
# CONSTRUCT x2e205800/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$~@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_mvn/1@1
# AUNIT --inst x2e205800/mask=xfffffc00 --status pass
:mvn Rd_VPR64.8B, Rn_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=16 & b_1216=5 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd unary Rd_VPR64.8B = ~(Rn_VPR64.8B) on lane size 1
Rd_VPR64.8B[0,8] = ~(Rn_VPR64.8B[0,8]);
Rd_VPR64.8B[8,8] = ~(Rn_VPR64.8B[8,8]);
Rd_VPR64.8B[16,8] = ~(Rn_VPR64.8B[16,8]);
Rd_VPR64.8B[24,8] = ~(Rn_VPR64.8B[24,8]);
Rd_VPR64.8B[32,8] = ~(Rn_VPR64.8B[32,8]);
Rd_VPR64.8B[40,8] = ~(Rn_VPR64.8B[40,8]);
Rd_VPR64.8B[48,8] = ~(Rn_VPR64.8B[48,8]);
Rd_VPR64.8B[56,8] = ~(Rn_VPR64.8B[56,8]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x2f006400/mask=xbf80fc00
# C7.2.311 SRI page C7-2092 line 117324 MATCH x2f004400/mask=xbf80fc00
# C7.2.385 URSHR page C7-2268 line 127587 MATCH x2f002400/mask=xbf80fc00
# C7.2.392 USHR page C7-2282 line 128386 MATCH x2f000400/mask=xbf80fc00
# CONSTRUCT x2f000400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:4 ~ &=$dup
# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4
# AUNIT --inst x2f000400/mask=xfff89c00 --status pass
:mvni Rd_VPR64.2S, Imm_neon_uimm8Shift
is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & b_1515=0 & Imm_neon_uimm8Shift & b_1012=1 & Rd_VPR64.2S & Zd
{
local tmp1:4 = ~ Imm_neon_uimm8Shift:4;
# simd duplicate Rd_VPR64.2S = all elements tmp1 (lane size 4)
Rd_VPR64.2S[0,32] = tmp1;
Rd_VPR64.2S[32,32] = tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2079 line 116627 MATCH x2f008400/mask=xbf80fc00
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# CONSTRUCT x2f008400/mask=xfff8dc00 MATCHED 5 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:2 ~ &=$dup
# SMACRO(pseudo) ARG1 ARG2:2 =NEON_mvni/1@2
# AUNIT --inst x2f008400/mask=xfff8dc00 --status pass
:mvni Rd_VPR64.4H, Imm_neon_uimm8Shift
is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=1 & Rd_VPR64.4H & Zd
{
local tmp1:2 = ~ Imm_neon_uimm8Shift:2;
# simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2)
Rd_VPR64.4H[0,16] = tmp1;
Rd_VPR64.4H[16,16] = tmp1;
Rd_VPR64.4H[32,16] = tmp1;
Rd_VPR64.4H[48,16] = tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x2f006400/mask=xbf80fc00
# C7.2.311 SRI page C7-2092 line 117324 MATCH x2f004400/mask=xbf80fc00
# C7.2.385 URSHR page C7-2268 line 127587 MATCH x2f002400/mask=xbf80fc00
# C7.2.392 USHR page C7-2282 line 128386 MATCH x2f000400/mask=xbf80fc00
# CONSTRUCT x6f000400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:4 ~ &=$dup
# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4
# AUNIT --inst x6f000400/mask=xfff89c00 --status pass
:mvni Rd_VPR128.4S, Imm_neon_uimm8Shift
is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1515=0 & b_1012=1 & Rd_VPR128.4S & Zd
{
local tmp1:4 = ~ Imm_neon_uimm8Shift:4;
# simd duplicate Rd_VPR128.4S = all elements tmp1 (lane size 4)
Rd_VPR128.4S[0,32] = tmp1;
Rd_VPR128.4S[32,32] = tmp1;
Rd_VPR128.4S[64,32] = tmp1;
Rd_VPR128.4S[96,32] = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2079 line 116627 MATCH x2f008400/mask=xbf80fc00
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# CONSTRUCT x6f008400/mask=xfff8dc00 MATCHED 5 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:2 ~ &=$dup
# SMACRO(pseudo) ARG1 ARG2:2 =NEON_mvni/1@2
# AUNIT --inst x6f008400/mask=xfff8dc00 --status pass
:mvni Rd_VPR128.8H, Imm_neon_uimm8Shift
is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=1 & Rd_VPR128.8H & Zd
{
local tmp1:2 = ~ Imm_neon_uimm8Shift:2;
# simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2)
Rd_VPR128.8H[0,16] = tmp1;
Rd_VPR128.8H[16,16] = tmp1;
Rd_VPR128.8H[32,16] = tmp1;
Rd_VPR128.8H[48,16] = tmp1;
Rd_VPR128.8H[64,16] = tmp1;
Rd_VPR128.8H[80,16] = tmp1;
Rd_VPR128.8H[96,16] = tmp1;
Rd_VPR128.8H[112,16] = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# C7.2.20 BIC (vector, immediate) page C7-1428 line 79003 MATCH x2f001400/mask=xbff81c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# CONSTRUCT x2f00c400/mask=xfff8ec00 MATCHED 3 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:4 ~ &=$dup
# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4
# AUNIT --inst x2f00c400/mask=xfff8ec00 --status pass
:mvni Rd_VPR64.2S, Imm_neon_uimm8Shift
is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1315=6 & b_1011=1 & Rd_VPR64.2S & Zd
{
local tmp1:4 = ~ Imm_neon_uimm8Shift:4;
# simd duplicate Rd_VPR64.2S = all elements tmp1 (lane size 4)
Rd_VPR64.2S[0,32] = tmp1;
Rd_VPR64.2S[32,32] = tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.208 MVNI page C7-1871 line 104944 MATCH x2f000400/mask=xbff80c00
# C7.2.20 BIC (vector, immediate) page C7-1428 line 79003 MATCH x2f001400/mask=xbff81c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# CONSTRUCT x6f00c400/mask=xfff8ec00 MATCHED 3 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:4 ~ &=$dup
# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4
# AUNIT --inst x6f00c400/mask=xfff8ec00 --status pass
:mvni Rd_VPR128.4S, Imm_neon_uimm8Shift
is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1315=6 & b_1011=1 & Rd_VPR128.4S & Zd
{
local tmp1:4 = ~ Imm_neon_uimm8Shift:4;
# simd duplicate Rd_VPR128.4S = all elements tmp1 (lane size 4)
Rd_VPR128.4S[0,32] = tmp1;
Rd_VPR128.4S[32,32] = tmp1;
Rd_VPR128.4S[64,32] = tmp1;
Rd_VPR128.4S[96,32] = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.209 NEG (vector) page C7-1874 line 105094 MATCH x7e20b800/mask=xff3ffc00
# CONSTRUCT x7ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =2comp
# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1
# AUNIT --inst x7ee0b800/mask=xfffffc00 --status pass
:neg Rd_VPR64, Rn_VPR64
is b_3131=0 & q=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64 & Rd_VPR64 & Zd
{
Rd_VPR64 = - Rn_VPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.209 NEG (vector) page C7-1874 line 105094 MATCH x2e20b800/mask=xbf3ffc00
# CONSTRUCT x2e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@1
# AUNIT --inst x2e20b800/mask=xfffffc00 --status nopcodeop
:neg Rd_VPR64.8B, Rn_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_neg(Rn_VPR64.8B, 1:1);
}
# C7.2.209 NEG (vector) page C7-1874 line 105094 MATCH x2e20b800/mask=xbf3ffc00
# CONSTRUCT x6e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@1
# AUNIT --inst x6e20b800/mask=xfffffc00 --status nopcodeop
:neg Rd_VPR128.16B, Rn_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_neg(Rn_VPR128.16B, 1:1);
}
# C7.2.209 NEG (vector) page C7-1874 line 105094 MATCH x2e20b800/mask=xbf3ffc00
# CONSTRUCT x2e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@2
# AUNIT --inst x2e60b800/mask=xfffffc00 --status nopcodeop
:neg Rd_VPR64.4H, Rn_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_neg(Rn_VPR64.4H, 2:1);
}
# C7.2.209 NEG (vector) page C7-1874 line 105094 MATCH x2e20b800/mask=xbf3ffc00
# CONSTRUCT x6e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@2
# AUNIT --inst x6e60b800/mask=xfffffc00 --status nopcodeop
:neg Rd_VPR128.8H, Rn_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_neg(Rn_VPR128.8H, 2:1);
}
# C7.2.209 NEG (vector) page C7-1874 line 105094 MATCH x2e20b800/mask=xbf3ffc00
# CONSTRUCT x2ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@4
# AUNIT --inst x2ea0b800/mask=xfffffc00 --status nopcodeop
:neg Rd_VPR64.2S, Rn_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_neg(Rn_VPR64.2S, 4:1);
}
# C7.2.209 NEG (vector) page C7-1874 line 105094 MATCH x2e20b800/mask=xbf3ffc00
# CONSTRUCT x6ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@4
# AUNIT --inst x6ea0b800/mask=xfffffc00 --status nopcodeop
:neg Rd_VPR128.4S, Rn_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_neg(Rn_VPR128.4S, 4:1);
}
# C7.2.209 NEG (vector) page C7-1874 line 105094 MATCH x2e20b800/mask=xbf3ffc00
# CONSTRUCT x6ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@8
# AUNIT --inst x6ee0b800/mask=xfffffc00 --status nopcodeop
:neg Rd_VPR128.2D, Rn_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_neg(Rn_VPR128.2D, 8:1);
}
# C7.2.211 ORN (vector) page C7-1878 line 105307 MATCH x0ee01c00/mask=xbfe0fc00
# CONSTRUCT x4ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $~@1 =$|@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_orn/2@1
# AUNIT --inst x4ee01c00/mask=xffe0fc00 --status pass
:orn Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd unary TMPQ1 = ~(Rm_VPR128.16B) on lane size 1
TMPQ1[0,8] = ~(Rm_VPR128.16B[0,8]);
TMPQ1[8,8] = ~(Rm_VPR128.16B[8,8]);
TMPQ1[16,8] = ~(Rm_VPR128.16B[16,8]);
TMPQ1[24,8] = ~(Rm_VPR128.16B[24,8]);
TMPQ1[32,8] = ~(Rm_VPR128.16B[32,8]);
TMPQ1[40,8] = ~(Rm_VPR128.16B[40,8]);
TMPQ1[48,8] = ~(Rm_VPR128.16B[48,8]);
TMPQ1[56,8] = ~(Rm_VPR128.16B[56,8]);
TMPQ1[64,8] = ~(Rm_VPR128.16B[64,8]);
TMPQ1[72,8] = ~(Rm_VPR128.16B[72,8]);
TMPQ1[80,8] = ~(Rm_VPR128.16B[80,8]);
TMPQ1[88,8] = ~(Rm_VPR128.16B[88,8]);
TMPQ1[96,8] = ~(Rm_VPR128.16B[96,8]);
TMPQ1[104,8] = ~(Rm_VPR128.16B[104,8]);
TMPQ1[112,8] = ~(Rm_VPR128.16B[112,8]);
TMPQ1[120,8] = ~(Rm_VPR128.16B[120,8]);
# simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ1 on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ1[0,8];
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ1[8,8];
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ1[16,8];
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ1[24,8];
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ1[32,8];
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ1[40,8];
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ1[48,8];
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ1[56,8];
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ1[64,8];
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ1[72,8];
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ1[80,8];
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ1[88,8];
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ1[96,8];
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ1[104,8];
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ1[112,8];
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.211 ORN (vector) page C7-1878 line 105307 MATCH x0ee01c00/mask=xbfe0fc00
# CONSTRUCT x0ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $~@1 =$|@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_orn/2@1
# AUNIT --inst x0ee01c00/mask=xffe0fc00 --status pass
:orn Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd unary TMPD1 = ~(Rm_VPR64.8B) on lane size 1
TMPD1[0,8] = ~(Rm_VPR64.8B[0,8]);
TMPD1[8,8] = ~(Rm_VPR64.8B[8,8]);
TMPD1[16,8] = ~(Rm_VPR64.8B[16,8]);
TMPD1[24,8] = ~(Rm_VPR64.8B[24,8]);
TMPD1[32,8] = ~(Rm_VPR64.8B[32,8]);
TMPD1[40,8] = ~(Rm_VPR64.8B[40,8]);
TMPD1[48,8] = ~(Rm_VPR64.8B[48,8]);
TMPD1[56,8] = ~(Rm_VPR64.8B[56,8]);
# simd infix Rd_VPR64.8B = Rn_VPR64.8B | TMPD1 on lane size 1
Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] | TMPD1[0,8];
Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] | TMPD1[8,8];
Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] | TMPD1[16,8];
Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] | TMPD1[24,8];
Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] | TMPD1[32,8];
Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] | TMPD1[40,8];
Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] | TMPD1[48,8];
Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] | TMPD1[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.212 ORR (vector, immediate) page C7-1880 line 105389 MATCH x0f001400/mask=xbff81c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.254 SHL page C7-1955 line 109567 MATCH x0f005400/mask=xbf80fc00
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x0f007400/mask=xbf80fc00
# C7.2.314 SRSRA page C7-2099 line 117760 MATCH x0f003400/mask=xbf80fc00
# C7.2.318 SSRA page C7-2109 line 118340 MATCH x0f001400/mask=xbf80fc00
# CONSTRUCT x0f001400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:4 &=$|@4
# SMACRO(pseudo) ARG1 ARG2:4 &=NEON_orn/2@4
# AUNIT --inst x0f001400/mask=xfff89c00 --status pass
:orr Rd_VPR64.2S, Imm_neon_uimm8Shift
is b_3131=0 & q=0 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1515=0 & b_1012=5 & Rd_VPR64.2S & Zd
{
# simd infix Rd_VPR64.2S = Rd_VPR64.2S | Imm_neon_uimm8Shift:4 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] | Imm_neon_uimm8Shift:4;
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] | Imm_neon_uimm8Shift:4;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.212 ORR (vector, immediate) page C7-1880 line 105389 MATCH x0f001400/mask=xbff81c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.305 SQSHRN, SQSHRN2 page C7-2076 line 116443 MATCH x0f009400/mask=xbf80fc00
# CONSTRUCT x0f009400/mask=xfff8dc00 MATCHED 3 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:2 &=$|@2
# SMACRO(pseudo) ARG1 ARG2:2 &=NEON_orn/2@2
# AUNIT --inst x0f009400/mask=xfff8dc00 --status pass
:orr Rd_VPR64.4H, Imm_neon_uimm8Shift
is b_3131=0 & q=0 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=5 & Rd_VPR64.4H & Zd
{
# simd infix Rd_VPR64.4H = Rd_VPR64.4H | Imm_neon_uimm8Shift:2 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] | Imm_neon_uimm8Shift:2;
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] | Imm_neon_uimm8Shift:2;
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] | Imm_neon_uimm8Shift:2;
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] | Imm_neon_uimm8Shift:2;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.212 ORR (vector, immediate) page C7-1880 line 105389 MATCH x0f001400/mask=xbff81c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.254 SHL page C7-1955 line 109567 MATCH x0f005400/mask=xbf80fc00
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x0f007400/mask=xbf80fc00
# C7.2.314 SRSRA page C7-2099 line 117760 MATCH x0f003400/mask=xbf80fc00
# C7.2.318 SSRA page C7-2109 line 118340 MATCH x0f001400/mask=xbf80fc00
# CONSTRUCT x4f001400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:4 &=$|
# SMACRO(pseudo) ARG1 ARG2:4 &=NEON_orn/2@4
# AUNIT --inst x4f001400/mask=xfff89c00 --status pass
:orr Rd_VPR128.4S, Imm_neon_uimm8Shift
is b_3131=0 & q=1 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1515=0 & b_1012=5 & Rd_VPR128.4S & Zd
{
# simd infix Rd_VPR128.4S = Rd_VPR128.4S | Imm_neon_uimm8Shift:4 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] | Imm_neon_uimm8Shift:4;
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] | Imm_neon_uimm8Shift:4;
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] | Imm_neon_uimm8Shift:4;
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] | Imm_neon_uimm8Shift:4;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.212 ORR (vector, immediate) page C7-1880 line 105389 MATCH x0f001400/mask=xbff81c00
# C7.2.204 MOVI page C7-1863 line 104465 MATCH x0f000400/mask=x9ff80c00
# C7.2.305 SQSHRN, SQSHRN2 page C7-2076 line 116443 MATCH x0f009400/mask=xbf80fc00
# CONSTRUCT x4f009400/mask=xfff8dc00 MATCHED 3 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2:2 &=$|
# SMACRO(pseudo) ARG1 ARG2:2 &=NEON_orr/2@2
# AUNIT --inst x4f009400/mask=xfff8dc00 --status pass
:orr Rd_VPR128.8H, Imm_neon_uimm8Shift
is b_3131=0 & q=1 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=5 & Rd_VPR128.8H & Zd
{
# simd infix Rd_VPR128.8H = Rd_VPR128.8H | Imm_neon_uimm8Shift:2 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] | Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] | Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] | Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] | Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] | Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] | Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] | Imm_neon_uimm8Shift:2;
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] | Imm_neon_uimm8Shift:2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.213 ORR (vector, register) page C7-1882 line 105515 MATCH x0ea01c00/mask=xbfe0fc00
# C7.2.202 MOV (vector) page C7-1860 line 104306 MATCH x0ea01c00/mask=xbfe0fc00
# CONSTRUCT x4ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$|@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_orr/2@1
# AUNIT --inst x4ea01c00/mask=xffe0fc00 --status pass
:orr Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix Rd_VPR128.16B = Rn_VPR128.16B | Rm_VPR128.16B on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | Rm_VPR128.16B[0,8];
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | Rm_VPR128.16B[8,8];
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | Rm_VPR128.16B[16,8];
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | Rm_VPR128.16B[24,8];
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | Rm_VPR128.16B[32,8];
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | Rm_VPR128.16B[40,8];
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | Rm_VPR128.16B[48,8];
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | Rm_VPR128.16B[56,8];
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | Rm_VPR128.16B[64,8];
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | Rm_VPR128.16B[72,8];
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | Rm_VPR128.16B[80,8];
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | Rm_VPR128.16B[88,8];
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | Rm_VPR128.16B[96,8];
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | Rm_VPR128.16B[104,8];
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | Rm_VPR128.16B[112,8];
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | Rm_VPR128.16B[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.213 ORR (vector, register) page C7-1882 line 105515 MATCH x0ea01c00/mask=xbfe0fc00
# C7.2.202 MOV (vector) page C7-1860 line 104306 MATCH x0ea01c00/mask=xbfe0fc00
# CONSTRUCT x0ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$|@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_orr/2@1
# AUNIT --inst x0ea01c00/mask=xffe0fc00 --status pass
:orr Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix Rd_VPR64.8B = Rn_VPR64.8B | Rm_VPR64.8B on lane size 1
Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] | Rm_VPR64.8B[0,8];
Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] | Rm_VPR64.8B[8,8];
Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] | Rm_VPR64.8B[16,8];
Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] | Rm_VPR64.8B[24,8];
Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] | Rm_VPR64.8B[32,8];
Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] | Rm_VPR64.8B[40,8];
Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] | Rm_VPR64.8B[48,8];
Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] | Rm_VPR64.8B[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.214 PMUL page C7-1884 line 105605 MATCH x2e209c00/mask=xbf20fc00
# CONSTRUCT x6e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmul/2@1
# AUNIT --inst x6e209c00/mask=xffe0fc00 --status nopcodeop
:pmul Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x13 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_pmul(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.214 PMUL page C7-1884 line 105605 MATCH x2e209c00/mask=xbf20fc00
# CONSTRUCT x2e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmul/2@1
# AUNIT --inst x2e209c00/mask=xffe0fc00 --status nopcodeop
:pmul Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x13 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_pmul(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.215 PMULL, PMULL2 page C7-1886 line 105707 MATCH x0e20e000/mask=xbf20fc00
# CONSTRUCT x0ee0e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull/2@8
# AUNIT --inst x0ee0e000/mask=xffe0fc00 --status nopcodeop --comment "ext"
:pmull Rd_VPR128.1Q, Rn_VPR64.1D, Rm_VPR64.1D
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR64.1D & b_1215=0xe & b_1011=0 & Rn_VPR64.1D & Rd_VPR128.1Q & Zd
{
Rd_VPR128.1Q = NEON_pmull(Rn_VPR64.1D, Rm_VPR64.1D, 8:1);
}
# C7.2.215 PMULL, PMULL2 page C7-1886 line 105707 MATCH x0e20e000/mask=xbf20fc00
# CONSTRUCT x0e20e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull/2@1
# AUNIT --inst x0e20e000/mask=xffe0fc00 --status nopcodeop --comment "ext"
:pmull Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xe & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_pmull(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.215 PMULL, PMULL2 page C7-1886 line 105707 MATCH x0e20e000/mask=xbf20fc00
# CONSTRUCT x4ee0e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull2/2@8
# AUNIT --inst x4ee0e000/mask=xffe0fc00 --status nopcodeop --comment "ext"
:pmull2 Rd_VPR128.1Q, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1215=0xe & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.1Q & Zd
{
Rd_VPR128.1Q = NEON_pmull2(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.215 PMULL, PMULL2 page C7-1886 line 105707 MATCH x0e20e000/mask=xbf20fc00
# CONSTRUCT x4e20e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull2/2@1
# AUNIT --inst x4e20e000/mask=xffe0fc00 --status nopcodeop --comment "ext"
:pmull2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xe & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_pmull2(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.216 RADDHN, RADDHN2 page C7-1888 line 105826 MATCH x2e204000/mask=xbf20fc00
# CONSTRUCT x6e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $+@2 0x80:2 &=$+@2 &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn2/3@2
# AUNIT --inst x6e204000/mask=xffe0fc00 --status pass --comment "intround"
:raddhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16];
TMPQ1[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16];
TMPQ1[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16];
TMPQ1[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16];
TMPQ1[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16];
TMPQ1[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16];
TMPQ1[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16];
TMPQ1[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16];
# simd infix TMPQ1 = TMPQ1 + 0x80:2 on lane size 2
TMPQ1[0,16] = TMPQ1[0,16] + 0x80:2;
TMPQ1[16,16] = TMPQ1[16,16] + 0x80:2;
TMPQ1[32,16] = TMPQ1[32,16] + 0x80:2;
TMPQ1[48,16] = TMPQ1[48,16] + 0x80:2;
TMPQ1[64,16] = TMPQ1[64,16] + 0x80:2;
TMPQ1[80,16] = TMPQ1[80,16] + 0x80:2;
TMPQ1[96,16] = TMPQ1[96,16] + 0x80:2;
TMPQ1[112,16] = TMPQ1[112,16] + 0x80:2;
# simd shuffle Rd_VPR128.16B = TMPQ1 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1
Rd_VPR128.16B[64,8] = TMPQ1[8,8];
Rd_VPR128.16B[72,8] = TMPQ1[24,8];
Rd_VPR128.16B[80,8] = TMPQ1[40,8];
Rd_VPR128.16B[88,8] = TMPQ1[56,8];
Rd_VPR128.16B[96,8] = TMPQ1[72,8];
Rd_VPR128.16B[104,8] = TMPQ1[88,8];
Rd_VPR128.16B[112,8] = TMPQ1[104,8];
Rd_VPR128.16B[120,8] = TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.216 RADDHN, RADDHN2 page C7-1888 line 105826 MATCH x2e204000/mask=xbf20fc00
# CONSTRUCT x6ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $+@8 0x80000000:8 &=$+@8 &=$shuffle@1-2@3-3:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn2/3@8
# AUNIT --inst x6ea04000/mask=xffe0fc00 --status pass --comment "intround"
:raddhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
# simd infix TMPQ1 = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64];
TMPQ1[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64];
# simd infix TMPQ1 = TMPQ1 + 0x80000000:8 on lane size 8
TMPQ1[0,64] = TMPQ1[0,64] + 0x80000000:8;
TMPQ1[64,64] = TMPQ1[64,64] + 0x80000000:8;
# simd shuffle Rd_VPR128.4S = TMPQ1 (@1-2@3-3) lane size 4
Rd_VPR128.4S[64,32] = TMPQ1[32,32];
Rd_VPR128.4S[96,32] = TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.216 RADDHN, RADDHN2 page C7-1888 line 105826 MATCH x2e204000/mask=xbf20fc00
# CONSTRUCT x6e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $+@4 0x8000:4 &=$+@4 &=$shuffle@1-4@3-5@5-6@7-7:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn2/3@4
# AUNIT --inst x6e604000/mask=xffe0fc00 --status pass --comment "intround"
:raddhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32];
TMPQ1[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32];
TMPQ1[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32];
TMPQ1[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32];
# simd infix TMPQ1 = TMPQ1 + 0x8000:4 on lane size 4
TMPQ1[0,32] = TMPQ1[0,32] + 0x8000:4;
TMPQ1[32,32] = TMPQ1[32,32] + 0x8000:4;
TMPQ1[64,32] = TMPQ1[64,32] + 0x8000:4;
TMPQ1[96,32] = TMPQ1[96,32] + 0x8000:4;
# simd shuffle Rd_VPR128.8H = TMPQ1 (@1-4@3-5@5-6@7-7) lane size 2
Rd_VPR128.8H[64,16] = TMPQ1[16,16];
Rd_VPR128.8H[80,16] = TMPQ1[48,16];
Rd_VPR128.8H[96,16] = TMPQ1[80,16];
Rd_VPR128.8H[112,16] = TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.216 RADDHN, RADDHN2 page C7-1888 line 105826 MATCH x2e204000/mask=xbf20fc00
# CONSTRUCT x2ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn/3@8
# AUNIT --inst x2ea04000/mask=xffe0fc00 --status nopcodeop
:raddhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_raddhn(Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.216 RADDHN, RADDHN2 page C7-1888 line 105826 MATCH x2e204000/mask=xbf20fc00
# CONSTRUCT x2e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn/3@4
# AUNIT --inst x2e604000/mask=xffe0fc00 --status nopcodeop
:raddhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_raddhn(Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.216 RADDHN, RADDHN2 page C7-1888 line 105826 MATCH x2e204000/mask=xbf20fc00
# CONSTRUCT x2e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn/3@2
# AUNIT --inst x2e204000/mask=xffe0fc00 --status nopcodeop
:raddhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_raddhn(Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.217 RAX1 page C7-1890 line 105949 MATCH xce608c00/mask=xffe0fc00
# CONSTRUCT xce608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 1:8 $<<@8 =$|@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_rax1/2@8
# AUNIT --inst xce608c00/mask=xffe0fc00 --status noqemu
:rax1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_2131=0b11001110011 & b_1015=0b100011 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
{
# simd infix TMPQ1 = Rm_VPR128.2D << 1:8 on lane size 8
TMPQ1[0,64] = Rm_VPR128.2D[0,64] << 1:8;
TMPQ1[64,64] = Rm_VPR128.2D[64,64] << 1:8;
# simd infix Rd_VPR128.2D = Rn_VPR128.2D | TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] | TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] | TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.218 RBIT (vector) page C7-1891 line 106016 MATCH x2e605800/mask=xbffffc00
# CONSTRUCT x2e605800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rbit/1@1
# AUNIT --inst x2e605800/mask=xfffffc00 --status nopcodeop
:rbit Rd_VPR64.8B, Rn_VPR64.8B
is b_31=0 & b_30=0 & b_1029=0b10111001100000010110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_rbit(Rn_VPR64.8B, 1:1);
}
# C7.2.218 RBIT (vector) page C7-1891 line 106016 MATCH x2e605800/mask=xbffffc00
# CONSTRUCT x6e605800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rbit/1@1
# AUNIT --inst x6e605800/mask=xfffffc00 --status nopcodeop
:rbit Rd_VPR128.16B, Rn_VPR128.16B
is b_31=0 & b_30=1 & b_1029=0b10111001100000010110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_rbit(Rn_VPR128.16B, 1:1);
}
# C7.2.219 REV16 (vector) page C7-1893 line 106101 MATCH x0e201800/mask=xbf3ffc00
# CONSTRUCT x4e201800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rev16/1@1
# AUNIT --inst x4e201800/mask=xfffffc00 --status nopcodeop
:rev16 Rd_VPR128.16B, Rn_VPR128.16B
is b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_rev16(Rn_VPR128.16B, 1:1);
}
# C7.2.219 REV16 (vector) page C7-1893 line 106101 MATCH x0e201800/mask=xbf3ffc00
# CONSTRUCT x0e201800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rev16/1@1
# AUNIT --inst x0e201800/mask=xfffffc00 --status nopcodeop
:rev16 Rd_VPR64.8B, Rn_VPR64.8B
is b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_rev16(Rn_VPR64.8B, 1:1);
}
# C7.2.220 REV32 (vector) page C7-1895 line 106218 MATCH x2e200800/mask=xbf3ffc00
# CONSTRUCT x6e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@1
# AUNIT --inst x6e200800/mask=xfffffc00 --status nopcodeop
:rev32 Rd_VPR128.16B, Rn_VPR128.16B
is b_3131=0 & Q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_rev32(Rn_VPR128.16B, 1:1);
}
# C7.2.220 REV32 (vector) page C7-1895 line 106218 MATCH x2e200800/mask=xbf3ffc00
# CONSTRUCT x2e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@2
# AUNIT --inst x2e600800/mask=xfffffc00 --status nopcodeop
:rev32 Rd_VPR64.4H, Rn_VPR64.4H
is b_3131=0 & Q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_rev32(Rn_VPR64.4H, 2:1);
}
# C7.2.220 REV32 (vector) page C7-1895 line 106218 MATCH x2e200800/mask=xbf3ffc00
# CONSTRUCT x2e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@1
# AUNIT --inst x2e200800/mask=xfffffc00 --status nopcodeop
:rev32 Rd_VPR64.8B, Rn_VPR64.8B
is b_3131=0 & Q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_rev32(Rn_VPR64.8B, 1:1);
}
# C7.2.220 REV32 (vector) page C7-1895 line 106218 MATCH x2e200800/mask=xbf3ffc00
# CONSTRUCT x6e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@2
# AUNIT --inst x6e600800/mask=xfffffc00 --status nopcodeop
:rev32 Rd_VPR128.8H, Rn_VPR128.8H
is b_3131=0 & Q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_rev32(Rn_VPR128.8H, 2:1);
}
# C7.2.221 REV64 page C7-1897 line 106333 MATCH x0e200800/mask=xbf3ffc00
# CONSTRUCT x4e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@1
# AUNIT --inst x4e200800/mask=xfffffc00 --status nopcodeop
:rev64 Rd_VPR128.16B, Rn_VPR128.16B
is b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_rev64(Rn_VPR128.16B, 1:1);
}
# C7.2.221 REV64 page C7-1897 line 106333 MATCH x0e200800/mask=xbf3ffc00
# CONSTRUCT x0ea00800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@4
# AUNIT --inst x0ea00800/mask=xfffffc00 --status nopcodeop
:rev64 Rd_VPR64.2S, Rn_VPR64.2S
is b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_rev64(Rn_VPR64.2S, 4:1);
}
# C7.2.221 REV64 page C7-1897 line 106333 MATCH x0e200800/mask=xbf3ffc00
# CONSTRUCT x0e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@2
# AUNIT --inst x0e600800/mask=xfffffc00 --status nopcodeop
:rev64 Rd_VPR64.4H, Rn_VPR64.4H
is b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_rev64(Rn_VPR64.4H, 2:1);
}
# C7.2.221 REV64 page C7-1897 line 106333 MATCH x0e200800/mask=xbf3ffc00
# CONSTRUCT x4ea00800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@4
# AUNIT --inst x4ea00800/mask=xfffffc00 --status nopcodeop
:rev64 Rd_VPR128.4S, Rn_VPR128.4S
is b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_rev64(Rn_VPR128.4S, 4:1);
}
# C7.2.221 REV64 page C7-1897 line 106333 MATCH x0e200800/mask=xbf3ffc00
# CONSTRUCT x0e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@1
# AUNIT --inst x0e200800/mask=xfffffc00 --status nopcodeop
:rev64 Rd_VPR64.8B, Rn_VPR64.8B
is b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_rev64(Rn_VPR64.8B, 1:1);
}
# C7.2.221 REV64 page C7-1897 line 106333 MATCH x0e200800/mask=xbf3ffc00
# CONSTRUCT x4e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@2
# AUNIT --inst x4e600800/mask=xfffffc00 --status nopcodeop
:rev64 Rd_VPR128.8H, Rn_VPR128.8H
is b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_rev64(Rn_VPR128.8H, 2:1);
}
# C7.2.222 RSHRN, RSHRN2 page C7-1899 line 106450 MATCH x0f008c00/mask=xbf80fc00
# CONSTRUCT x4f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn2/3@2
# AUNIT --inst x4f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround"
:rshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_rshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.222 RSHRN, RSHRN2 page C7-1899 line 106450 MATCH x0f008c00/mask=xbf80fc00
# CONSTRUCT x0f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn/3@8
# AUNIT --inst x0f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:rshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_rshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.222 RSHRN, RSHRN2 page C7-1899 line 106450 MATCH x0f008c00/mask=xbf80fc00
# CONSTRUCT x0f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn/3@4
# AUNIT --inst x0f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround"
:rshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_rshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.222 RSHRN, RSHRN2 page C7-1899 line 106450 MATCH x0f008c00/mask=xbf80fc00
# CONSTRUCT x4f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn2/3@8
# AUNIT --inst x4f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:rshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_rshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.222 RSHRN, RSHRN2 page C7-1899 line 106450 MATCH x0f008c00/mask=xbf80fc00
# CONSTRUCT x0f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn/3@2
# AUNIT --inst x0f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround"
:rshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_rshrn(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.222 RSHRN, RSHRN2 page C7-1899 line 106450 MATCH x0f008c00/mask=xbf80fc00
# CONSTRUCT x4f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn2/3@4
# AUNIT --inst x4f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround"
:rshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_rshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.223 RSUBHN, RSUBHN2 page C7-1901 line 106573 MATCH x2e206000/mask=xbf20fc00
# CONSTRUCT x6e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn2/3@2
# AUNIT --inst x6e206000/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:rsubhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_rsubhn2(Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.223 RSUBHN, RSUBHN2 page C7-1901 line 106573 MATCH x2e206000/mask=xbf20fc00
# CONSTRUCT x6ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn2/3@8
# AUNIT --inst x6ea06000/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:rsubhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_rsubhn2(Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.223 RSUBHN, RSUBHN2 page C7-1901 line 106573 MATCH x2e206000/mask=xbf20fc00
# CONSTRUCT x6e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn2/3@4
# AUNIT --inst x6e606000/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:rsubhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_rsubhn2(Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.223 RSUBHN, RSUBHN2 page C7-1901 line 106573 MATCH x2e206000/mask=xbf20fc00
# CONSTRUCT x2ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn/3@8
# AUNIT --inst x2ea06000/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:rsubhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_rsubhn(Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.223 RSUBHN, RSUBHN2 page C7-1901 line 106573 MATCH x2e206000/mask=xbf20fc00
# CONSTRUCT x2e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn/3@4
# AUNIT --inst x2e606000/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:rsubhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_rsubhn(Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.223 RSUBHN, RSUBHN2 page C7-1901 line 106573 MATCH x2e206000/mask=xbf20fc00
# CONSTRUCT x2e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn/3@2
# AUNIT --inst x2e206000/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:rsubhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_rsubhn(Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.224 SABA page C7-1903 line 106699 MATCH x0e207c00/mask=xbf20fc00
# CONSTRUCT x4e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@1
# AUNIT --inst x4e207c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
:saba Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xf & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_saba(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.224 SABA page C7-1903 line 106699 MATCH x0e207c00/mask=xbf20fc00
# CONSTRUCT x0ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@4
# AUNIT --inst x0ea07c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
:saba Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xf & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_saba(Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.224 SABA page C7-1903 line 106699 MATCH x0e207c00/mask=xbf20fc00
# CONSTRUCT x0e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@2
# AUNIT --inst x0e607c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
:saba Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xf & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_saba(Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.224 SABA page C7-1903 line 106699 MATCH x0e207c00/mask=xbf20fc00
# CONSTRUCT x4ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@4
# AUNIT --inst x4ea07c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
:saba Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xf & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_saba(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.224 SABA page C7-1903 line 106699 MATCH x0e207c00/mask=xbf20fc00
# CONSTRUCT x0e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@1
# AUNIT --inst x0e207c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
:saba Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xf & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_saba(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.224 SABA page C7-1903 line 106699 MATCH x0e207c00/mask=xbf20fc00
# CONSTRUCT x4e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@2
# AUNIT --inst x4e607c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
:saba Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xf & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_saba(Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.225 SABAL, SABAL2 page C7-1905 line 106799 MATCH x0e205000/mask=xbf20fc00
# CONSTRUCT x0ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $-@8 $abs@8 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal/3@4
# AUNIT --inst x0ea05000/mask=xffe0fc00 --status pass --comment "ext abd"
:sabal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x5 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8
TMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64];
TMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64];
# simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 8
TMPQ4[0,64] = MP_INT_ABS(TMPQ3[0,64]);
TMPQ4[64,64] = MP_INT_ABS(TMPQ3[64,64]);
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.225 SABAL, SABAL2 page C7-1905 line 106799 MATCH x0e205000/mask=xbf20fc00
# CONSTRUCT x0e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $-@4 $abs@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal/3@2
# AUNIT --inst x0e605000/mask=xffe0fc00 --status pass --comment "ext abd"
:sabal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x5 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4
TMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32];
TMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32];
TMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32];
TMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32];
# simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 4
TMPQ4[0,32] = MP_INT_ABS(TMPQ3[0,32]);
TMPQ4[32,32] = MP_INT_ABS(TMPQ3[32,32]);
TMPQ4[64,32] = MP_INT_ABS(TMPQ3[64,32]);
TMPQ4[96,32] = MP_INT_ABS(TMPQ3[96,32]);
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.225 SABAL, SABAL2 page C7-1905 line 106799 MATCH x0e205000/mask=xbf20fc00
# CONSTRUCT x0e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $-@2 $abs@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal/3@1
# AUNIT --inst x0e205000/mask=xffe0fc00 --status pass --comment "ext abd"
:sabal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x5 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2
TMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16];
TMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16];
TMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16];
TMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16];
TMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16];
TMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16];
TMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16];
TMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16];
# simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 2
TMPQ4[0,16] = MP_INT_ABS(TMPQ3[0,16]);
TMPQ4[16,16] = MP_INT_ABS(TMPQ3[16,16]);
TMPQ4[32,16] = MP_INT_ABS(TMPQ3[32,16]);
TMPQ4[48,16] = MP_INT_ABS(TMPQ3[48,16]);
TMPQ4[64,16] = MP_INT_ABS(TMPQ3[64,16]);
TMPQ4[80,16] = MP_INT_ABS(TMPQ3[80,16]);
TMPQ4[96,16] = MP_INT_ABS(TMPQ3[96,16]);
TMPQ4[112,16] = MP_INT_ABS(TMPQ3[112,16]);
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ4 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ4[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ4[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ4[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ4[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ4[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ4[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ4[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ4[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.225 SABAL, SABAL2 page C7-1905 line 106799 MATCH x0e205000/mask=xbf20fc00
# CONSTRUCT x4ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $-@8 $abs@8 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal2/3@4
# AUNIT --inst x4ea05000/mask=xffe0fc00 --status pass --comment "ext abd"
:sabal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x5 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = sext(TMPD3[0,32]);
TMPQ4[64,64] = sext(TMPD3[32,32]);
# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8
TMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64];
TMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64];
# simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 8
TMPQ6[0,64] = MP_INT_ABS(TMPQ5[0,64]);
TMPQ6[64,64] = MP_INT_ABS(TMPQ5[64,64]);
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ6 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ6[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ6[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.225 SABAL, SABAL2 page C7-1905 line 106799 MATCH x0e205000/mask=xbf20fc00
# CONSTRUCT x4e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $-@4 $abs@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal2/3@2
# AUNIT --inst x4e605000/mask=xffe0fc00 --status pass --comment "ext abd"
:sabal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x5 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = sext(TMPD3[0,16]);
TMPQ4[32,32] = sext(TMPD3[16,16]);
TMPQ4[64,32] = sext(TMPD3[32,16]);
TMPQ4[96,32] = sext(TMPD3[48,16]);
# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4
TMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32];
TMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32];
TMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32];
TMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32];
# simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 4
TMPQ6[0,32] = MP_INT_ABS(TMPQ5[0,32]);
TMPQ6[32,32] = MP_INT_ABS(TMPQ5[32,32]);
TMPQ6[64,32] = MP_INT_ABS(TMPQ5[64,32]);
TMPQ6[96,32] = MP_INT_ABS(TMPQ5[96,32]);
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ6 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ6[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ6[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ6[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ6[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.225 SABAL, SABAL2 page C7-1905 line 106799 MATCH x0e205000/mask=xbf20fc00
# CONSTRUCT x4e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $-@2 $abs@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal2/3@1
# AUNIT --inst x4e205000/mask=xffe0fc00 --status pass --comment "ext abd"
:sabal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x5 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = sext(TMPD1[0,8]);
TMPQ2[16,16] = sext(TMPD1[8,8]);
TMPQ2[32,16] = sext(TMPD1[16,8]);
TMPQ2[48,16] = sext(TMPD1[24,8]);
TMPQ2[64,16] = sext(TMPD1[32,8]);
TMPQ2[80,16] = sext(TMPD1[40,8]);
TMPQ2[96,16] = sext(TMPD1[48,8]);
TMPQ2[112,16] = sext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = sext(TMPD3[0,8]);
TMPQ4[16,16] = sext(TMPD3[8,8]);
TMPQ4[32,16] = sext(TMPD3[16,8]);
TMPQ4[48,16] = sext(TMPD3[24,8]);
TMPQ4[64,16] = sext(TMPD3[32,8]);
TMPQ4[80,16] = sext(TMPD3[40,8]);
TMPQ4[96,16] = sext(TMPD3[48,8]);
TMPQ4[112,16] = sext(TMPD3[56,8]);
# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2
TMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16];
TMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16];
TMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16];
TMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16];
TMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16];
TMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16];
TMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16];
TMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16];
# simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 2
TMPQ6[0,16] = MP_INT_ABS(TMPQ5[0,16]);
TMPQ6[16,16] = MP_INT_ABS(TMPQ5[16,16]);
TMPQ6[32,16] = MP_INT_ABS(TMPQ5[32,16]);
TMPQ6[48,16] = MP_INT_ABS(TMPQ5[48,16]);
TMPQ6[64,16] = MP_INT_ABS(TMPQ5[64,16]);
TMPQ6[80,16] = MP_INT_ABS(TMPQ5[80,16]);
TMPQ6[96,16] = MP_INT_ABS(TMPQ5[96,16]);
TMPQ6[112,16] = MP_INT_ABS(TMPQ5[112,16]);
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ6 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ6[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ6[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ6[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ6[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ6[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ6[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ6[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ6[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.226 SABD page C7-1907 line 106916 MATCH x0e207400/mask=xbf20fc00
# CONSTRUCT x4e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@1
# AUNIT --inst x4e207400/mask=xffe0fc00 --status nopcodeop --comment "abd"
:sabd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sabd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.226 SABD page C7-1907 line 106916 MATCH x0e207400/mask=xbf20fc00
# CONSTRUCT x0ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $-@4 ARG3 ARG2 $-@4 2:4 &=$* ARG2 ARG3 $sless@4 &=$*@4 =$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@4
# AUNIT --inst x0ea07400/mask=xffe0fc00 --status pass --comment "abd"
# This abd instruction is implemented correctly to document a correct
# way to implement the signed absolute difference semantic.
:sabd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix TMPD1 = Rn_VPR64.2S - Rm_VPR64.2S on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] - Rm_VPR64.2S[0,32];
TMPD1[32,32] = Rn_VPR64.2S[32,32] - Rm_VPR64.2S[32,32];
# simd infix TMPD2 = Rm_VPR64.2S - Rn_VPR64.2S on lane size 4
TMPD2[0,32] = Rm_VPR64.2S[0,32] - Rn_VPR64.2S[0,32];
TMPD2[32,32] = Rm_VPR64.2S[32,32] - Rn_VPR64.2S[32,32];
# simd infix TMPD2 = TMPD2 * 2:4 on lane size 4
TMPD2[0,32] = TMPD2[0,32] * 2:4;
TMPD2[32,32] = TMPD2[32,32] * 2:4;
# simd infix TMPD3 = Rn_VPR64.2S s< Rm_VPR64.2S on lane size 4
TMPD3[0,32] = zext(Rn_VPR64.2S[0,32] s< Rm_VPR64.2S[0,32]);
TMPD3[32,32] = zext(Rn_VPR64.2S[32,32] s< Rm_VPR64.2S[32,32]);
# simd infix TMPD2 = TMPD2 * TMPD3 on lane size 4
TMPD2[0,32] = TMPD2[0,32] * TMPD3[0,32];
TMPD2[32,32] = TMPD2[32,32] * TMPD3[32,32];
# simd infix Rd_VPR64.2S = TMPD1 + TMPD2 on lane size 4
Rd_VPR64.2S[0,32] = TMPD1[0,32] + TMPD2[0,32];
Rd_VPR64.2S[32,32] = TMPD1[32,32] + TMPD2[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.226 SABD page C7-1907 line 106916 MATCH x0e207400/mask=xbf20fc00
# CONSTRUCT x0e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@2
# AUNIT --inst x0e607400/mask=xffe0fc00 --status nopcodeop --comment "abd"
:sabd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sabd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.226 SABD page C7-1907 line 106916 MATCH x0e207400/mask=xbf20fc00
# CONSTRUCT x4ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@4
# AUNIT --inst x4ea07400/mask=xffe0fc00 --status nopcodeop --comment "abd"
:sabd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sabd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.226 SABD page C7-1907 line 106916 MATCH x0e207400/mask=xbf20fc00
# CONSTRUCT x0e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@1
# AUNIT --inst x0e207400/mask=xffe0fc00 --status nopcodeop --comment "abd"
:sabd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sabd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.226 SABD page C7-1907 line 106916 MATCH x0e207400/mask=xbf20fc00
# CONSTRUCT x4e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@2
# AUNIT --inst x4e607400/mask=xffe0fc00 --status nopcodeop --comment "abd"
:sabd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sabd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.227 SABDL, SABDL2 page C7-1909 line 107016 MATCH x0e207000/mask=xbf20fc00
# CONSTRUCT x0ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $-@8 =$abs@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl/3@4
# AUNIT --inst x0ea07000/mask=xffe0fc00 --status pass --comment "ext abd"
:sabdl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x7 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8
TMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64];
TMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64];
# simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ3) on lane size 8
Rd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ3[0,64]);
Rd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ3[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.227 SABDL, SABDL2 page C7-1909 line 107016 MATCH x0e207000/mask=xbf20fc00
# CONSTRUCT x0e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $-@4 =$abs@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl/3@2
# AUNIT --inst x0e607000/mask=xffe0fc00 --status pass --comment "ext abd"
:sabdl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x7 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4
TMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32];
TMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32];
TMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32];
TMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32];
# simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ3) on lane size 4
Rd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ3[0,32]);
Rd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ3[32,32]);
Rd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ3[64,32]);
Rd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ3[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.227 SABDL, SABDL2 page C7-1909 line 107016 MATCH x0e207000/mask=xbf20fc00
# CONSTRUCT x0e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $-@2 =$abs@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl/3@1
# AUNIT --inst x0e207000/mask=xffe0fc00 --status pass --comment "ext abd"
:sabdl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x7 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2
TMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16];
TMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16];
TMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16];
TMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16];
TMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16];
TMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16];
TMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16];
TMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16];
# simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ3) on lane size 2
Rd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ3[0,16]);
Rd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ3[16,16]);
Rd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ3[32,16]);
Rd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ3[48,16]);
Rd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ3[64,16]);
Rd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ3[80,16]);
Rd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ3[96,16]);
Rd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ3[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.227 SABDL, SABDL2 page C7-1909 line 107016 MATCH x0e207000/mask=xbf20fc00
# CONSTRUCT x4ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $-@8 =$abs@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl2/3@4
# AUNIT --inst x4ea07000/mask=xffe0fc00 --status pass --comment "ext abd"
:sabdl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x7 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = sext(TMPD3[0,32]);
TMPQ4[64,64] = sext(TMPD3[32,32]);
# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8
TMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64];
TMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64];
# simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ5) on lane size 8
Rd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ5[0,64]);
Rd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ5[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.227 SABDL, SABDL2 page C7-1909 line 107016 MATCH x0e207000/mask=xbf20fc00
# CONSTRUCT x4e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $-@4 =$abs@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl2/3@2
# AUNIT --inst x4e607000/mask=xffe0fc00 --status pass --comment "ext abd"
:sabdl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x7 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = sext(TMPD3[0,16]);
TMPQ4[32,32] = sext(TMPD3[16,16]);
TMPQ4[64,32] = sext(TMPD3[32,16]);
TMPQ4[96,32] = sext(TMPD3[48,16]);
# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4
TMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32];
TMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32];
TMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32];
TMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32];
# simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ5) on lane size 4
Rd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ5[0,32]);
Rd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ5[32,32]);
Rd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ5[64,32]);
Rd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ5[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.227 SABDL, SABDL2 page C7-1909 line 107016 MATCH x0e207000/mask=xbf20fc00
# CONSTRUCT x4e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $-@2 =$abs@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl2/3@1
# AUNIT --inst x4e207000/mask=xffe0fc00 --status pass --comment "ext abd"
:sabdl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x7 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = sext(TMPD1[0,8]);
TMPQ2[16,16] = sext(TMPD1[8,8]);
TMPQ2[32,16] = sext(TMPD1[16,8]);
TMPQ2[48,16] = sext(TMPD1[24,8]);
TMPQ2[64,16] = sext(TMPD1[32,8]);
TMPQ2[80,16] = sext(TMPD1[40,8]);
TMPQ2[96,16] = sext(TMPD1[48,8]);
TMPQ2[112,16] = sext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = sext(TMPD3[0,8]);
TMPQ4[16,16] = sext(TMPD3[8,8]);
TMPQ4[32,16] = sext(TMPD3[16,8]);
TMPQ4[48,16] = sext(TMPD3[24,8]);
TMPQ4[64,16] = sext(TMPD3[32,8]);
TMPQ4[80,16] = sext(TMPD3[40,8]);
TMPQ4[96,16] = sext(TMPD3[48,8]);
TMPQ4[112,16] = sext(TMPD3[56,8]);
# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2
TMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16];
TMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16];
TMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16];
TMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16];
TMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16];
TMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16];
TMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16];
TMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16];
# simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ5) on lane size 2
Rd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ5[0,16]);
Rd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ5[16,16]);
Rd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ5[32,16]);
Rd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ5[48,16]);
Rd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ5[64,16]);
Rd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ5[80,16]);
Rd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ5[96,16]);
Rd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ5[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.228 SADALP page C7-1911 line 107134 MATCH x0e206800/mask=xbf3ffc00
# CONSTRUCT x0e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:8 ARG2 =#+ &=$+@2
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@1
# AUNIT --inst x0e206800/mask=xfffffc00 --status pass --comment "ext"
# Vector variant when 4H when size = 00 , Q = 0 Ta=VPR64.4H Tb=VPR64.8B e1=1 e2=2 s2=16
:sadalp Rd_VPR64.4H, Rn_VPR64.8B
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011010 & Rd_VPR64.4H & Rn_VPR64.8B & Zd
{
TMPD1 = 0;
# sipd infix TMPD1 = +(Rn_VPR64.8B) on pairs lane size (1 to 2)
tmp2 = Rn_VPR64.8B[0,8];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR64.8B[8,8];
tmp5 = sext(tmp3);
TMPD1[0,16] = tmp4 + tmp5;
tmp2 = Rn_VPR64.8B[16,8];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR64.8B[24,8];
tmp5 = sext(tmp3);
TMPD1[16,16] = tmp4 + tmp5;
tmp2 = Rn_VPR64.8B[32,8];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR64.8B[40,8];
tmp5 = sext(tmp3);
TMPD1[32,16] = tmp4 + tmp5;
tmp2 = Rn_VPR64.8B[48,8];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR64.8B[56,8];
tmp5 = sext(tmp3);
TMPD1[48,16] = tmp4 + tmp5;
# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.228 SADALP page C7-1911 line 107134 MATCH x0e206800/mask=xbf3ffc00
# CONSTRUCT x4e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 =#+ &=$+@2
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@1
# AUNIT --inst x4e206800/mask=xfffffc00 --status pass --comment "ext"
# Vector variant when 8H when size = 00 , Q = 1 Ta=VPR128.8H Tb=VPR128.16B e1=1 e2=2 s2=32
:sadalp Rd_VPR128.8H, Rn_VPR128.16B
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011010 & Rd_VPR128.8H & Rn_VPR128.16B & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = +(Rn_VPR128.16B) on pairs lane size (1 to 2)
tmp2 = Rn_VPR128.16B[0,8];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.16B[8,8];
tmp5 = sext(tmp3);
TMPQ1[0,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[16,8];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.16B[24,8];
tmp5 = sext(tmp3);
TMPQ1[16,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[32,8];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.16B[40,8];
tmp5 = sext(tmp3);
TMPQ1[32,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[48,8];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.16B[56,8];
tmp5 = sext(tmp3);
TMPQ1[48,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[64,8];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.16B[72,8];
tmp5 = sext(tmp3);
TMPQ1[64,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[80,8];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.16B[88,8];
tmp5 = sext(tmp3);
TMPQ1[80,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[96,8];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.16B[104,8];
tmp5 = sext(tmp3);
TMPQ1[96,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[112,8];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.16B[120,8];
tmp5 = sext(tmp3);
TMPQ1[112,16] = tmp4 + tmp5;
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.228 SADALP page C7-1911 line 107134 MATCH x0e206800/mask=xbf3ffc00
# CONSTRUCT x0e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:8 ARG2 =#+ &=$+@4
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@2
# AUNIT --inst x0e606800/mask=xfffffc00 --status pass --comment "ext"
# Vector variant when 2S when size = 01 , Q = 0 Ta=VPR64.2S Tb=VPR64.4H e1=2 e2=4 s2=16
:sadalp Rd_VPR64.2S, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011010 & Rd_VPR64.2S & Rn_VPR64.4H & Zd
{
TMPD1 = 0;
# sipd infix TMPD1 = +(Rn_VPR64.4H) on pairs lane size (2 to 4)
tmp2 = Rn_VPR64.4H[0,16];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR64.4H[16,16];
tmp5 = sext(tmp3);
TMPD1[0,32] = tmp4 + tmp5;
tmp2 = Rn_VPR64.4H[32,16];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR64.4H[48,16];
tmp5 = sext(tmp3);
TMPD1[32,32] = tmp4 + tmp5;
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.228 SADALP page C7-1911 line 107134 MATCH x0e206800/mask=xbf3ffc00
# CONSTRUCT x4e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 =#+ &=$+@4
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@2
# AUNIT --inst x4e606800/mask=xfffffc00 --status pass --comment "ext"
# Vector variant when 4S when size = 01 , Q = 1 Ta=VPR128.4S Tb=VPR128.8H e1=2 e2=4 s2=32
:sadalp Rd_VPR128.4S, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011010 & Rd_VPR128.4S & Rn_VPR128.8H & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = +(Rn_VPR128.8H) on pairs lane size (2 to 4)
tmp2 = Rn_VPR128.8H[0,16];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.8H[16,16];
tmp5 = sext(tmp3);
TMPQ1[0,32] = tmp4 + tmp5;
tmp2 = Rn_VPR128.8H[32,16];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.8H[48,16];
tmp5 = sext(tmp3);
TMPQ1[32,32] = tmp4 + tmp5;
tmp2 = Rn_VPR128.8H[64,16];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.8H[80,16];
tmp5 = sext(tmp3);
TMPQ1[64,32] = tmp4 + tmp5;
tmp2 = Rn_VPR128.8H[96,16];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.8H[112,16];
tmp5 = sext(tmp3);
TMPQ1[96,32] = tmp4 + tmp5;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.228 SADALP page C7-1911 line 107134 MATCH x0e206800/mask=xbf3ffc00
# CONSTRUCT x0ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:8 ARG2 =#+ &=$+@8
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@4
# AUNIT --inst x0ea06800/mask=xfffffc00 --status pass --comment "ext"
# Vector variant when 1D when size = 10 , Q = 0 Ta=VPR64.1D Tb=VPR64.2S e1=4 e2=8 s2=16
:sadalp Rd_VPR64.1D, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011010 & Rd_VPR64.1D & Rn_VPR64.2S & Zd
{
# sipd infix TMPD1 = +(Rn_VPR64.2S) on pairs lane size (4 to 8)
tmp2 = Rn_VPR64.2S[0,32];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR64.2S[32,32];
tmp5 = sext(tmp3);
tmpd1 = tmp4 + tmp5;
# simd infix Rd_VPR64.1D = Rd_VPR64.1D + TMPD1 on lane size 8
Rd_VPR64.1D[0,64] = Rd_VPR64.1D[0,64] + tmpd1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.228 SADALP page C7-1911 line 107134 MATCH x0e206800/mask=xbf3ffc00
# CONSTRUCT x4ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 =#+ &=$+@8
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@4
# AUNIT --inst x4ea06800/mask=xfffffc00 --status pass --comment "ext"
# Vector variant when 2D when size = 10 , Q = 1 Ta=VPR128.2D Tb=VPR128.4S e1=4 e2=8 s2=32
:sadalp Rd_VPR128.2D, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011010 & Rd_VPR128.2D & Rn_VPR128.4S & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = +(Rn_VPR128.4S) on pairs lane size (4 to 8)
tmp2 = Rn_VPR128.4S[0,32];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.4S[32,32];
tmp5 = sext(tmp3);
TMPQ1[0,64] = tmp4 + tmp5;
tmp2 = Rn_VPR128.4S[64,32];
tmp4 = sext(tmp2);
tmp3 = Rn_VPR128.4S[96,32];
tmp5 = sext(tmp3);
TMPQ1[64,64] = tmp4 + tmp5;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.229 SADDL, SADDL2 page C7-1913 line 107243 MATCH x0e200000/mask=xbf20fc00
# CONSTRUCT x0ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 =$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saddl/2@4
# AUNIT --inst x0ea00000/mask=xffe0fc00 --status pass --comment "ext"
:saddl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x0 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
# simd infix Rd_VPR128.2D = TMPQ1 + TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64] + TMPQ2[0,64];
Rd_VPR128.2D[64,64] = TMPQ1[64,64] + TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.229 SADDL, SADDL2 page C7-1913 line 107243 MATCH x0e200000/mask=xbf20fc00
# CONSTRUCT x0e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 =$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl/2@2
# AUNIT --inst x0e600000/mask=xffe0fc00 --status pass --comment "ext"
:saddl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x0 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
# simd infix Rd_VPR128.4S = TMPQ1 + TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32] + TMPQ2[0,32];
Rd_VPR128.4S[32,32] = TMPQ1[32,32] + TMPQ2[32,32];
Rd_VPR128.4S[64,32] = TMPQ1[64,32] + TMPQ2[64,32];
Rd_VPR128.4S[96,32] = TMPQ1[96,32] + TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.229 SADDL, SADDL2 page C7-1913 line 107243 MATCH x0e200000/mask=xbf20fc00
# CONSTRUCT x0e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 =$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl/2@1
# AUNIT --inst x0e200000/mask=xffe0fc00 --status pass --comment "ext"
:saddl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x0 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
# simd infix Rd_VPR128.8H = TMPQ1 + TMPQ2 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[0,16] + TMPQ2[0,16];
Rd_VPR128.8H[16,16] = TMPQ1[16,16] + TMPQ2[16,16];
Rd_VPR128.8H[32,16] = TMPQ1[32,16] + TMPQ2[32,16];
Rd_VPR128.8H[48,16] = TMPQ1[48,16] + TMPQ2[48,16];
Rd_VPR128.8H[64,16] = TMPQ1[64,16] + TMPQ2[64,16];
Rd_VPR128.8H[80,16] = TMPQ1[80,16] + TMPQ2[80,16];
Rd_VPR128.8H[96,16] = TMPQ1[96,16] + TMPQ2[96,16];
Rd_VPR128.8H[112,16] = TMPQ1[112,16] + TMPQ2[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.229 SADDL, SADDL2 page C7-1913 line 107243 MATCH x0e200000/mask=xbf20fc00
# CONSTRUCT x4ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 =$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl2/2@4
# AUNIT --inst x4ea00000/mask=xffe0fc00 --status pass --comment "ext"
:saddl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x0 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = sext(TMPD3[0,32]);
TMPQ4[64,64] = sext(TMPD3[32,32]);
# simd infix Rd_VPR128.2D = TMPQ2 + TMPQ4 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ2[0,64] + TMPQ4[0,64];
Rd_VPR128.2D[64,64] = TMPQ2[64,64] + TMPQ4[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.229 SADDL, SADDL2 page C7-1913 line 107243 MATCH x0e200000/mask=xbf20fc00
# CONSTRUCT x4e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 =$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl2/2@2
# AUNIT --inst x4e600000/mask=xffe0fc00 --status pass --comment "ext"
:saddl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x0 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = sext(TMPD3[0,16]);
TMPQ4[32,32] = sext(TMPD3[16,16]);
TMPQ4[64,32] = sext(TMPD3[32,16]);
TMPQ4[96,32] = sext(TMPD3[48,16]);
# simd infix Rd_VPR128.4S = TMPQ2 + TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ2[0,32] + TMPQ4[0,32];
Rd_VPR128.4S[32,32] = TMPQ2[32,32] + TMPQ4[32,32];
Rd_VPR128.4S[64,32] = TMPQ2[64,32] + TMPQ4[64,32];
Rd_VPR128.4S[96,32] = TMPQ2[96,32] + TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.229 SADDL, SADDL2 page C7-1913 line 107243 MATCH x0e200000/mask=xbf20fc00
# CONSTRUCT x4e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 =$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl2/2@1
# AUNIT --inst x4e200000/mask=xffe0fc00 --status pass --comment "ext"
:saddl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x0 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = sext(TMPD1[0,8]);
TMPQ2[16,16] = sext(TMPD1[8,8]);
TMPQ2[32,16] = sext(TMPD1[16,8]);
TMPQ2[48,16] = sext(TMPD1[24,8]);
TMPQ2[64,16] = sext(TMPD1[32,8]);
TMPQ2[80,16] = sext(TMPD1[40,8]);
TMPQ2[96,16] = sext(TMPD1[48,8]);
TMPQ2[112,16] = sext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = sext(TMPD3[0,8]);
TMPQ4[16,16] = sext(TMPD3[8,8]);
TMPQ4[32,16] = sext(TMPD3[16,8]);
TMPQ4[48,16] = sext(TMPD3[24,8]);
TMPQ4[64,16] = sext(TMPD3[32,8]);
TMPQ4[80,16] = sext(TMPD3[40,8]);
TMPQ4[96,16] = sext(TMPD3[48,8]);
TMPQ4[112,16] = sext(TMPD3[56,8]);
# simd infix Rd_VPR128.8H = TMPQ2 + TMPQ4 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ2[0,16] + TMPQ4[0,16];
Rd_VPR128.8H[16,16] = TMPQ2[16,16] + TMPQ4[16,16];
Rd_VPR128.8H[32,16] = TMPQ2[32,16] + TMPQ4[32,16];
Rd_VPR128.8H[48,16] = TMPQ2[48,16] + TMPQ4[48,16];
Rd_VPR128.8H[64,16] = TMPQ2[64,16] + TMPQ4[64,16];
Rd_VPR128.8H[80,16] = TMPQ2[80,16] + TMPQ4[80,16];
Rd_VPR128.8H[96,16] = TMPQ2[96,16] + TMPQ4[96,16];
Rd_VPR128.8H[112,16] = TMPQ2[112,16] + TMPQ4[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.230 SADDLP page C7-1915 line 107363 MATCH x0e202800/mask=xbf3ffc00
# CONSTRUCT x0ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =#+@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@4
# AUNIT --inst x0ea02800/mask=xfffffc00 --status pass --comment "ext"
:saddlp Rd_VPR64.1D, Rn_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.1D & Zd
{
TMPD1 = Rn_VPR64.2S;
# sipd infix Rd_VPR64.1D = +(TMPD1) on pairs lane size (4 to 8)
tmp2 = TMPD1[0,32];
tmp4 = sext(tmp2);
tmp3 = TMPD1[32,32];
tmp5 = sext(tmp3);
Rd_VPR64.1D[0,64] = tmp4 + tmp5;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.230 SADDLP page C7-1915 line 107363 MATCH x0e202800/mask=xbf3ffc00
# CONSTRUCT x0e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =#+@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@2
# AUNIT --inst x0e602800/mask=xfffffc00 --status pass --comment "ext"
:saddlp Rd_VPR64.2S, Rn_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.2S & Zd
{
TMPD1 = Rn_VPR64.4H;
# sipd infix Rd_VPR64.2S = +(TMPD1) on pairs lane size (2 to 4)
tmp2 = TMPD1[0,16];
tmp4 = sext(tmp2);
tmp3 = TMPD1[16,16];
tmp5 = sext(tmp3);
Rd_VPR64.2S[0,32] = tmp4 + tmp5;
tmp2 = TMPD1[32,16];
tmp4 = sext(tmp2);
tmp3 = TMPD1[48,16];
tmp5 = sext(tmp3);
Rd_VPR64.2S[32,32] = tmp4 + tmp5;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.230 SADDLP page C7-1915 line 107363 MATCH x0e202800/mask=xbf3ffc00
# CONSTRUCT x0e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =#+@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@1
# AUNIT --inst x0e202800/mask=xfffffc00 --status pass --comment "ext"
:saddlp Rd_VPR64.4H, Rn_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.4H & Zd
{
TMPD1 = Rn_VPR64.8B;
# sipd infix Rd_VPR64.4H = +(TMPD1) on pairs lane size (1 to 2)
tmp2 = TMPD1[0,8];
tmp4 = sext(tmp2);
tmp3 = TMPD1[8,8];
tmp5 = sext(tmp3);
Rd_VPR64.4H[0,16] = tmp4 + tmp5;
tmp2 = TMPD1[16,8];
tmp4 = sext(tmp2);
tmp3 = TMPD1[24,8];
tmp5 = sext(tmp3);
Rd_VPR64.4H[16,16] = tmp4 + tmp5;
tmp2 = TMPD1[32,8];
tmp4 = sext(tmp2);
tmp3 = TMPD1[40,8];
tmp5 = sext(tmp3);
Rd_VPR64.4H[32,16] = tmp4 + tmp5;
tmp2 = TMPD1[48,8];
tmp4 = sext(tmp2);
tmp3 = TMPD1[56,8];
tmp5 = sext(tmp3);
Rd_VPR64.4H[48,16] = tmp4 + tmp5;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.230 SADDLP page C7-1915 line 107363 MATCH x0e202800/mask=xbf3ffc00
# CONSTRUCT x4ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =#+@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@4
# AUNIT --inst x4ea02800/mask=xfffffc00 --status pass --comment "ext"
:saddlp Rd_VPR128.2D, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPQ1 = Rn_VPR128.4S;
# sipd infix Rd_VPR128.2D = +(TMPQ1) on pairs lane size (4 to 8)
tmp2 = TMPQ1[0,32];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[32,32];
tmp5 = sext(tmp3);
Rd_VPR128.2D[0,64] = tmp4 + tmp5;
tmp2 = TMPQ1[64,32];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[96,32];
tmp5 = sext(tmp3);
Rd_VPR128.2D[64,64] = tmp4 + tmp5;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.230 SADDLP page C7-1915 line 107363 MATCH x0e202800/mask=xbf3ffc00
# CONSTRUCT x4e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =#+@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@2
# AUNIT --inst x4e602800/mask=xfffffc00 --status pass --comment "ext"
:saddlp Rd_VPR128.4S, Rn_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPQ1 = Rn_VPR128.8H;
# sipd infix Rd_VPR128.4S = +(TMPQ1) on pairs lane size (2 to 4)
tmp2 = TMPQ1[0,16];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[16,16];
tmp5 = sext(tmp3);
Rd_VPR128.4S[0,32] = tmp4 + tmp5;
tmp2 = TMPQ1[32,16];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[48,16];
tmp5 = sext(tmp3);
Rd_VPR128.4S[32,32] = tmp4 + tmp5;
tmp2 = TMPQ1[64,16];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[80,16];
tmp5 = sext(tmp3);
Rd_VPR128.4S[64,32] = tmp4 + tmp5;
tmp2 = TMPQ1[96,16];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[112,16];
tmp5 = sext(tmp3);
Rd_VPR128.4S[96,32] = tmp4 + tmp5;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.230 SADDLP page C7-1915 line 107363 MATCH x0e202800/mask=xbf3ffc00
# CONSTRUCT x4e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =#+@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@1
# AUNIT --inst x4e202800/mask=xfffffc00 --status pass --comment "ext"
:saddlp Rd_VPR128.8H, Rn_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPQ1 = Rn_VPR128.16B;
# sipd infix Rd_VPR128.8H = +(TMPQ1) on pairs lane size (1 to 2)
tmp2 = TMPQ1[0,8];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[8,8];
tmp5 = sext(tmp3);
Rd_VPR128.8H[0,16] = tmp4 + tmp5;
tmp2 = TMPQ1[16,8];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[24,8];
tmp5 = sext(tmp3);
Rd_VPR128.8H[16,16] = tmp4 + tmp5;
tmp2 = TMPQ1[32,8];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[40,8];
tmp5 = sext(tmp3);
Rd_VPR128.8H[32,16] = tmp4 + tmp5;
tmp2 = TMPQ1[48,8];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[56,8];
tmp5 = sext(tmp3);
Rd_VPR128.8H[48,16] = tmp4 + tmp5;
tmp2 = TMPQ1[64,8];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[72,8];
tmp5 = sext(tmp3);
Rd_VPR128.8H[64,16] = tmp4 + tmp5;
tmp2 = TMPQ1[80,8];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[88,8];
tmp5 = sext(tmp3);
Rd_VPR128.8H[80,16] = tmp4 + tmp5;
tmp2 = TMPQ1[96,8];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[104,8];
tmp5 = sext(tmp3);
Rd_VPR128.8H[96,16] = tmp4 + tmp5;
tmp2 = TMPQ1[112,8];
tmp4 = sext(tmp2);
tmp3 = TMPQ1[120,8];
tmp5 = sext(tmp3);
Rd_VPR128.8H[112,16] = tmp4 + tmp5;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.231 SADDLV page C7-1917 line 107472 MATCH x0e303800/mask=xbf3ffc00
# CONSTRUCT x4eb03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@4
# AUNIT --inst x4eb03800/mask=xfffffc00 --status nopcodeop --comment "ext"
:saddlv Rd_FPR64, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.4S & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_saddlv(Rn_VPR128.4S, 4:1);
}
# C7.2.231 SADDLV page C7-1917 line 107472 MATCH x0e303800/mask=xbf3ffc00
# CONSTRUCT x4e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@1
# AUNIT --inst x4e303800/mask=xfffffc00 --status nopcodeop --comment "ext"
:saddlv Rd_FPR16, Rn_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.16B & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_saddlv(Rn_VPR128.16B, 1:1);
}
# C7.2.231 SADDLV page C7-1917 line 107472 MATCH x0e303800/mask=xbf3ffc00
# CONSTRUCT x0e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@1
# AUNIT --inst x0e303800/mask=xfffffc00 --status nopcodeop --comment "ext"
:saddlv Rd_FPR16, Rn_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.8B & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_saddlv(Rn_VPR64.8B, 1:1);
}
# C7.2.231 SADDLV page C7-1917 line 107472 MATCH x0e303800/mask=xbf3ffc00
# CONSTRUCT x0e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@2
# AUNIT --inst x0e703800/mask=xfffffc00 --status nopcodeop --comment "ext"
:saddlv Rd_FPR32, Rn_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.4H & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_saddlv(Rn_VPR64.4H, 2:1);
}
# C7.2.231 SADDLV page C7-1917 line 107472 MATCH x0e303800/mask=xbf3ffc00
# CONSTRUCT x4e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@2
# AUNIT --inst x4e703800/mask=xfffffc00 --status nopcodeop --comment "ext"
:saddlv Rd_FPR32, Rn_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.8H & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_saddlv(Rn_VPR128.8H, 2:1);
}
# C7.2.232 SADDW, SADDW2 page C7-1919 line 107570 MATCH x0e201000/mask=xbf20fc00
# CONSTRUCT x0ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $sext@4:16 =$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw/2@4
# AUNIT --inst x0ea01000/mask=xffe0fc00 --status pass --comment "ext"
:saddw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rm_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rm_VPR64.2S[32,32]);
# simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.232 SADDW, SADDW2 page C7-1919 line 107570 MATCH x0e201000/mask=xbf20fc00
# CONSTRUCT x0e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $sext@2:16 =$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw/2@2
# AUNIT --inst x0e601000/mask=xffe0fc00 --status pass --comment "ext"
:saddw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rm_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rm_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rm_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rm_VPR64.4H[48,16]);
# simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.232 SADDW, SADDW2 page C7-1919 line 107570 MATCH x0e201000/mask=xbf20fc00
# CONSTRUCT x0e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $sext@1:16 =$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw/2@1
# AUNIT --inst x0e201000/mask=xffe0fc00 --status pass --comment "ext"
:saddw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = sext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = sext(Rm_VPR64.8B[0,8]);
TMPQ1[16,16] = sext(Rm_VPR64.8B[8,8]);
TMPQ1[32,16] = sext(Rm_VPR64.8B[16,8]);
TMPQ1[48,16] = sext(Rm_VPR64.8B[24,8]);
TMPQ1[64,16] = sext(Rm_VPR64.8B[32,8]);
TMPQ1[80,16] = sext(Rm_VPR64.8B[40,8]);
TMPQ1[96,16] = sext(Rm_VPR64.8B[48,8]);
TMPQ1[112,16] = sext(Rm_VPR64.8B[56,8]);
# simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.232 SADDW, SADDW2 page C7-1919 line 107570 MATCH x0e201000/mask=xbf20fc00
# CONSTRUCT x4ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@4:16 =$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw2/2@4
# AUNIT --inst x4ea01000/mask=xffe0fc00 --status pass --comment "ext"
:saddw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
TMPD1 = Rm_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
# simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ2[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.232 SADDW, SADDW2 page C7-1919 line 107570 MATCH x0e201000/mask=xbf20fc00
# CONSTRUCT x4e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@2:16 =$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw2/2@2
# AUNIT --inst x4e601000/mask=xffe0fc00 --status pass --comment "ext"
:saddw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
TMPD1 = Rm_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
# simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ2[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ2[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ2[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.232 SADDW, SADDW2 page C7-1919 line 107570 MATCH x0e201000/mask=xbf20fc00
# CONSTRUCT x4e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@1:16 =$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw2/2@1
# AUNIT --inst x4e201000/mask=xffe0fc00 --status pass --comment "ext"
:saddw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
TMPD1 = Rm_VPR128.16B[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = sext(TMPD1[0,8]);
TMPQ2[16,16] = sext(TMPD1[8,8]);
TMPQ2[32,16] = sext(TMPD1[16,8]);
TMPQ2[48,16] = sext(TMPD1[24,8]);
TMPQ2[64,16] = sext(TMPD1[32,8]);
TMPQ2[80,16] = sext(TMPD1[40,8]);
TMPQ2[96,16] = sext(TMPD1[48,8]);
TMPQ2[112,16] = sext(TMPD1[56,8]);
# simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ2 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ2[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ2[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ2[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ2[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ2[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ2[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ2[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ2[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.233 SCVTF (vector, fixed-point) page C7-1921 line 107690 MATCH x5f00e400/mask=xff80fc00
# CONSTRUCT x5f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2
# AUNIT --inst x5f40e400/mask=xffc0fc00 --status nopcodeop --comment "nofpround"
:scvtf Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_3031=1 & u=0 & b_2428=0x1f & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_scvtf(Rn_FPR64, Imm_shr_imm64:4);
}
# C7.2.233 SCVTF (vector, fixed-point) page C7-1921 line 107690 MATCH x5f00e400/mask=xff80fc00
# CONSTRUCT x5f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2
# AUNIT --inst x5f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround"
:scvtf Rd_FPR32, Rn_FPR32, Imm_shr_imm32
is b_3031=1 & u=0 & b_2428=0x1f & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_scvtf(Rn_FPR32, Imm_shr_imm32:4);
}
# C7.2.233 SCVTF (vector, fixed-point) page C7-1921 line 107690 MATCH x5f00e400/mask=xff80fc00
# CONSTRUCT x5f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2
# AUNIT --inst x5f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround"
:scvtf Rd_FPR16, Rn_FPR16, Imm_shr_imm16
is b_3031=1 & u=0 & b_2428=0x1f & b_2023=1 & Imm_shr_imm16 & b_1115=0x1c & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_scvtf(Rn_FPR16, Imm_shr_imm16:4);
}
# C7.2.233 SCVTF (vector, fixed-point) page C7-1921 line 107690 MATCH x0f00e400/mask=xbf80fc00
# CONSTRUCT x4f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@8
# AUNIT --inst x4f40e400/mask=xffc0fc00 --status nopcodeop --comment "nofpround"
:scvtf Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_scvtf(Rn_VPR128.2D, Imm_shr_imm64:4, 8:1);
}
# C7.2.233 SCVTF (vector, fixed-point) page C7-1921 line 107690 MATCH x0f00e400/mask=xbf80fc00
# CONSTRUCT x0f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@4
# AUNIT --inst x0f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround"
:scvtf Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_scvtf(Rn_VPR64.2S, Imm_shr_imm32:4, 4:1);
}
# C7.2.233 SCVTF (vector, fixed-point) page C7-1921 line 107690 MATCH x0f00e400/mask=xbf80fc00
# CONSTRUCT x4f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@4
# AUNIT --inst x4f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround"
:scvtf Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_scvtf(Rn_VPR128.4S, Imm_shr_imm32:4, 4:1);
}
# C7.2.233 SCVTF (vector, fixed-point) page C7-1921 line 107690 MATCH x0f00e400/mask=xbf80fc00
# CONSTRUCT x0f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@2
# AUNIT --inst x0f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround"
:scvtf Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm32
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_scvtf(Rn_VPR64.4H, Imm_shr_imm32:4, 2:1);
}
# C7.2.233 SCVTF (vector, fixed-point) page C7-1921 line 107690 MATCH x0f00e400/mask=xbf80fc00
# CONSTRUCT x4f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@2
# AUNIT --inst x4f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround"
:scvtf Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm32
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_scvtf(Rn_VPR128.8H, Imm_shr_imm32:4, 2:1);
}
# C7.2.234 SCVTF (vector, integer) page C7-1924 line 107840 MATCH x5e21d800/mask=xffbffc00
# CONSTRUCT x5e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =int2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
# AUNIT --inst x5e21d800/mask=xfffffc00 --status fail --comment "nofpround"
:scvtf Rd_FPR32, Rn_FPR32
is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = int2float(Rn_FPR32);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.234 SCVTF (vector, integer) page C7-1924 line 107840 MATCH x5e21d800/mask=xffbffc00
# CONSTRUCT x5e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =int2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
# AUNIT --inst x5e61d800/mask=xfffffc00 --status pass --comment "nofpround"
:scvtf Rd_FPR64, Rn_FPR64
is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = int2float(Rn_FPR64);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.234 SCVTF (vector, integer) page C7-1924 line 107840 MATCH x0e21d800/mask=xbfbffc00
# CONSTRUCT x4e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@8
# AUNIT --inst x4e61d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
:scvtf Rd_VPR128.2D, Rn_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=0 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_scvtf(Rn_VPR128.2D, 8:1);
}
# C7.2.234 SCVTF (vector, integer) page C7-1924 line 107840 MATCH x0e21d800/mask=xbfbffc00
# CONSTRUCT x0e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@4
# AUNIT --inst x0e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
:scvtf Rd_VPR64.2S, Rn_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_scvtf(Rn_VPR64.2S, 4:1);
}
# C7.2.234 SCVTF (vector, integer) page C7-1924 line 107840 MATCH x0e21d800/mask=xbfbffc00
# CONSTRUCT x4e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@4
# AUNIT --inst x4e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
:scvtf Rd_VPR128.4S, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_scvtf(Rn_VPR128.4S, 4:1);
}
# C7.2.234 SCVTF (vector, integer) page C7-1924 line 107840 MATCH x5e79d800/mask=xfffffc00
# CONSTRUCT x5e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =int2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
# AUNIT --inst x5e79d800/mask=xfffffc00 --status noqemu --comment "nofpround"
# Scalar half precision variant
:scvtf Rd_FPR16, Rn_FPR16
is b_1031=0b0101111001111001110110 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = int2float(Rn_FPR16);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.234 SCVTF (vector, integer) page C7-1924 line 107840 MATCH x0e79d800/mask=xbffffc00
# CONSTRUCT x0e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@2
# AUNIT --inst x0e79d800/mask=xfffffc00 --status noqemu --comment "nofpround"
# Vector half precision variant when Q=0 suf=VPR64.4H
:scvtf Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_1029=0b00111001111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_scvtf(Rn_VPR64.4H, 2:1);
}
# C7.2.234 SCVTF (vector, integer) page C7-1924 line 107840 MATCH x0e79d800/mask=xbffffc00
# CONSTRUCT x4e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@2
# AUNIT --inst x4e79d800/mask=xfffffc00 --status noqemu --comment "nofpround"
# Vector half precision variant when Q=1 suf=VPR128.8H
:scvtf Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_1029=0b00111001111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_scvtf(Rn_VPR128.8H, 2:1);
}
# C7.2.235 SCVTF (scalar, fixed-point) page C7-1927 line 108018 MATCH x1e020000/mask=x7f3f0000
# CONSTRUCT x1ec28000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 int2float:2 FBits16 =f/
# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_scvtf/2
# AUNIT --inst x1ec28000/mask=xffff8000 --status noqemu --comment "nofpround"
# 32-bit to half-precision variant when sf == 0 && type == 11
:scvtf Rd_FPR16, Rn_GPR32, FBitsOp
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=2 & b_15=1 & FBitsOp & FBits16 & Rn_GPR32 & Rd_FPR16 & Zd
{
local tmp1:2 = int2float(Rn_GPR32);
Rd_FPR16 = tmp1 f/ FBits16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.235 SCVTF (scalar, fixed-point) page C7-1927 line 108018 MATCH x1e020000/mask=x7f3f0000
# CONSTRUCT x9ec20000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 int2float:2 FBits16 =f/
# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_scvtf/2
# AUNIT --inst x9ec20000/mask=xffff0000 --status noqemu --comment "nofpround"
# 64-bit to half-precision variant when sf == 1 && type == 11
:scvtf Rd_FPR16, Rn_GPR64, FBitsOp
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=2 & FBitsOp & FBits16 & Rn_GPR64 & Rd_FPR16 & Zd
{
local tmp1:2 = int2float(Rn_GPR64);
Rd_FPR16 = tmp1 f/ FBits16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.235 SCVTF (scalar, fixed-point) page C7-1927 line 108018 MATCH x1e020000/mask=x7f3f0000
# CONSTRUCT x1e428000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 int2float:8 FBits64 =f/
# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_scvtf/2
# AUNIT --inst x1e428000/mask=xffff8000 --status pass --comment "nofpround"
:scvtf Rd_FPR64, Rn_GPR32, FBitsOp
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=2 & b_15=1 & FBitsOp & FBits64 & Rn_GPR32 & Rd_FPR64 & Zd
{
local tmp1:8 = int2float(Rn_GPR32);
Rd_FPR64 = tmp1 f/ FBits64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.235 SCVTF (scalar, fixed-point) page C7-1927 line 108018 MATCH x1e020000/mask=x7f3f0000
# CONSTRUCT x1e028000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 int2float FBits32 =f/
# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_scvtf/2
# AUNIT --inst x1e028000/mask=xffff8000 --status fail --comment "nofpround"
:scvtf Rd_FPR32, Rn_GPR32, FBitsOp
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=2 & b_15=1 & FBitsOp & FBits32 & Rn_GPR32 & Rd_FPR32 & Zd
{
local tmp1:4 = int2float(Rn_GPR32);
Rd_FPR32 = tmp1 f/ FBits32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.235 SCVTF (scalar, fixed-point) page C7-1927 line 108018 MATCH x1e020000/mask=x7f3f0000
# CONSTRUCT x9e420000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 int2float FBits64 =f/
# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_scvtf/2
# AUNIT --inst x9e420000/mask=xffff0000 --status fail --comment "nofpround"
:scvtf Rd_FPR64, Rn_GPR64, FBitsOp
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=2 & FBitsOp & FBits64 & Rn_GPR64 & Rd_FPR64 & Zd
{
local tmp1:8 = int2float(Rn_GPR64);
Rd_FPR64 = tmp1 f/ FBits64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.235 SCVTF (scalar, fixed-point) page C7-1927 line 108018 MATCH x1e020000/mask=x7f3f0000
# CONSTRUCT x9e020000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 int2float:4 FBits32 =f/
# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_scvtf/2
# AUNIT --inst x9e020000/mask=xffff0000 --status fail --comment "nofpround"
:scvtf Rd_FPR32, Rn_GPR64, FBitsOp
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=2 & FBitsOp & FBits32 & Rn_GPR64 & Rd_FPR32 & Rd_FPR64 & Zd
{
local tmp1:4 = int2float(Rn_GPR64);
Rd_FPR32 = tmp1 f/ FBits32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.236 SCVTF (scalar, integer) page C7-1929 line 108148 MATCH x1e220000/mask=x7f3ffc00
# CONSTRUCT x1ee20000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =int2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
# AUNIT --inst x1ee20000/mask=xfffffc00 --status noqemu --comment "nofpround"
:scvtf Rd_FPR16, Rn_GPR32
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR32 & Rd_FPR16 & Zd
{
Rd_FPR16 = int2float(Rn_GPR32);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.236 SCVTF (scalar, integer) page C7-1929 line 108148 MATCH x1e220000/mask=x7f3ffc00
# CONSTRUCT x9ee20000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =int2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
# AUNIT --inst x9ee20000/mask=xfffffc00 --status noqemu --comment "nofpround"
:scvtf Rd_FPR16, Rn_GPR64
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR64 & Rd_FPR16 & Zd
{
Rd_FPR16 = int2float(Rn_GPR64);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.236 SCVTF (scalar, integer) page C7-1929 line 108148 MATCH x1e220000/mask=x7f3ffc00
# CONSTRUCT x1e620000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =int2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
# AUNIT --inst x1e620000/mask=xfffffc00 --status pass --comment "nofpround"
:scvtf Rd_FPR64, Rn_GPR32
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR32 & Rd_FPR64 & Zd
{
Rd_FPR64 = int2float(Rn_GPR32);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.236 SCVTF (scalar, integer) page C7-1929 line 108148 MATCH x1e220000/mask=x7f3ffc00
# CONSTRUCT x9e620000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =int2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
# AUNIT --inst x9e620000/mask=xfffffc00 --status pass --comment "nofpround"
:scvtf Rd_FPR64, Rn_GPR64
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = int2float(Rn_GPR64);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.236 SCVTF (scalar, integer) page C7-1929 line 108148 MATCH x1e220000/mask=x7f3ffc00
# CONSTRUCT x1e220000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =int2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
# AUNIT --inst x1e220000/mask=xfffffc00 --status fail --comment "nofpround"
:scvtf Rd_FPR32, Rn_GPR32
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = int2float(Rn_GPR32);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.236 SCVTF (scalar, integer) page C7-1929 line 108148 MATCH x1e220000/mask=x7f3ffc00
# CONSTRUCT x9e220000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =int2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
# AUNIT --inst x9e220000/mask=xfffffc00 --status fail --comment "nofpround"
:scvtf Rd_FPR32, Rn_GPR64
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR64 & Rd_FPR32 & Zd
{
Rd_FPR32 = int2float(Rn_GPR64);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.237 SDOT (by element) page C7-1931 line 108271 MATCH x0f00e000/mask=xbf00f400
# CONSTRUCT x0f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_sdot/2@1
# AUNIT --inst x0f80e000/mask=xffc0f400 --status noqemu
# Vector variant when Q=0 Ta=64.2S Tb=64.8B
:sdot Rd_VPR64.2S, Rn_VPR64.8B, Re_VPR128.B.vIndex
is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR64.2S & Rn_VPR64.8B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd
{
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
Rd_VPR64.2S = NEON_sdot(Rn_VPR64.8B, tmp1, 1:1);
}
# C7.2.237 SDOT (by element) page C7-1931 line 108271 MATCH x0f00e000/mask=xbf00f400
# CONSTRUCT x4f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_sdot/2@1
# AUNIT --inst x4f80e000/mask=xffc0f400 --status noqemu
# Vector variant when Q=1 Ta=128.4S Tb=128.16B
:sdot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.B.vIndex
is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR128.4S & Rn_VPR128.16B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd
{
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
Rd_VPR128.4S = NEON_sdot(Rn_VPR128.16B, tmp1, 1:1);
}
# C7.2.238 SDOT (vector) page C7-1933 line 108370 MATCH x0e009400/mask=xbf20fc00
# CONSTRUCT x0e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sdot/2@1
# AUNIT --inst x0e809400/mask=xffe0fc00 --status noqemu
# Three registers of the same type variant when Q=0 Ta=64.2S Tb=64.8B
:sdot Rd_VPR64.2S, Rn_VPR64.8B, Rm_VPR64.8B
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR64.2S & Rn_VPR64.8B & Rm_VPR64.8B & Zd
{
Rd_VPR64.2S = NEON_sdot(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.238 SDOT (vector) page C7-1933 line 108370 MATCH x0e009400/mask=xbf20fc00
# CONSTRUCT x4e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sdot/2@1
# AUNIT --inst x4e809400/mask=xffe0fc00 --status noqemu
# Three registers of the same type variant when Q=1 Ta=128.4S Tb=128.16B
:sdot Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR128.4S & Rn_VPR128.16B & Rm_VPR128.16B & Zd
{
Rd_VPR128.4S = NEON_sdot(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.239 SHA1C page C7-1935 line 108468 MATCH x5e000000/mask=xffe0fc00
# CONSTRUCT x5e000000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1c/3@4
# AUNIT --inst x5e000000/mask=xffe0fc00 --status noqemu
:sha1c Rd_VPR128, Rn_FPR32, Rm_VPR128.4S
is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b000000 & Rn_FPR32 & Rd_VPR128 & Zd
{
Rd_VPR128 = NEON_sha1c(Rd_VPR128, Rn_FPR32, Rm_VPR128.4S, 4:1);
}
# C7.2.240 SHA1H page C7-1936 line 108537 MATCH x5e280800/mask=xfffffc00
# CONSTRUCT x5e280800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 30:1 =<<
# SMACRO(pseudo) ARG1 ARG2 =NEON_sha1h/1
# AUNIT --inst x5e280800/mask=xfffffc00 --status noqemu
:sha1h Rd_FPR32, Rn_FPR32
is b_2431=0b01011110 & b_2223=0b00 & b_1721=0b10100 & b_1216=0b00000 & b_1011=0b10 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = Rn_FPR32 << 30:1;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.241 SHA1M page C7-1937 line 108594 MATCH x5e002000/mask=xffe0fc00
# CONSTRUCT x5e002000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1m/3@4
# AUNIT --inst x5e002000/mask=xffe0fc00 --status noqemu
:sha1m Rd_VPR128, Rn_FPR32, Rm_VPR128.4S
is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b001000 & Rn_FPR32 & Rd_VPR128 & Zd
{
Rd_VPR128 = NEON_sha1m(Rd_VPR128, Rn_FPR32, Rm_VPR128.4S, 4:1);
}
# C7.2.242 SHA1P page C7-1938 line 108663 MATCH x5e001000/mask=xffe0fc00
# CONSTRUCT x5e001000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1p/3@4
# AUNIT --inst x5e001000/mask=xffe0fc00 --status noqemu
:sha1p Rd_VPR128, Rn_FPR32, Rm_VPR128.4S
is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b000100 & Rn_FPR32 & Rd_VPR128 & Zd
{
Rd_VPR128 = NEON_sha1p(Rd_VPR128, Rn_FPR32, Rm_VPR128.4S, 4:1);
}
# C7.2.243 SHA1SU0 page C7-1939 line 108732 MATCH x5e003000/mask=xffe0fc00
# CONSTRUCT x5e003000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1su0/3@4
# AUNIT --inst x5e003000/mask=xffe0fc00 --status noqemu
:sha1su0 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b001100 & Rn_VPR128.4S & Rd_VPR128.4S & Rd_VPR128 & Zd
{
Rd_VPR128.4S = NEON_sha1su0(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.244 SHA1SU1 page C7-1940 line 108798 MATCH x5e281800/mask=xfffffc00
# CONSTRUCT x5e281800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sha1su1/2@4
# AUNIT --inst x5e281800/mask=xfffffc00 --status noqemu
:sha1su1 Rd_VPR128.4S, Rn_VPR128.4S
is b_2431=0b01011110 & b_2223=0b00 & b_2121=1 & b_1620=0b01000 & b_1015=0b000110 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sha1su1(Rd_VPR128.4S, Rn_VPR128.4S, 4:1);
}
# C7.2.245 SHA256H2 page C7-1941 line 108862 MATCH x5e005000/mask=xffe0fc00
# CONSTRUCT x5e005000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha256h2/3@4
# AUNIT --inst x5e005000/mask=xffe0fc00 --status noqemu
:sha256h2 Rd_VPR128, Rn_VPR128, Rm_VPR128.4S
is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b010100 & Rn_VPR128 & Rd_VPR128 & Zd
{
Rd_VPR128 = NEON_sha256h2(Rd_VPR128, Rn_VPR128, Rm_VPR128.4S, 4:1);
}
# C7.2.246 SHA256H page C7-1942 line 108922 MATCH x5e004000/mask=xffe0fc00
# CONSTRUCT x5e004000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha256h/3@4
# AUNIT --inst x5e004000/mask=xffe0fc00 --status noqemu
:sha256h Rd_VPR128, Rn_VPR128, Rm_VPR128.4S
is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b010000 & Rn_VPR128 & Rd_VPR128 & Zd
{
Rd_VPR128 = NEON_sha256h(Rd_VPR128, Rn_VPR128, Rm_VPR128.4S, 4:1);
}
# C7.2.247 SHA256SU0 page C7-1943 line 108982 MATCH x5e282800/mask=xfffffc00
# CONSTRUCT x5e282800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sha256su0/2@4
# AUNIT --inst x5e282800/mask=xfffffc00 --status noqemu
:sha256su0 Rd_VPR128.4S, Rn_VPR128.4S
is b_2431=0b01011110 & b_2223=0b00 & b_2121=1 & b_1620=0b01000 & b_1015=0b001010 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sha256su0(Rd_VPR128.4S, Rn_VPR128.4S, 4:1);
}
# C7.2.248 SHA256SU1 page C7-1944 line 109048 MATCH x5e006000/mask=xffe0fc00
# CONSTRUCT x5e006000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha256su1/3@4
# AUNIT --inst x5e006000/mask=xffe0fc00 --status noqemu
:sha256su1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b011000 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sha256su1(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.249 SHA512H page C7-1946 line 109138 MATCH xce608000/mask=xffe0fc00
# CONSTRUCT xce608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha512h/3@8
# AUNIT --inst xce608000/mask=xffe0fc00 --status noqemu
:sha512h Rd_VPR128, Rn_VPR128, Rm_VPR128.2D
is b_2131=0b11001110011 & b_1015=0b100000 & Rd_VPR128 & Rn_VPR128 & Rm_VPR128.2D & Zd
{
Rd_VPR128 = NEON_sha512h(Rd_VPR128, Rn_VPR128, Rm_VPR128.2D, 8:1);
}
# C7.2.250 SHA512H2 page C7-1948 line 109227 MATCH xce608400/mask=xffe0fc00
# CONSTRUCT xce608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha512h2/3@8
# AUNIT --inst xce608400/mask=xffe0fc00 --status noqemu
:sha512h2 Rd_VPR128, Rn_VPR128, Rm_VPR128.2D
is b_2131=0b11001110011 & b_1015=0b100001 & Rd_VPR128 & Rn_VPR128 & Rm_VPR128.2D & Zd
{
Rd_VPR128 = NEON_sha512h2(Rd_VPR128, Rn_VPR128, Rm_VPR128.2D, 8:1);
}
# C7.2.251 SHA512SU0 page C7-1950 line 109313 MATCH xcec08000/mask=xfffffc00
# CONSTRUCT xcec08000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sha512su0/2@8
# AUNIT --inst xcec08000/mask=xfffffc00 --status noqemu
:sha512su0 Rd_VPR128.2D, Rn_VPR128.2D
is b_1031=0b1100111011000000100000 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_sha512su0(Rd_VPR128.2D, Rn_VPR128.2D, 8:1);
}
# C7.2.252 SHA512SU1 page C7-1951 line 109383 MATCH xce608800/mask=xffe0fc00
# CONSTRUCT xce608800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha512su1/3@8
# AUNIT --inst xce608800/mask=xffe0fc00 --status noqemu
:sha512su1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_2131=0b11001110011 & b_1015=0b100010 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_sha512su1(Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.253 SHADD page C7-1953 line 109467 MATCH x0e200400/mask=xbf20fc00
# CONSTRUCT x4e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@1
# AUNIT --inst x4e200400/mask=xffe0fc00 --status nopcodeop
:shadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_shadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.253 SHADD page C7-1953 line 109467 MATCH x0e200400/mask=xbf20fc00
# CONSTRUCT x0ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@4
# AUNIT --inst x0ea00400/mask=xffe0fc00 --status nopcodeop
:shadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_shadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.253 SHADD page C7-1953 line 109467 MATCH x0e200400/mask=xbf20fc00
# CONSTRUCT x0e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@2
# AUNIT --inst x0e600400/mask=xffe0fc00 --status nopcodeop
:shadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_shadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.253 SHADD page C7-1953 line 109467 MATCH x0e200400/mask=xbf20fc00
# CONSTRUCT x4ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@4
# AUNIT --inst x4ea00400/mask=xffe0fc00 --status nopcodeop
:shadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_shadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.253 SHADD page C7-1953 line 109467 MATCH x0e200400/mask=xbf20fc00
# CONSTRUCT x0e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@1
# AUNIT --inst x0e200400/mask=xffe0fc00 --status nopcodeop
:shadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_shadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.253 SHADD page C7-1953 line 109467 MATCH x0e200400/mask=xbf20fc00
# CONSTRUCT x4e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@2
# AUNIT --inst x4e600400/mask=xffe0fc00 --status nopcodeop
:shadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_shadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.254 SHL page C7-1955 line 109567 MATCH x5f005400/mask=xff80fc00
# CONSTRUCT x5f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2
# AUNIT --inst x5f405400/mask=xffc0fc00 --status nopcodeop
:shl Rd_FPR64, Rn_FPR64, Imm_imm0_63
is b_3031=1 & u=0 & b_2428=0x1f & b_2223=0b01 & Imm_imm0_63 & b_1115=0xa & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_shl(Rn_FPR64, Imm_imm0_63:1);
}
# C7.2.254 SHL page C7-1955 line 109567 MATCH x0f005400/mask=xbf80fc00
# CONSTRUCT x4f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:1 =$<<@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@1
# AUNIT --inst x4f085400/mask=xfff8fc00 --status pass
:shl Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
local tmp1:1 = Imm_uimm3;
# simd infix Rd_VPR128.16B = Rn_VPR128.16B << tmp1 on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] << tmp1;
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] << tmp1;
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] << tmp1;
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] << tmp1;
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] << tmp1;
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] << tmp1;
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] << tmp1;
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] << tmp1;
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] << tmp1;
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] << tmp1;
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] << tmp1;
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] << tmp1;
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] << tmp1;
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] << tmp1;
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] << tmp1;
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] << tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.254 SHL page C7-1955 line 109567 MATCH x0f005400/mask=xbf80fc00
# CONSTRUCT x4f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:8 =$<<@8
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@8
# AUNIT --inst x4f405400/mask=xffc0fc00 --status pass
:shl Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
local tmp1:8 = Imm_imm0_63;
# simd infix Rd_VPR128.2D = Rn_VPR128.2D << tmp1 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] << tmp1;
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] << tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.254 SHL page C7-1955 line 109567 MATCH x0f005400/mask=xbf80fc00
# CONSTRUCT x0f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:4 =$<<@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@4
# AUNIT --inst x0f205400/mask=xffe0fc00 --status pass
:shl Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
local tmp1:4 = Imm_uimm5;
# simd infix Rd_VPR64.2S = Rn_VPR64.2S << tmp1 on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] << tmp1;
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] << tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.254 SHL page C7-1955 line 109567 MATCH x0f005400/mask=xbf80fc00
# CONSTRUCT x0f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:2 =$<<@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@2
# AUNIT --inst x0f105400/mask=xfff0fc00 --status pass
:shl Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
local tmp1:2 = Imm_uimm4;
# simd infix Rd_VPR64.4H = Rn_VPR64.4H << tmp1 on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] << tmp1;
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] << tmp1;
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] << tmp1;
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] << tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.254 SHL page C7-1955 line 109567 MATCH x0f005400/mask=xbf80fc00
# CONSTRUCT x4f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:4 =$<<@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@4
# AUNIT --inst x4f205400/mask=xffe0fc00 --status pass
:shl Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
local tmp1:4 = Imm_uimm5;
# simd infix Rd_VPR128.4S = Rn_VPR128.4S << tmp1 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] << tmp1;
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] << tmp1;
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] << tmp1;
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] << tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.254 SHL page C7-1955 line 109567 MATCH x0f005400/mask=xbf80fc00
# CONSTRUCT x0f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:1 =$<<@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@1
# AUNIT --inst x0f085400/mask=xfff8fc00 --status pass
:shl Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
local tmp1:1 = Imm_uimm3;
# simd infix Rd_VPR64.8B = Rn_VPR64.8B << tmp1 on lane size 1
Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] << tmp1;
Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] << tmp1;
Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] << tmp1;
Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] << tmp1;
Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] << tmp1;
Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] << tmp1;
Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] << tmp1;
Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] << tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.254 SHL page C7-1955 line 109567 MATCH x0f005400/mask=xbf80fc00
# CONSTRUCT x4f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:2 =$<<@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@2
# AUNIT --inst x4f105400/mask=xfff0fc00 --status pass
:shl Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
local tmp1:2 = Imm_uimm4;
# simd infix Rd_VPR128.8H = Rn_VPR128.8H << tmp1 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] << tmp1;
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] << tmp1;
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] << tmp1;
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] << tmp1;
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] << tmp1;
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] << tmp1;
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] << tmp1;
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] << tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.255 SHLL, SHLL2 page C7-1957 line 109703 MATCH x2e213800/mask=xbf3ffc00
# CONSTRUCT x2ea13800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 zext:8 =$<<@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll/2@4
# AUNIT --inst x2ea13800/mask=xfffffc00 --status pass --comment "ext"
:shll Rd_VPR128.2D, Rn_VPR64.2S, Imm_uimm_exact32
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & Imm_uimm_exact32 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
local tmp2:8 = zext(Imm_uimm_exact32);
# simd infix Rd_VPR128.2D = TMPQ1 << tmp2 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64] << tmp2;
Rd_VPR128.2D[64,64] = TMPQ1[64,64] << tmp2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.255 SHLL, SHLL2 page C7-1957 line 109703 MATCH x2e213800/mask=xbf3ffc00
# CONSTRUCT x2e613800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3:4 =$<<@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll/2@2
# AUNIT --inst x2e613800/mask=xfffffc00 --status pass --comment "ext"
:shll Rd_VPR128.4S, Rn_VPR64.4H, Imm_uimm_exact16
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & Imm_uimm_exact16 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd infix Rd_VPR128.4S = TMPQ1 << Imm_uimm_exact16:4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32] << Imm_uimm_exact16:4;
Rd_VPR128.4S[32,32] = TMPQ1[32,32] << Imm_uimm_exact16:4;
Rd_VPR128.4S[64,32] = TMPQ1[64,32] << Imm_uimm_exact16:4;
Rd_VPR128.4S[96,32] = TMPQ1[96,32] << Imm_uimm_exact16:4;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.255 SHLL, SHLL2 page C7-1957 line 109703 MATCH x2e213800/mask=xbf3ffc00
# CONSTRUCT x2e213800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@1:16 ARG3:2 =$<<@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll/2@1
# AUNIT --inst x2e213800/mask=xfffffc00 --status pass --comment "ext"
:shll Rd_VPR128.8H, Rn_VPR64.8B, Imm_uimm_exact8
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & Imm_uimm_exact8 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
# simd infix Rd_VPR128.8H = TMPQ1 << Imm_uimm_exact8:2 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[0,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[16,16] = TMPQ1[16,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[32,16] = TMPQ1[32,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[48,16] = TMPQ1[48,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[64,16] = TMPQ1[64,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[80,16] = TMPQ1[80,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[96,16] = TMPQ1[96,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[112,16] = TMPQ1[112,16] << Imm_uimm_exact8:2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.255 SHLL, SHLL2 page C7-1957 line 109703 MATCH x2e213800/mask=xbf3ffc00
# CONSTRUCT x6ea13800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 zext:8 =$<<@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll2/2@4
# AUNIT --inst x6ea13800/mask=xfffffc00 --status pass --comment "ext"
:shll2 Rd_VPR128.2D, Rn_VPR128.4S, Imm_uimm_exact32
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & Imm_uimm_exact32 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
local tmp3:8 = zext(Imm_uimm_exact32);
# simd infix Rd_VPR128.2D = TMPQ2 << tmp3 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ2[0,64] << tmp3;
Rd_VPR128.2D[64,64] = TMPQ2[64,64] << tmp3;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.255 SHLL, SHLL2 page C7-1957 line 109703 MATCH x2e213800/mask=xbf3ffc00
# CONSTRUCT x6e613800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3:4 =$<<@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll2/2@2
# AUNIT --inst x6e613800/mask=xfffffc00 --status pass --comment "ext"
:shll2 Rd_VPR128.4S, Rn_VPR128.8H, Imm_uimm_exact16
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & Imm_uimm_exact16 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
# simd infix Rd_VPR128.4S = TMPQ2 << Imm_uimm_exact16:4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ2[0,32] << Imm_uimm_exact16:4;
Rd_VPR128.4S[32,32] = TMPQ2[32,32] << Imm_uimm_exact16:4;
Rd_VPR128.4S[64,32] = TMPQ2[64,32] << Imm_uimm_exact16:4;
Rd_VPR128.4S[96,32] = TMPQ2[96,32] << Imm_uimm_exact16:4;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.255 SHLL, SHLL2 page C7-1957 line 109703 MATCH x2e213800/mask=xbf3ffc00
# CONSTRUCT x6e213800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3:2 =$<<@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll2/2@1
# AUNIT --inst x6e213800/mask=xfffffc00 --status pass --comment "ext"
:shll2 Rd_VPR128.8H, Rn_VPR128.16B, Imm_uimm_exact8
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & Imm_uimm_exact8 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = sext(TMPD1[0,8]);
TMPQ2[16,16] = sext(TMPD1[8,8]);
TMPQ2[32,16] = sext(TMPD1[16,8]);
TMPQ2[48,16] = sext(TMPD1[24,8]);
TMPQ2[64,16] = sext(TMPD1[32,8]);
TMPQ2[80,16] = sext(TMPD1[40,8]);
TMPQ2[96,16] = sext(TMPD1[48,8]);
TMPQ2[112,16] = sext(TMPD1[56,8]);
# simd infix Rd_VPR128.8H = TMPQ2 << Imm_uimm_exact8:2 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ2[0,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[16,16] = TMPQ2[16,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[32,16] = TMPQ2[32,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[48,16] = TMPQ2[48,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[64,16] = TMPQ2[64,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[80,16] = TMPQ2[80,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[96,16] = TMPQ2[96,16] << Imm_uimm_exact8:2;
Rd_VPR128.8H[112,16] = TMPQ2[112,16] << Imm_uimm_exact8:2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.256 SHRN, SHRN2 page C7-1959 line 109821 MATCH x0f008400/mask=xbf80fc00
# CONSTRUCT x0f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 =$zext@8:8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn/2@8
# AUNIT --inst x0f208400/mask=xffe0fc00 --status pass --comment "ext"
:shrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
local tmp1:8 = zext(Imm_shr_imm32);
# simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1;
TMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1;
# simd resize Rd_VPR64.2S = zext(TMPQ1) (lane size 8 to 4)
Rd_VPR64.2S[0,32] = TMPQ1[0,32];
Rd_VPR64.2S[32,32] = TMPQ1[64,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.256 SHRN, SHRN2 page C7-1959 line 109821 MATCH x0f008400/mask=xbf80fc00
# CONSTRUCT x0f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:4 $>>@4 =$zext@4:16
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn/2@4
# AUNIT --inst x0f108400/mask=xfff0fc00 --status pass --comment "ext"
:shrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S >> Imm_shr_imm16:4 on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] >> Imm_shr_imm16:4;
TMPQ1[32,32] = Rn_VPR128.4S[32,32] >> Imm_shr_imm16:4;
TMPQ1[64,32] = Rn_VPR128.4S[64,32] >> Imm_shr_imm16:4;
TMPQ1[96,32] = Rn_VPR128.4S[96,32] >> Imm_shr_imm16:4;
# simd resize Rd_VPR64.4H = zext(TMPQ1) (lane size 4 to 2)
Rd_VPR64.4H[0,16] = TMPQ1[0,16];
Rd_VPR64.4H[16,16] = TMPQ1[32,16];
Rd_VPR64.4H[32,16] = TMPQ1[64,16];
Rd_VPR64.4H[48,16] = TMPQ1[96,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.256 SHRN, SHRN2 page C7-1959 line 109821 MATCH x0f008400/mask=xbf80fc00
# CONSTRUCT x0f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 $>>@2 =$zext@2:8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn/2@2
# AUNIT --inst x0f088400/mask=xfff8fc00 --status pass --comment "ext"
:shrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm8:2 on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm8:2;
TMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm8:2;
TMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm8:2;
TMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm8:2;
TMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm8:2;
TMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm8:2;
TMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm8:2;
TMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm8:2;
# simd resize Rd_VPR64.8B = zext(TMPQ1) (lane size 2 to 1)
Rd_VPR64.8B[0,8] = TMPQ1[0,8];
Rd_VPR64.8B[8,8] = TMPQ1[16,8];
Rd_VPR64.8B[16,8] = TMPQ1[32,8];
Rd_VPR64.8B[24,8] = TMPQ1[48,8];
Rd_VPR64.8B[32,8] = TMPQ1[64,8];
Rd_VPR64.8B[40,8] = TMPQ1[80,8];
Rd_VPR64.8B[48,8] = TMPQ1[96,8];
Rd_VPR64.8B[56,8] = TMPQ1[112,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.256 SHRN, SHRN2 page C7-1959 line 109821 MATCH x0f008400/mask=xbf80fc00
# CONSTRUCT x4f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 $zext@8:8 1:1 &=$copy
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn2/2@8
# AUNIT --inst x4f208400/mask=xffe0fc00 --status pass --comment "ext"
:shrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
local tmp1:8 = zext(Imm_shr_imm32);
# simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1;
TMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1;
# simd resize TMPD2 = zext(TMPQ1) (lane size 8 to 4)
TMPD2[0,32] = TMPQ1[0,32];
TMPD2[32,32] = TMPQ1[64,32];
# simd copy Rd_VPR128.4S element 1:1 = TMPD2 (lane size 8)
Rd_VPR128.4S[64,64] = TMPD2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.256 SHRN, SHRN2 page C7-1959 line 109821 MATCH x0f008400/mask=xbf80fc00
# CONSTRUCT x4f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:4 $>>@4 $zext@4:8 1:1 &=$copy
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn2/2@4
# AUNIT --inst x4f108400/mask=xfff0fc00 --status pass --comment "ext"
:shrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S >> Imm_shr_imm16:4 on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] >> Imm_shr_imm16:4;
TMPQ1[32,32] = Rn_VPR128.4S[32,32] >> Imm_shr_imm16:4;
TMPQ1[64,32] = Rn_VPR128.4S[64,32] >> Imm_shr_imm16:4;
TMPQ1[96,32] = Rn_VPR128.4S[96,32] >> Imm_shr_imm16:4;
# simd resize TMPD2 = zext(TMPQ1) (lane size 4 to 2)
TMPD2[0,16] = TMPQ1[0,16];
TMPD2[16,16] = TMPQ1[32,16];
TMPD2[32,16] = TMPQ1[64,16];
TMPD2[48,16] = TMPQ1[96,16];
# simd copy Rd_VPR128.8H element 1:1 = TMPD2 (lane size 8)
Rd_VPR128.8H[64,64] = TMPD2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.256 SHRN, SHRN2 page C7-1959 line 109821 MATCH x0f008400/mask=xbf80fc00
# CONSTRUCT x4f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 $>>@2 $zext@2:8 1:1 &=$copy
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn2/2@2
# AUNIT --inst x4f088400/mask=xfff8fc00 --status pass --comment "ext"
:shrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm8:2 on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm8:2;
TMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm8:2;
TMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm8:2;
TMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm8:2;
TMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm8:2;
TMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm8:2;
TMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm8:2;
TMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm8:2;
# simd resize TMPD2 = zext(TMPQ1) (lane size 2 to 1)
TMPD2[0,8] = TMPQ1[0,8];
TMPD2[8,8] = TMPQ1[16,8];
TMPD2[16,8] = TMPQ1[32,8];
TMPD2[24,8] = TMPQ1[48,8];
TMPD2[32,8] = TMPQ1[64,8];
TMPD2[40,8] = TMPQ1[80,8];
TMPD2[48,8] = TMPQ1[96,8];
TMPD2[56,8] = TMPQ1[112,8];
# simd copy Rd_VPR128.16B element 1:1 = TMPD2 (lane size 8)
Rd_VPR128.16B[64,64] = TMPD2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.257 SHSUB page C7-1961 line 109944 MATCH x0e202400/mask=xbf20fc00
# CONSTRUCT x4e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@1
# AUNIT --inst x4e202400/mask=xffe0fc00 --status nopcodeop
:shsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_shsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.257 SHSUB page C7-1961 line 109944 MATCH x0e202400/mask=xbf20fc00
# CONSTRUCT x0ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@4
# AUNIT --inst x0ea02400/mask=xffe0fc00 --status nopcodeop
:shsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_shsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.257 SHSUB page C7-1961 line 109944 MATCH x0e202400/mask=xbf20fc00
# CONSTRUCT x0e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@2
# AUNIT --inst x0e602400/mask=xffe0fc00 --status nopcodeop
:shsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_shsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.257 SHSUB page C7-1961 line 109944 MATCH x0e202400/mask=xbf20fc00
# CONSTRUCT x4ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@4
# AUNIT --inst x4ea02400/mask=xffe0fc00 --status nopcodeop
:shsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_shsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.257 SHSUB page C7-1961 line 109944 MATCH x0e202400/mask=xbf20fc00
# CONSTRUCT x0e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@1
# AUNIT --inst x0e202400/mask=xffe0fc00 --status nopcodeop
:shsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_shsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.257 SHSUB page C7-1961 line 109944 MATCH x0e202400/mask=xbf20fc00
# CONSTRUCT x4e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@2
# AUNIT --inst x4e602400/mask=xffe0fc00 --status nopcodeop
:shsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_shsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.258 SLI page C7-1963 line 110042 MATCH x2f005400/mask=xbf80fc00
# CONSTRUCT x6f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@1
# AUNIT --inst x6f085400/mask=xfff8fc00 --status nopcodeop
:sli Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sli(Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3:1, 1:1);
}
# C7.2.258 SLI page C7-1963 line 110042 MATCH x2f005400/mask=xbf80fc00
# CONSTRUCT x6f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@8
# AUNIT --inst x6f405400/mask=xffc0fc00 --status nopcodeop
:sli Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_sli(Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63:1, 8:1);
}
# C7.2.258 SLI page C7-1963 line 110042 MATCH x2f005400/mask=xbf80fc00
# CONSTRUCT x2f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@4
# AUNIT --inst x2f205400/mask=xffe0fc00 --status nopcodeop
:sli Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sli(Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5:1, 4:1);
}
# C7.2.258 SLI page C7-1963 line 110042 MATCH x2f005400/mask=xbf80fc00
# CONSTRUCT x2f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@2
# AUNIT --inst x2f105400/mask=xfff0fc00 --status nopcodeop
:sli Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sli(Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4:1, 2:1);
}
# C7.2.258 SLI page C7-1963 line 110042 MATCH x2f005400/mask=xbf80fc00
# CONSTRUCT x6f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@4
# AUNIT --inst x6f205400/mask=xffe0fc00 --status nopcodeop
:sli Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sli(Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5:1, 4:1);
}
# C7.2.258 SLI page C7-1963 line 110042 MATCH x2f005400/mask=xbf80fc00
# CONSTRUCT x2f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@1
# AUNIT --inst x2f085400/mask=xfff8fc00 --status nopcodeop
:sli Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sli(Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3:1, 1:1);
}
# C7.2.258 SLI page C7-1963 line 110042 MATCH x2f005400/mask=xbf80fc00
# CONSTRUCT x6f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@2
# AUNIT --inst x6f105400/mask=xfff0fc00 --status nopcodeop
:sli Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sli(Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4:1, 2:1);
}
# C7.2.258 SLI page C7-1963 line 110042 MATCH x7f005400/mask=xff80fc00
# CONSTRUCT x7f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3
# AUNIT --inst x7f405400/mask=xffc0fc00 --status nopcodeop
:sli Rd_VPR64, Rn_VPR64, Imm_uimm5
is b_2331=0b011111110 & b_22=1 & b_1015=0b010101 & Rd_VPR64 & Rn_VPR64 & Imm_uimm5 & Zd
{
Rd_VPR64 = NEON_sli(Rd_VPR64, Rn_VPR64, Imm_uimm5:1);
}
# C7.2.259 SM3PARTW1 page C7-1966 line 110207 MATCH xce60c000/mask=xffe0fc00
# CONSTRUCT xce60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3partw1/3@4
# AUNIT --inst xce60c000/mask=xffe0fc00 --status noqemu
:sm3partw1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_2131=0b11001110011 & b_1015=0b110000 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sm3partw1(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.260 SM3PARTW2 page C7-1968 line 110294 MATCH xce60c400/mask=xffe0fc00
# CONSTRUCT xce60c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3partw2/3@4
# AUNIT --inst xce60c400/mask=xffe0fc00 --status noqemu
:sm3partw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_2131=0b11001110011 & b_1015=0b110001 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sm3partw2(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.261 SM3SS1 page C7-1970 line 110380 MATCH xce400000/mask=xffe08000
# CONSTRUCT xce400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_sm3ss1/3@4
# AUNIT --inst xce400000/mask=xffe08000 --status noqemu
:sm3ss1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, Ra_VPR128.4S
is b_2131=0b11001110010 & b_15=0 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Ra_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sm3ss1(Rn_VPR128.4S, Rm_VPR128.4S, Ra_VPR128.4S, 4:1);
}
# C7.2.247 SM3TT1A page C7-1529 line 88534 KEEPWITH
sm3imm2: b_1213 is b_1213 { export *[const]:4 b_1213; }
Re_VPR128.S.sm3imm2: Re_VPR128.S^"["^sm3imm2^"]" is Re_VPR128.S & sm3imm2 { export Re_VPR128.S; }
# C7.2.262 SM3TT1A page C7-1972 line 110466 MATCH xce408000/mask=xffe0cc00
# CONSTRUCT xce408000/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt1a/3@4
# AUNIT --inst xce408000/mask=xffe0cc00 --status noqemu
:sm3tt1a Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.sm3imm2
is b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b00 & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd
{
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1);
Rd_VPR128.4S = NEON_sm3tt1a(Rd_VPR128.4S, Rn_VPR128.4S, tmp1, 4:1);
}
# C7.2.263 SM3TT1B page C7-1974 line 110572 MATCH xce408400/mask=xffe0cc00
# CONSTRUCT xce408400/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt1b/3@4
# AUNIT --inst xce408400/mask=xffe0cc00 --status noqemu
:sm3tt1b Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.sm3imm2
is b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b01 & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd
{
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1);
Rd_VPR128.4S = NEON_sm3tt1b(Rd_VPR128.4S, Rn_VPR128.4S, tmp1, 4:1);
}
# C7.2.264 SM3TT2A page C7-1976 line 110678 MATCH xce408800/mask=xffe0cc00
# CONSTRUCT xce408800/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt2a/3@4
# AUNIT --inst xce408800/mask=xffe0cc00 --status noqemu
:sm3tt2a Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.sm3imm2
is b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b10 & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd
{
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1);
Rd_VPR128.4S = NEON_sm3tt2a(Rd_VPR128.4S, Rn_VPR128.4S, tmp1, 4:1);
}
# C7.2.265 SM3TT2B page C7-1978 line 110783 MATCH xce408c00/mask=xffe0cc00
# CONSTRUCT xce408c00/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt2b/3@4
# AUNIT --inst xce408c00/mask=xffe0cc00 --status noqemu
:sm3tt2b Rd_VPR128.S, Rn_VPR128.S, Re_VPR128.S.sm3imm2
is b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b11 & Rd_VPR128.S & Rn_VPR128.S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd
{
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1);
Rd_VPR128.S = NEON_sm3tt2b(Rd_VPR128.S, Rn_VPR128.S, tmp1, 4:1);
}
# C7.2.266 SM4E page C7-1980 line 110888 MATCH xcec08400/mask=xfffffc00
# CONSTRUCT xcec08400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sm4e/2@4
# AUNIT --inst xcec08400/mask=xfffffc00 --status noqemu
:sm4e Rd_VPR128.4S, Rn_VPR128.4S
is b_1031=0b1100111011000000100001 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sm4e(Rd_VPR128.4S, Rn_VPR128.4S, 4:1);
}
# C7.2.267 SM4EKEY page C7-1982 line 110982 MATCH xce60c800/mask=xffe0fc00
# CONSTRUCT xce60c800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm4ekey/3@4
# AUNIT --inst xce60c800/mask=xffe0fc00 --status noqemu
:sm4ekey Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_2131=0b11001110011 & b_1015=0b110010 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sm4ekey(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.268 SMAX page C7-1984 line 111078 MATCH x0e206400/mask=xbf20fc00
# CONSTRUCT x4e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@1
# AUNIT --inst x4e206400/mask=xffe0fc00 --status nopcodeop
:smax Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xc & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_smax(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.268 SMAX page C7-1984 line 111078 MATCH x0e206400/mask=xbf20fc00
# CONSTRUCT x0ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@4
# AUNIT --inst x0ea06400/mask=xffe0fc00 --status nopcodeop
:smax Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xc & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_smax(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.268 SMAX page C7-1984 line 111078 MATCH x0e206400/mask=xbf20fc00
# CONSTRUCT x0e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@2
# AUNIT --inst x0e606400/mask=xffe0fc00 --status nopcodeop
:smax Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xc & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_smax(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.268 SMAX page C7-1984 line 111078 MATCH x0e206400/mask=xbf20fc00
# CONSTRUCT x4ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@4
# AUNIT --inst x4ea06400/mask=xffe0fc00 --status nopcodeop
:smax Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xc & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_smax(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.268 SMAX page C7-1984 line 111078 MATCH x0e206400/mask=xbf20fc00
# CONSTRUCT x0e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@1
# AUNIT --inst x0e206400/mask=xffe0fc00 --status nopcodeop
:smax Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xc & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_smax(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.268 SMAX page C7-1984 line 111078 MATCH x0e206400/mask=xbf20fc00
# CONSTRUCT x4e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@2
# AUNIT --inst x4e606400/mask=xffe0fc00 --status nopcodeop
:smax Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xc & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_smax(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.269 SMAXP page C7-1986 line 111178 MATCH x0e20a400/mask=xbf20fc00
# CONSTRUCT x4e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@1
# AUNIT --inst x4e20a400/mask=xffe0fc00 --status nopcodeop
:smaxp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_smax(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.269 SMAXP page C7-1986 line 111178 MATCH x0e20a400/mask=xbf20fc00
# CONSTRUCT x0ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@4
# AUNIT --inst x0ea0a400/mask=xffe0fc00 --status nopcodeop
:smaxp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_smaxp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.269 SMAXP page C7-1986 line 111178 MATCH x0e20a400/mask=xbf20fc00
# CONSTRUCT x0e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@2
# AUNIT --inst x0e60a400/mask=xffe0fc00 --status nopcodeop
:smaxp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_smaxp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.269 SMAXP page C7-1986 line 111178 MATCH x0e20a400/mask=xbf20fc00
# CONSTRUCT x4ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@4
# AUNIT --inst x4ea0a400/mask=xffe0fc00 --status nopcodeop
:smaxp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_smaxp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.269 SMAXP page C7-1986 line 111178 MATCH x0e20a400/mask=xbf20fc00
# CONSTRUCT x0e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@1
# AUNIT --inst x0e20a400/mask=xffe0fc00 --status nopcodeop
:smaxp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_smaxp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.269 SMAXP page C7-1986 line 111178 MATCH x0e20a400/mask=xbf20fc00
# CONSTRUCT x4e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@2
# AUNIT --inst x4e60a400/mask=xffe0fc00 --status nopcodeop
:smaxp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_smaxp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.270 SMAXV page C7-1988 line 111280 MATCH x0e30a800/mask=xbf3ffc00
# CONSTRUCT x4e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@1
# AUNIT --inst x4e30a800/mask=xfffffc00 --status nopcodeop
:smaxv Rd_FPR8, Rn_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_smaxv(Rn_VPR128.16B, 1:1);
}
# C7.2.270 SMAXV page C7-1988 line 111280 MATCH x0e30a800/mask=xbf3ffc00
# CONSTRUCT x0e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@1
# AUNIT --inst x0e30a800/mask=xfffffc00 --status nopcodeop
:smaxv Rd_FPR8, Rn_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_smaxv(Rn_VPR64.8B, 1:1);
}
# C7.2.270 SMAXV page C7-1988 line 111280 MATCH x0e30a800/mask=xbf3ffc00
# CONSTRUCT x0e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@2
# AUNIT --inst x0e70a800/mask=xfffffc00 --status nopcodeop
:smaxv Rd_FPR16, Rn_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_smaxv(Rn_VPR64.4H, 2:1);
}
# C7.2.270 SMAXV page C7-1988 line 111280 MATCH x0e30a800/mask=xbf3ffc00
# CONSTRUCT x4e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@2
# AUNIT --inst x4e70a800/mask=xfffffc00 --status nopcodeop
:smaxv Rd_FPR16, Rn_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_smaxv(Rn_VPR128.8H, 2:1);
}
# C7.2.270 SMAXV page C7-1988 line 111280 MATCH x0e30a800/mask=xbf3ffc00
# CONSTRUCT x4eb0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@4
# AUNIT --inst x4eb0a800/mask=xfffffc00 --status nopcodeop
:smaxv Rd_FPR32, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_smaxv(Rn_VPR128.4S, 4:1);
}
# C7.2.271 SMIN page C7-1990 line 111381 MATCH x0e206c00/mask=xbf20fc00
# CONSTRUCT x4e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@1
# AUNIT --inst x4e206c00/mask=xffe0fc00 --status nopcodeop
:smin Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xd & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_smin(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.271 SMIN page C7-1990 line 111381 MATCH x0e206c00/mask=xbf20fc00
# CONSTRUCT x0ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@4
# AUNIT --inst x0ea06c00/mask=xffe0fc00 --status nopcodeop
:smin Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xd & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_smin(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.271 SMIN page C7-1990 line 111381 MATCH x0e206c00/mask=xbf20fc00
# CONSTRUCT x0e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@2
# AUNIT --inst x0e606c00/mask=xffe0fc00 --status nopcodeop
:smin Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xd & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_smin(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.271 SMIN page C7-1990 line 111381 MATCH x0e206c00/mask=xbf20fc00
# CONSTRUCT x4ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@4
# AUNIT --inst x4ea06c00/mask=xffe0fc00 --status nopcodeop
:smin Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xd & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_smin(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.271 SMIN page C7-1990 line 111381 MATCH x0e206c00/mask=xbf20fc00
# CONSTRUCT x0e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@1
# AUNIT --inst x0e206c00/mask=xffe0fc00 --status nopcodeop
:smin Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xd & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_smin(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.271 SMIN page C7-1990 line 111381 MATCH x0e206c00/mask=xbf20fc00
# CONSTRUCT x4e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@2
# AUNIT --inst x4e606c00/mask=xffe0fc00 --status nopcodeop
:smin Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xd & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_smin(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.272 SMINP page C7-1992 line 111481 MATCH x0e20ac00/mask=xbf20fc00
# CONSTRUCT x4e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@1
# AUNIT --inst x4e20ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:sminp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x15 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sminp(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.272 SMINP page C7-1992 line 111481 MATCH x0e20ac00/mask=xbf20fc00
# CONSTRUCT x0ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@4
# AUNIT --inst x0ea0ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:sminp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x15 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sminp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.272 SMINP page C7-1992 line 111481 MATCH x0e20ac00/mask=xbf20fc00
# CONSTRUCT x0e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@2
# AUNIT --inst x0e60ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:sminp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x15 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sminp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.272 SMINP page C7-1992 line 111481 MATCH x0e20ac00/mask=xbf20fc00
# CONSTRUCT x4ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@4
# AUNIT --inst x4ea0ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:sminp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x15 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sminp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.272 SMINP page C7-1992 line 111481 MATCH x0e20ac00/mask=xbf20fc00
# CONSTRUCT x0e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@1
# AUNIT --inst x0e20ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:sminp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x15 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sminp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.272 SMINP page C7-1992 line 111481 MATCH x0e20ac00/mask=xbf20fc00
# CONSTRUCT x4e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@2
# AUNIT --inst x4e60ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:sminp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x15 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sminp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.273 SMINV page C7-1994 line 111583 MATCH x0e31a800/mask=xbf3ffc00
# CONSTRUCT x4e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@1
# AUNIT --inst x4e31a800/mask=xfffffc00 --status nopcodeop
:sminv Rd_FPR8, Rn_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_sminv(Rn_VPR128.16B, 1:1);
}
# C7.2.273 SMINV page C7-1994 line 111583 MATCH x0e31a800/mask=xbf3ffc00
# CONSTRUCT x0e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@1
# AUNIT --inst x0e31a800/mask=xfffffc00 --status nopcodeop
:sminv Rd_FPR8, Rn_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_sminv(Rn_VPR64.8B, 1:1);
}
# C7.2.273 SMINV page C7-1994 line 111583 MATCH x0e31a800/mask=xbf3ffc00
# CONSTRUCT x0e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@2
# AUNIT --inst x0e71a800/mask=xfffffc00 --status nopcodeop
:sminv Rd_FPR16, Rn_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_sminv(Rn_VPR64.4H, 2:1);
}
# C7.2.273 SMINV page C7-1994 line 111583 MATCH x0e31a800/mask=xbf3ffc00
# CONSTRUCT x4e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@2
# AUNIT --inst x4e71a800/mask=xfffffc00 --status nopcodeop
:sminv Rd_FPR16, Rn_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_sminv(Rn_VPR128.8H, 2:1);
}
# C7.2.273 SMINV page C7-1994 line 111583 MATCH x0e31a800/mask=xbf3ffc00
# CONSTRUCT x4eb1a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@4
# AUNIT --inst x4eb1a800/mask=xfffffc00 --status nopcodeop
:sminv Rd_FPR32, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_sminv(Rn_VPR128.4S, 4:1);
}
# C7.2.274 SMLAL, SMLAL2 (by element) page C7-1996 line 111684 MATCH x0f002000/mask=xbf00f400
# CONSTRUCT x0f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@4
# AUNIT --inst x0f802000/mask=xffc0f400 --status pass --comment "ext"
:smlal Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ2[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.274 SMLAL, SMLAL2 (by element) page C7-1996 line 111684 MATCH x0f002000/mask=xbf00f400
# CONSTRUCT x0f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@2
# AUNIT --inst x0f402000/mask=xffc0f400 --status pass --comment "ext"
:smlal Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ2[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ2[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ2[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.274 SMLAL, SMLAL2 (by element) page C7-1996 line 111684 MATCH x0f002000/mask=xbf00f400
# CONSTRUCT x4f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@4
# AUNIT --inst x4f802000/mask=xffc0f400 --status pass --comment "ext"
:smlal2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Rn_VPR128 & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp3:4 = Re_VPR128.S.vIndex;
local tmp4:8 = sext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.274 SMLAL, SMLAL2 (by element) page C7-1996 line 111684 MATCH x0f002000/mask=xbf00f400
# CONSTRUCT x4f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@2
# AUNIT --inst x4f402000/mask=xffc0f400 --status pass --comment "ext"
:smlal2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Rn_VPR128 & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp4:4 = sext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.275 SMLAL, SMLAL2 (vector) page C7-1999 line 111847 MATCH x0e208000/mask=xbf20fc00
# CONSTRUCT x0ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@4
# AUNIT --inst x0ea08000/mask=xffe0fc00 --status pass --comment "ext"
:smlal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x8 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8
TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.275 SMLAL, SMLAL2 (vector) page C7-1999 line 111847 MATCH x0e208000/mask=xbf20fc00
# CONSTRUCT x0e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@2
# AUNIT --inst x0e608000/mask=xffe0fc00 --status pass --comment "ext"
:smlal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x8 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4
TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.275 SMLAL, SMLAL2 (vector) page C7-1999 line 111847 MATCH x0e208000/mask=xbf20fc00
# CONSTRUCT x0e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $*@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@1
# AUNIT --inst x0e208000/mask=xffe0fc00 --status pass --comment "ext"
:smlal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x8 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2
TMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16];
TMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16];
TMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16];
TMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16];
TMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16];
TMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16];
TMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16];
TMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16];
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ3 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ3[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ3[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ3[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ3[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ3[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ3[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ3[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ3[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.275 SMLAL, SMLAL2 (vector) page C7-1999 line 111847 MATCH x0e208000/mask=xbf20fc00
# CONSTRUCT x4ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@4
# AUNIT --inst x4ea08000/mask=xffe0fc00 --status pass --comment "ext"
:smlal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x8 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = sext(TMPD3[0,32]);
TMPQ4[64,64] = sext(TMPD3[32,32]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ5 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ5[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ5[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.275 SMLAL, SMLAL2 (vector) page C7-1999 line 111847 MATCH x0e208000/mask=xbf20fc00
# CONSTRUCT x4e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@2
# AUNIT --inst x4e608000/mask=xffe0fc00 --status pass --comment "ext"
:smlal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x8 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = sext(TMPD3[0,16]);
TMPQ4[32,32] = sext(TMPD3[16,16]);
TMPQ4[64,32] = sext(TMPD3[32,16]);
TMPQ4[96,32] = sext(TMPD3[48,16]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ5 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ5[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ5[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ5[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ5[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.275 SMLAL, SMLAL2 (vector) page C7-1999 line 111847 MATCH x0e208000/mask=xbf20fc00
# CONSTRUCT x4e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $*@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@1
# AUNIT --inst x4e208000/mask=xffe0fc00 --status pass --comment "ext"
:smlal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x8 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = sext(TMPD1[0,8]);
TMPQ2[16,16] = sext(TMPD1[8,8]);
TMPQ2[32,16] = sext(TMPD1[16,8]);
TMPQ2[48,16] = sext(TMPD1[24,8]);
TMPQ2[64,16] = sext(TMPD1[32,8]);
TMPQ2[80,16] = sext(TMPD1[40,8]);
TMPQ2[96,16] = sext(TMPD1[48,8]);
TMPQ2[112,16] = sext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = sext(TMPD3[0,8]);
TMPQ4[16,16] = sext(TMPD3[8,8]);
TMPQ4[32,16] = sext(TMPD3[16,8]);
TMPQ4[48,16] = sext(TMPD3[24,8]);
TMPQ4[64,16] = sext(TMPD3[32,8]);
TMPQ4[80,16] = sext(TMPD3[40,8]);
TMPQ4[96,16] = sext(TMPD3[48,8]);
TMPQ4[112,16] = sext(TMPD3[56,8]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2
TMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16];
TMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16];
TMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16];
TMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16];
TMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16];
TMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16];
TMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16];
TMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16];
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ5 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ5[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ5[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ5[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ5[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ5[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ5[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ5[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ5[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2001 line 111970 MATCH x0f006000/mask=xbf00f400
# CONSTRUCT x0f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* &=$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@4
# AUNIT --inst x0f806000/mask=xffc0f400 --status pass --comment "ext"
:smlsl Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ2[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2001 line 111970 MATCH x0f006000/mask=xbf00f400
# CONSTRUCT x0f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@2
# AUNIT --inst x0f406000/mask=xffc0f400 --status pass --comment "ext"
:smlsl Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ2[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ2[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ2[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2001 line 111970 MATCH x0f006000/mask=xbf00f400
# CONSTRUCT x4f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* &=$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@4
# AUNIT --inst x4f806000/mask=xffc0f400 --status pass --comment "ext"
:smlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp3:4 = Re_VPR128.S.vIndex;
local tmp4:8 = sext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2001 line 111970 MATCH x0f006000/mask=xbf00f400
# CONSTRUCT x4f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@2
# AUNIT --inst x4f406000/mask=xffc0f400 --status pass --comment "ext"
:smlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp4:4 = sext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2004 line 112131 MATCH x0e20a000/mask=xbf20fc00
# CONSTRUCT x0ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 &=$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@4
# AUNIT --inst x0ea0a000/mask=xffe0fc00 --status pass --comment "ext"
:smlsl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xa & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8
TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2004 line 112131 MATCH x0e20a000/mask=xbf20fc00
# CONSTRUCT x0e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@2
# AUNIT --inst x0e60a000/mask=xffe0fc00 --status pass --comment "ext"
:smlsl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xa & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4
TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2004 line 112131 MATCH x0e20a000/mask=xbf20fc00
# CONSTRUCT x0e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $*@2 &=$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@1
# AUNIT --inst x0e20a000/mask=xffe0fc00 --status pass --comment "ext"
:smlsl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xa & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2
TMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16];
TMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16];
TMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16];
TMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16];
TMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16];
TMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16];
TMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16];
TMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16];
# simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ3 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ3[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ3[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ3[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ3[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ3[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ3[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ3[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ3[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2004 line 112131 MATCH x0e20a000/mask=xbf20fc00
# CONSTRUCT x4ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 &=$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@4
# AUNIT --inst x4ea0a000/mask=xffe0fc00 --status pass --comment "ext"
:smlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xa & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = sext(TMPD3[0,32]);
TMPQ4[64,64] = sext(TMPD3[32,32]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ5 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ5[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ5[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2004 line 112131 MATCH x0e20a000/mask=xbf20fc00
# CONSTRUCT x4e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@2
# AUNIT --inst x4e60a000/mask=xffe0fc00 --status pass --comment "ext"
:smlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xa & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = sext(TMPD3[0,16]);
TMPQ4[32,32] = sext(TMPD3[16,16]);
TMPQ4[64,32] = sext(TMPD3[32,16]);
TMPQ4[96,32] = sext(TMPD3[48,16]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ5 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ5[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ5[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ5[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ5[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2004 line 112131 MATCH x0e20a000/mask=xbf20fc00
# CONSTRUCT x4e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $*@2 &=$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@1
# AUNIT --inst x4e20a000/mask=xffe0fc00 --status pass --comment "ext"
:smlsl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xa & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = sext(TMPD1[0,8]);
TMPQ2[16,16] = sext(TMPD1[8,8]);
TMPQ2[32,16] = sext(TMPD1[16,8]);
TMPQ2[48,16] = sext(TMPD1[24,8]);
TMPQ2[64,16] = sext(TMPD1[32,8]);
TMPQ2[80,16] = sext(TMPD1[40,8]);
TMPQ2[96,16] = sext(TMPD1[48,8]);
TMPQ2[112,16] = sext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = sext(TMPD3[0,8]);
TMPQ4[16,16] = sext(TMPD3[8,8]);
TMPQ4[32,16] = sext(TMPD3[16,8]);
TMPQ4[48,16] = sext(TMPD3[24,8]);
TMPQ4[64,16] = sext(TMPD3[32,8]);
TMPQ4[80,16] = sext(TMPD3[40,8]);
TMPQ4[96,16] = sext(TMPD3[48,8]);
TMPQ4[112,16] = sext(TMPD3[56,8]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2
TMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16];
TMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16];
TMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16];
TMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16];
TMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16];
TMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16];
TMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16];
TMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16];
# simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ5 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ5[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ5[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ5[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ5[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ5[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ5[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ5[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ5[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.279 SMOV page C7-2007 line 112311 MATCH x0e002c00/mask=xbfe0fc00
# CONSTRUCT x0e012c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =sext
# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1
# AUNIT --inst x0e012c00/mask=xffe1fc00 --status pass
:smov Rd_GPR32, Rn_VPR128.B.imm_neon_uimm4
is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64
{
# simd element Rn_VPR128[imm_neon_uimm4] lane size 1
local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;
Rd_GPR32 = sext(tmp1);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.279 SMOV page C7-2007 line 112311 MATCH x0e002c00/mask=xbfe0fc00
# CONSTRUCT x0e022c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =sext
# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1
# AUNIT --inst x0e022c00/mask=xffe3fc00 --status pass
:smov Rd_GPR32, Rn_VPR128.H.imm_neon_uimm3
is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64
{
# simd element Rn_VPR128[imm_neon_uimm3] lane size 2
local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;
Rd_GPR32 = sext(tmp1);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.279 SMOV page C7-2007 line 112311 MATCH x0e002c00/mask=xbfe0fc00
# CONSTRUCT x4e012c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =sext
# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1
# AUNIT --inst x4e012c00/mask=xffe1fc00 --status pass
:smov Rd_GPR64, Rn_VPR128.B.imm_neon_uimm4
is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR64
{
# simd element Rn_VPR128[imm_neon_uimm4] lane size 1
local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;
Rd_GPR64 = sext(tmp1);
}
# C7.2.279 SMOV page C7-2007 line 112311 MATCH x0e002c00/mask=xbfe0fc00
# CONSTRUCT x4e022c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =sext
# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1
# AUNIT --inst x4e022c00/mask=xffe3fc00 --status pass
:smov Rd_GPR64, Rn_VPR128.H.imm_neon_uimm3
is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR64
{
# simd element Rn_VPR128[imm_neon_uimm3] lane size 2
local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;
Rd_GPR64 = sext(tmp1);
}
# C7.2.279 SMOV page C7-2007 line 112311 MATCH x0e002c00/mask=xbfe0fc00
# CONSTRUCT x4e042c00/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =sext
# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1
# AUNIT --inst x4e042c00/mask=xffe7fc00 --status pass
:smov Rd_GPR64, Rn_VPR128.S.imm_neon_uimm2
is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR64
{
# simd element Rn_VPR128[imm_neon_uimm2] lane size 4
local tmp1:4 = Rn_VPR128.S.imm_neon_uimm2;
Rd_GPR64 = sext(tmp1);
}
# C7.2.280 SMULL, SMULL2 (by element) page C7-2009 line 112428 MATCH x0f00a000/mask=xbf00f400
# CONSTRUCT x0f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@4
# AUNIT --inst x0f80a000/mask=xffc0f400 --status pass --comment "ext"
:smull Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
# simd infix Rd_VPR128.2D = TMPQ1 * tmp3 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64] * tmp3;
Rd_VPR128.2D[64,64] = TMPQ1[64,64] * tmp3;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.280 SMULL, SMULL2 (by element) page C7-2009 line 112428 MATCH x0f00a000/mask=xbf00f400
# CONSTRUCT x0f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@2
# AUNIT --inst x0f40a000/mask=xffc0f400 --status pass --comment "ext"
:smull Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
# simd infix Rd_VPR128.4S = TMPQ1 * tmp3 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32] * tmp3;
Rd_VPR128.4S[32,32] = TMPQ1[32,32] * tmp3;
Rd_VPR128.4S[64,32] = TMPQ1[64,32] * tmp3;
Rd_VPR128.4S[96,32] = TMPQ1[96,32] * tmp3;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.280 SMULL, SMULL2 (by element) page C7-2009 line 112428 MATCH x0f00a000/mask=xbf00f400
# CONSTRUCT x4f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@4
# AUNIT --inst x4f80a000/mask=xffc0f400 --status pass --comment "ext"
:smull2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Rn_VPR128 & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp3:4 = Re_VPR128.S.vIndex;
local tmp4:8 = sext(tmp3);
# simd infix Rd_VPR128.2D = TMPQ2 * tmp4 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ2[0,64] * tmp4;
Rd_VPR128.2D[64,64] = TMPQ2[64,64] * tmp4;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.280 SMULL, SMULL2 (by element) page C7-2009 line 112428 MATCH x0f00a000/mask=xbf00f400
# CONSTRUCT x4f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@2
# AUNIT --inst x4f40a000/mask=xffc0f400 --status pass --comment "ext"
:smull2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Rn_VPR128 & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp4:4 = sext(tmp3);
# simd infix Rd_VPR128.4S = TMPQ2 * tmp4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ2[0,32] * tmp4;
Rd_VPR128.4S[32,32] = TMPQ2[32,32] * tmp4;
Rd_VPR128.4S[64,32] = TMPQ2[64,32] * tmp4;
Rd_VPR128.4S[96,32] = TMPQ2[96,32] * tmp4;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.281 SMULL, SMULL2 (vector) page C7-2012 line 112581 MATCH x0e20c000/mask=xbf20fc00
# CONSTRUCT x0ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 =$*@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@4
# AUNIT --inst x0ea0c000/mask=xffe0fc00 --status pass --comment "ext"
:smull Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xc & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
# simd infix Rd_VPR128.2D = TMPQ1 * TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
Rd_VPR128.2D[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.281 SMULL, SMULL2 (vector) page C7-2012 line 112581 MATCH x0e20c000/mask=xbf20fc00
# CONSTRUCT x0e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 =$*@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@2
# AUNIT --inst x0e60c000/mask=xffe0fc00 --status pass --comment "ext"
:smull Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xc & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
# simd infix Rd_VPR128.4S = TMPQ1 * TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
Rd_VPR128.4S[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
Rd_VPR128.4S[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
Rd_VPR128.4S[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.281 SMULL, SMULL2 (vector) page C7-2012 line 112581 MATCH x0e20c000/mask=xbf20fc00
# CONSTRUCT x0e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 =$*@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@1
# AUNIT --inst x0e20c000/mask=xffe0fc00 --status pass --comment "ext"
:smull Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xc & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
# simd infix Rd_VPR128.8H = TMPQ1 * TMPQ2 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[0,16] * TMPQ2[0,16];
Rd_VPR128.8H[16,16] = TMPQ1[16,16] * TMPQ2[16,16];
Rd_VPR128.8H[32,16] = TMPQ1[32,16] * TMPQ2[32,16];
Rd_VPR128.8H[48,16] = TMPQ1[48,16] * TMPQ2[48,16];
Rd_VPR128.8H[64,16] = TMPQ1[64,16] * TMPQ2[64,16];
Rd_VPR128.8H[80,16] = TMPQ1[80,16] * TMPQ2[80,16];
Rd_VPR128.8H[96,16] = TMPQ1[96,16] * TMPQ2[96,16];
Rd_VPR128.8H[112,16] = TMPQ1[112,16] * TMPQ2[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.281 SMULL, SMULL2 (vector) page C7-2012 line 112581 MATCH x0e20c000/mask=xbf20fc00
# CONSTRUCT x4ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 =$*@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@4
# AUNIT --inst x4ea0c000/mask=xffe0fc00 --status pass --comment "ext"
:smull2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xc & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Rn_VPR128 & Rm_VPR128 & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = sext(TMPD3[0,32]);
TMPQ4[64,64] = sext(TMPD3[32,32]);
# simd infix Rd_VPR128.2D = TMPQ2 * TMPQ4 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
Rd_VPR128.2D[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.281 SMULL, SMULL2 (vector) page C7-2012 line 112581 MATCH x0e20c000/mask=xbf20fc00
# CONSTRUCT x4e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 =$*@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@2
# AUNIT --inst x4e60c000/mask=xffe0fc00 --status pass --comment "ext"
:smull2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xc & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Rn_VPR128 & Rm_VPR128 & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = sext(TMPD3[0,16]);
TMPQ4[32,32] = sext(TMPD3[16,16]);
TMPQ4[64,32] = sext(TMPD3[32,16]);
TMPQ4[96,32] = sext(TMPD3[48,16]);
# simd infix Rd_VPR128.4S = TMPQ2 * TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
Rd_VPR128.4S[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
Rd_VPR128.4S[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
Rd_VPR128.4S[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.281 SMULL, SMULL2 (vector) page C7-2012 line 112581 MATCH x0e20c000/mask=xbf20fc00
# CONSTRUCT x4e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 =$*@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@1
# AUNIT --inst x4e20c000/mask=xffe0fc00 --status pass --comment "ext"
:smull2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xc & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Rn_VPR128 & Rm_VPR128 & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = sext(TMPD1[0,8]);
TMPQ2[16,16] = sext(TMPD1[8,8]);
TMPQ2[32,16] = sext(TMPD1[16,8]);
TMPQ2[48,16] = sext(TMPD1[24,8]);
TMPQ2[64,16] = sext(TMPD1[32,8]);
TMPQ2[80,16] = sext(TMPD1[40,8]);
TMPQ2[96,16] = sext(TMPD1[48,8]);
TMPQ2[112,16] = sext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = sext(TMPD3[0,8]);
TMPQ4[16,16] = sext(TMPD3[8,8]);
TMPQ4[32,16] = sext(TMPD3[16,8]);
TMPQ4[48,16] = sext(TMPD3[24,8]);
TMPQ4[64,16] = sext(TMPD3[32,8]);
TMPQ4[80,16] = sext(TMPD3[40,8]);
TMPQ4[96,16] = sext(TMPD3[48,8]);
TMPQ4[112,16] = sext(TMPD3[56,8]);
# simd infix Rd_VPR128.8H = TMPQ2 * TMPQ4 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ2[0,16] * TMPQ4[0,16];
Rd_VPR128.8H[16,16] = TMPQ2[16,16] * TMPQ4[16,16];
Rd_VPR128.8H[32,16] = TMPQ2[32,16] * TMPQ4[32,16];
Rd_VPR128.8H[48,16] = TMPQ2[48,16] * TMPQ4[48,16];
Rd_VPR128.8H[64,16] = TMPQ2[64,16] * TMPQ4[64,16];
Rd_VPR128.8H[80,16] = TMPQ2[80,16] * TMPQ4[80,16];
Rd_VPR128.8H[96,16] = TMPQ2[96,16] * TMPQ4[96,16];
Rd_VPR128.8H[112,16] = TMPQ2[112,16] * TMPQ4[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.282 SQABS page C7-2014 line 112696 MATCH x5e207800/mask=xff3ffc00
# CONSTRUCT x5e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =abs
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1
# AUNIT --inst x5e207800/mask=xfffffc00 --status pass --comment "nointsat"
# Scalar variant when size = 00 Q = 1 aa=1 suf=FPR8
# Note: in some implemented semantics that ignore saturation (where it
# makes a difference), there is an error in about 50% of the lanes.
:sqabs Rd_FPR8, Rn_FPR8
is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_FPR8 & Rn_FPR8 & Zd
{
Rd_FPR8 = MP_INT_ABS(Rn_FPR8);
zext_zb(Zd); # zero upper 31 bytes of Zd
}
# C7.2.282 SQABS page C7-2014 line 112696 MATCH x5e207800/mask=xff3ffc00
# CONSTRUCT x5e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =abs
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1
# AUNIT --inst x5e607800/mask=xfffffc00 --status pass --comment "nointsat"
# Scalar variant when size = 01 Q = 1 aa=1 suf=FPR16
:sqabs Rd_FPR16, Rn_FPR16
is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = MP_INT_ABS(Rn_FPR16);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.282 SQABS page C7-2014 line 112696 MATCH x5e207800/mask=xff3ffc00
# CONSTRUCT x5ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =abs
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1
# AUNIT --inst x5ea07800/mask=xfffffc00 --status pass --comment "nointsat"
# Scalar variant when size = 10 Q = 1 aa=1 suf=FPR32
:sqabs Rd_FPR32, Rn_FPR32
is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = MP_INT_ABS(Rn_FPR32);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.282 SQABS page C7-2014 line 112696 MATCH x5e207800/mask=xff3ffc00
# CONSTRUCT x5ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =abs
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1
# AUNIT --inst x5ee07800/mask=xfffffc00 --status pass --comment "nointsat"
# Scalar variant when size = 11 Q = 1 aa=1 suf=FPR64
:sqabs Rd_FPR64, Rn_FPR64
is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = MP_INT_ABS(Rn_FPR64);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.282 SQABS page C7-2014 line 112696 MATCH x0e207800/mask=xbf3ffc00
# CONSTRUCT x0e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@1
# AUNIT --inst x0e207800/mask=xfffffc00 --status fail --comment "nointsat"
# Vector variant when size = 00 Q = 0 aa=0 esize=1 suf=VPR64.8B
:sqabs Rd_VPR64.8B, Rn_VPR64.8B
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
{
# simd unary Rd_VPR64.8B = MP_INT_ABS(Rn_VPR64.8B) on lane size 1
Rd_VPR64.8B[0,8] = MP_INT_ABS(Rn_VPR64.8B[0,8]);
Rd_VPR64.8B[8,8] = MP_INT_ABS(Rn_VPR64.8B[8,8]);
Rd_VPR64.8B[16,8] = MP_INT_ABS(Rn_VPR64.8B[16,8]);
Rd_VPR64.8B[24,8] = MP_INT_ABS(Rn_VPR64.8B[24,8]);
Rd_VPR64.8B[32,8] = MP_INT_ABS(Rn_VPR64.8B[32,8]);
Rd_VPR64.8B[40,8] = MP_INT_ABS(Rn_VPR64.8B[40,8]);
Rd_VPR64.8B[48,8] = MP_INT_ABS(Rn_VPR64.8B[48,8]);
Rd_VPR64.8B[56,8] = MP_INT_ABS(Rn_VPR64.8B[56,8]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.282 SQABS page C7-2014 line 112696 MATCH x0e207800/mask=xbf3ffc00
# CONSTRUCT x4e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@1
# AUNIT --inst x4e207800/mask=xfffffc00 --status fail --comment "nointsat"
# Vector variant when size = 00 Q = 1 aa=0 esize=1 suf=VPR128.16B
:sqabs Rd_VPR128.16B, Rn_VPR128.16B
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
{
# simd unary Rd_VPR128.16B = MP_INT_ABS(Rn_VPR128.16B) on lane size 1
Rd_VPR128.16B[0,8] = MP_INT_ABS(Rn_VPR128.16B[0,8]);
Rd_VPR128.16B[8,8] = MP_INT_ABS(Rn_VPR128.16B[8,8]);
Rd_VPR128.16B[16,8] = MP_INT_ABS(Rn_VPR128.16B[16,8]);
Rd_VPR128.16B[24,8] = MP_INT_ABS(Rn_VPR128.16B[24,8]);
Rd_VPR128.16B[32,8] = MP_INT_ABS(Rn_VPR128.16B[32,8]);
Rd_VPR128.16B[40,8] = MP_INT_ABS(Rn_VPR128.16B[40,8]);
Rd_VPR128.16B[48,8] = MP_INT_ABS(Rn_VPR128.16B[48,8]);
Rd_VPR128.16B[56,8] = MP_INT_ABS(Rn_VPR128.16B[56,8]);
Rd_VPR128.16B[64,8] = MP_INT_ABS(Rn_VPR128.16B[64,8]);
Rd_VPR128.16B[72,8] = MP_INT_ABS(Rn_VPR128.16B[72,8]);
Rd_VPR128.16B[80,8] = MP_INT_ABS(Rn_VPR128.16B[80,8]);
Rd_VPR128.16B[88,8] = MP_INT_ABS(Rn_VPR128.16B[88,8]);
Rd_VPR128.16B[96,8] = MP_INT_ABS(Rn_VPR128.16B[96,8]);
Rd_VPR128.16B[104,8] = MP_INT_ABS(Rn_VPR128.16B[104,8]);
Rd_VPR128.16B[112,8] = MP_INT_ABS(Rn_VPR128.16B[112,8]);
Rd_VPR128.16B[120,8] = MP_INT_ABS(Rn_VPR128.16B[120,8]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.282 SQABS page C7-2014 line 112696 MATCH x0e207800/mask=xbf3ffc00
# CONSTRUCT x0e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@2
# AUNIT --inst x0e607800/mask=xfffffc00 --status pass --comment "nointsat"
# Vector variant when size = 01 Q = 0 aa=0 esize=2 suf=VPR64.4H
:sqabs Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
# simd unary Rd_VPR64.4H = MP_INT_ABS(Rn_VPR64.4H) on lane size 2
Rd_VPR64.4H[0,16] = MP_INT_ABS(Rn_VPR64.4H[0,16]);
Rd_VPR64.4H[16,16] = MP_INT_ABS(Rn_VPR64.4H[16,16]);
Rd_VPR64.4H[32,16] = MP_INT_ABS(Rn_VPR64.4H[32,16]);
Rd_VPR64.4H[48,16] = MP_INT_ABS(Rn_VPR64.4H[48,16]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.282 SQABS page C7-2014 line 112696 MATCH x0e207800/mask=xbf3ffc00
# CONSTRUCT x4e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@2
# AUNIT --inst x4e607800/mask=xfffffc00 --status pass --comment "nointsat"
# Vector variant when size = 01 Q = 1 aa=0 esize=2 suf=VPR128.8H
:sqabs Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
# simd unary Rd_VPR128.8H = MP_INT_ABS(Rn_VPR128.8H) on lane size 2
Rd_VPR128.8H[0,16] = MP_INT_ABS(Rn_VPR128.8H[0,16]);
Rd_VPR128.8H[16,16] = MP_INT_ABS(Rn_VPR128.8H[16,16]);
Rd_VPR128.8H[32,16] = MP_INT_ABS(Rn_VPR128.8H[32,16]);
Rd_VPR128.8H[48,16] = MP_INT_ABS(Rn_VPR128.8H[48,16]);
Rd_VPR128.8H[64,16] = MP_INT_ABS(Rn_VPR128.8H[64,16]);
Rd_VPR128.8H[80,16] = MP_INT_ABS(Rn_VPR128.8H[80,16]);
Rd_VPR128.8H[96,16] = MP_INT_ABS(Rn_VPR128.8H[96,16]);
Rd_VPR128.8H[112,16] = MP_INT_ABS(Rn_VPR128.8H[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.282 SQABS page C7-2014 line 112696 MATCH x0e207800/mask=xbf3ffc00
# CONSTRUCT x0ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@4
# AUNIT --inst x0ea07800/mask=xfffffc00 --status pass --comment "nointsat"
# Vector variant when size = 10 Q = 0 aa=0 esize=4 suf=VPR64.2S
:sqabs Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
# simd unary Rd_VPR64.2S = MP_INT_ABS(Rn_VPR64.2S) on lane size 4
Rd_VPR64.2S[0,32] = MP_INT_ABS(Rn_VPR64.2S[0,32]);
Rd_VPR64.2S[32,32] = MP_INT_ABS(Rn_VPR64.2S[32,32]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.282 SQABS page C7-2014 line 112696 MATCH x0e207800/mask=xbf3ffc00
# CONSTRUCT x4ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@4
# AUNIT --inst x4ea07800/mask=xfffffc00 --status pass --comment "nointsat"
# Vector variant when size = 10 Q = 1 aa=0 esize=4 suf=VPR128.4S
:sqabs Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
# simd unary Rd_VPR128.4S = MP_INT_ABS(Rn_VPR128.4S) on lane size 4
Rd_VPR128.4S[0,32] = MP_INT_ABS(Rn_VPR128.4S[0,32]);
Rd_VPR128.4S[32,32] = MP_INT_ABS(Rn_VPR128.4S[32,32]);
Rd_VPR128.4S[64,32] = MP_INT_ABS(Rn_VPR128.4S[64,32]);
Rd_VPR128.4S[96,32] = MP_INT_ABS(Rn_VPR128.4S[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.282 SQABS page C7-2014 line 112696 MATCH x0e207800/mask=xbf3ffc00
# CONSTRUCT x4ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$abs@8
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@8
# AUNIT --inst x4ee07800/mask=xfffffc00 --status pass --comment "nointsat"
# Vector variant when size = 11 Q = 1 aa=0 esize=8 suf=VPR128.2D
:sqabs Rd_VPR128.2D, Rn_VPR128.2D
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
{
# simd unary Rd_VPR128.2D = MP_INT_ABS(Rn_VPR128.2D) on lane size 8
Rd_VPR128.2D[0,64] = MP_INT_ABS(Rn_VPR128.2D[0,64]);
Rd_VPR128.2D[64,64] = MP_INT_ABS(Rn_VPR128.2D[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.283 SQADD page C7-2016 line 112816 MATCH x5e200c00/mask=xff20fc00
# CONSTRUCT x5e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2
# AUNIT --inst x5e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqadd Rd_FPR8, Rn_FPR8, Rm_FPR8
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x1 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_sqadd(Rn_FPR8, Rm_FPR8);
}
# C7.2.283 SQADD page C7-2016 line 112816 MATCH x5e200c00/mask=xff20fc00
# CONSTRUCT x5ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2
# AUNIT --inst x5ee00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqadd Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x1 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_sqadd(Rn_FPR64, Rm_FPR64);
}
# C7.2.283 SQADD page C7-2016 line 112816 MATCH x5e200c00/mask=xff20fc00
# CONSTRUCT x5e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2
# AUNIT --inst x5e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqadd Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x1 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_sqadd(Rn_FPR16, Rm_FPR16);
}
# C7.2.283 SQADD page C7-2016 line 112816 MATCH x5e200c00/mask=xff20fc00
# CONSTRUCT x5ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2
# AUNIT --inst x5ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqadd Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x1 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_sqadd(Rn_FPR32, Rm_FPR32);
}
# C7.2.283 SQADD page C7-2016 line 112816 MATCH x0e200c00/mask=xbf20fc00
# CONSTRUCT x4e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@1
# AUNIT --inst x4e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x1 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sqadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.283 SQADD page C7-2016 line 112816 MATCH x0e200c00/mask=xbf20fc00
# CONSTRUCT x4ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@8
# AUNIT --inst x4ee00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x1 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_sqadd(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.283 SQADD page C7-2016 line 112816 MATCH x0e200c00/mask=xbf20fc00
# CONSTRUCT x0ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@4
# AUNIT --inst x0ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x1 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.283 SQADD page C7-2016 line 112816 MATCH x0e200c00/mask=xbf20fc00
# CONSTRUCT x0e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@2
# AUNIT --inst x0e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x1 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.283 SQADD page C7-2016 line 112816 MATCH x0e200c00/mask=xbf20fc00
# CONSTRUCT x4ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@4
# AUNIT --inst x4ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x1 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.283 SQADD page C7-2016 line 112816 MATCH x0e200c00/mask=xbf20fc00
# CONSTRUCT x0e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@1
# AUNIT --inst x0e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x1 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sqadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.283 SQADD page C7-2016 line 112816 MATCH x0e200c00/mask=xbf20fc00
# CONSTRUCT x4e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@2
# AUNIT --inst x4e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x1 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2018 line 112941 MATCH x5f003000/mask=xff00f400
# CONSTRUCT x5f803000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=+/2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3
# AUNIT --inst x5f803000/mask=xffc0f400 --status fail --comment "nointsat"
# scalar variant, size == 10 (always part == 0)
:sqdmlal Rd_FPR64, Rn_FPR32, Re_VPR128.S.vIndex
is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b0011 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rd_FPR64 & Rn_FPR32 & Zd
{
local tmp1:8 = sext(Rn_FPR32);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
local tmp4:8 = tmp1 * tmp3;
local tmp5:8 = tmp4 * 2:8;
Rd_FPR64 = Rd_FPR64 + tmp5;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2018 line 112941 MATCH x5f003000/mask=xff00f400
# CONSTRUCT x5f403000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 sext:4 ARG2 sext:4 * 2:4 * &=+
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3
# AUNIT --inst x5f403000/mask=xffc0f400 --status fail --comment "nointsat"
# scalar variant, size == 01 (always part == 0)
:sqdmlal Rd_FPR32, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b0011 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rd_FPR32 & Rn_FPR16 & Zd
{
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp2:4 = sext(tmp1);
local tmp3:4 = sext(Rn_FPR16);
local tmp4:4 = tmp2 * tmp3;
local tmp5:4 = tmp4 * 2:4;
Rd_FPR32 = Rd_FPR32 + tmp5;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2018 line 112941 MATCH x0f003000/mask=xbf00f400
# CONSTRUCT x0f803000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@4
# AUNIT --inst x0f803000/mask=xffc0f400 --status fail --comment "ext nointsat"
# vector variant, Q == 0, size == 10
:sqdmlal Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0011 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
# simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8
TMPQ3[0,64] = TMPQ2[0,64] * 2:8;
TMPQ3[64,64] = TMPQ2[64,64] * 2:8;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2018 line 112941 MATCH x0f003000/mask=xbf00f400
# CONSTRUCT x0f403000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@2
# AUNIT --inst x0f403000/mask=xffc0f400 --status fail --comment "ext nointsat"
# vector variant, Q = 0, size == 01
:sqdmlal Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0011 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
# simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4
TMPQ3[0,32] = TMPQ2[0,32] * 2:4;
TMPQ3[32,32] = TMPQ2[32,32] * 2:4;
TMPQ3[64,32] = TMPQ2[64,32] * 2:4;
TMPQ3[96,32] = TMPQ2[96,32] * 2:4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2018 line 112941 MATCH x0f003000/mask=xbf00f400
# CONSTRUCT x4f803000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@4
# AUNIT --inst x4f803000/mask=xffc0f400 --status fail --comment "ext nointsat"
# vector variant, Q = 1, size == 10
:sqdmlal2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0011 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp3:4 = Re_VPR128.S.vIndex;
local tmp4:8 = sext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
# simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8
TMPQ4[0,64] = TMPQ3[0,64] * 2:8;
TMPQ4[64,64] = TMPQ3[64,64] * 2:8;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2018 line 112941 MATCH x0f003000/mask=xbf00f400
# CONSTRUCT x4f403000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@2
# AUNIT --inst x4f403000/mask=xffc0f400 --status fail --comment "ext nointsat"
# vector variant, Q = 1, size == 01
:sqdmlal2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0011 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp4:4 = sext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
# simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4
TMPQ4[0,32] = TMPQ3[0,32] * 2:4;
TMPQ4[32,32] = TMPQ3[32,32] * 2:4;
TMPQ4[64,32] = TMPQ3[64,32] * 2:4;
TMPQ4[96,32] = TMPQ3[96,32] * 2:4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2022 line 113158 MATCH x5e209000/mask=xff20fc00
# CONSTRUCT x5ea09000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=+
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3
# AUNIT --inst x5ea09000/mask=xffe0fc00 --status fail --comment "nointsat"
# scalar variant, size == 10 (always part == 0)
:sqdmlal Rd_FPR64, Rn_FPR32, Rm_FPR32
is b_2431=0b01011110 & b_2223=0b10 & b_21=1 & b_1015=0b100100 & Rd_FPR64 & Rn_FPR32 & Rm_FPR32 & Zd
{
local tmp1:8 = sext(Rn_FPR32);
local tmp2:8 = sext(Rm_FPR32);
local tmp3:8 = tmp1 * tmp2;
local tmp4:8 = tmp3 * 2:8;
Rd_FPR64 = Rd_FPR64 + tmp4;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2022 line 113158 MATCH x5e209000/mask=xff20fc00
# CONSTRUCT x5e609000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * &=+
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3
# AUNIT --inst x5e609000/mask=xffe0fc00 --status fail --comment "nointsat"
# scalar variant, size == 01 (always part == 0)
:sqdmlal Rd_FPR32, Rn_FPR16, Rm_FPR16
is b_2431=0b01011110 & b_2223=0b01 & b_21=1 & b_1015=0b100100 & Rd_FPR32 & Rn_FPR16 & Rm_FPR16 & Zd
{
local tmp1:4 = sext(Rn_FPR16);
local tmp2:4 = sext(Rm_FPR16);
local tmp3:4 = tmp1 * tmp2;
local tmp4:4 = tmp3 * 2:4;
Rd_FPR32 = Rd_FPR32 + tmp4;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2022 line 113158 MATCH x0e209000/mask=xbf20fc00
# CONSTRUCT x0ea09000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 2:8 $* &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@4
# AUNIT --inst x0ea09000/mask=xffe0fc00 --status fail --comment "ext nointsat"
# vector variant, Q == 0, size == 10
:sqdmlal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b100100 & Rn_VPR64.2S & Rd_VPR128.2D & Rm_VPR64.2S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8
TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
# simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8
TMPQ4[0,64] = TMPQ3[0,64] * 2:8;
TMPQ4[64,64] = TMPQ3[64,64] * 2:8;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2022 line 113158 MATCH x0e209000/mask=xbf20fc00
# CONSTRUCT x0e609000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 2:4 $* &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@2
# AUNIT --inst x0e609000/mask=xffe0fc00 --status fail --comment "ext nointsat"
# vector variant, Q = 0, size == 01
:sqdmlal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b100100 & Rn_VPR64.4H & Rd_VPR128.4S & Rm_VPR64.4H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4
TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
# simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4
TMPQ4[0,32] = TMPQ3[0,32] * 2:4;
TMPQ4[32,32] = TMPQ3[32,32] * 2:4;
TMPQ4[64,32] = TMPQ3[64,32] * 2:4;
TMPQ4[96,32] = TMPQ3[96,32] * 2:4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2022 line 113158 MATCH x0e209000/mask=xbf20fc00
# CONSTRUCT x4ea09000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 2:8 $* &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@4
# AUNIT --inst x4ea09000/mask=xffe0fc00 --status fail --comment "ext nointsat"
# vector variant, Q = 1, size == 10
:sqdmlal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b100100 & Rn_VPR128.4S & Rd_VPR128.2D & Rm_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = sext(TMPD3[0,32]);
TMPQ4[64,64] = sext(TMPD3[32,32]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
# simd infix TMPQ6 = TMPQ5 * 2:8 on lane size 8
TMPQ6[0,64] = TMPQ5[0,64] * 2:8;
TMPQ6[64,64] = TMPQ5[64,64] * 2:8;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ6 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ6[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ6[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2022 line 113158 MATCH x0e209000/mask=xbf20fc00
# CONSTRUCT x4e609000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 2:4 $* &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@2
# AUNIT --inst x4e609000/mask=xffe0fc00 --status fail --comment "ext nointsat"
# vector variant, Q = 1, size == 01
:sqdmlal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b100100 & Rn_VPR128.8H & Rd_VPR128.4S & Rm_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = sext(TMPD3[0,16]);
TMPQ4[32,32] = sext(TMPD3[16,16]);
TMPQ4[64,32] = sext(TMPD3[32,16]);
TMPQ4[96,32] = sext(TMPD3[48,16]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
# simd infix TMPQ6 = TMPQ5 * 2:4 on lane size 4
TMPQ6[0,32] = TMPQ5[0,32] * 2:4;
TMPQ6[32,32] = TMPQ5[32,32] * 2:4;
TMPQ6[64,32] = TMPQ5[64,32] * 2:4;
TMPQ6[96,32] = TMPQ5[96,32] * 2:4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ6 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ6[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ6[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ6[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ6[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2025 line 113331 MATCH x5f007000/mask=xff00f400
# CONSTRUCT x5f807000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=-
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3
# AUNIT --inst x5f807000/mask=xffc0f400 --status fail --comment "nointsat"
# scalar variant, size == 10 (always part == 0)
:sqdmlsl Rd_FPR64, Rn_FPR32, Re_VPR128.S.vIndex
is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b0111 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rd_FPR64 & Rn_FPR32 & Zd
{
local tmp1:8 = sext(Rn_FPR32);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
local tmp4:8 = tmp1 * tmp3;
local tmp5:8 = tmp4 * 2:8;
Rd_FPR64 = Rd_FPR64 - tmp5;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2025 line 113331 MATCH x5f007000/mask=xff00f400
# CONSTRUCT x5f407000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * &=-
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3
# AUNIT --inst x5f407000/mask=xffc0f400 --status fail --comment "nointsat"
# scalar variant, size == 01 (always part == 0)
:sqdmlsl Rd_FPR32, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b0111 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rd_FPR32 & Rn_FPR16 & Zd
{
local tmp1:4 = sext(Rn_FPR16);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
local tmp4:4 = tmp1 * tmp3;
local tmp5:4 = tmp4 * 2:4;
Rd_FPR32 = Rd_FPR32 - tmp5;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2025 line 113331 MATCH x0f007000/mask=xbf00f400
# CONSTRUCT x0f807000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@4
# AUNIT --inst x0f807000/mask=xffc0f400 --status fail --comment "ext nointsat"
# vector variant, Q == 0, size == 10
:sqdmlsl Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0111 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
# simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8
TMPQ3[0,64] = TMPQ2[0,64] * 2:8;
TMPQ3[64,64] = TMPQ2[64,64] * 2:8;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2025 line 113331 MATCH x0f007000/mask=xbf00f400
# CONSTRUCT x0f407000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@2
# AUNIT --inst x0f407000/mask=xffc0f400 --status fail --comment "ext nointsat"
# vector variant, Q = 0, size == 01
:sqdmlsl Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0111 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
# simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4
TMPQ3[0,32] = TMPQ2[0,32] * 2:4;
TMPQ3[32,32] = TMPQ2[32,32] * 2:4;
TMPQ3[64,32] = TMPQ2[64,32] * 2:4;
TMPQ3[96,32] = TMPQ2[96,32] * 2:4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2025 line 113331 MATCH x0f007000/mask=xbf00f400
# CONSTRUCT x4f807000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@4
# AUNIT --inst x4f807000/mask=xffc0f400 --status fail --comment "ext nointsat"
# vector variant, Q = 1, size == 10
:sqdmlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0111 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp3:4 = Re_VPR128.S.vIndex;
local tmp4:8 = sext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
# simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8
TMPQ4[0,64] = TMPQ3[0,64] * 2:8;
TMPQ4[64,64] = TMPQ3[64,64] * 2:8;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ4 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ4[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ4[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2025 line 113331 MATCH x0f007000/mask=xbf00f400
# CONSTRUCT x4f407000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@2
# AUNIT --inst x4f407000/mask=xffc0f400 --status fail --comment "ext nointsat"
# vector variant, Q = 1, size == 01
:sqdmlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0111 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp4:4 = sext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
# simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4
TMPQ4[0,32] = TMPQ3[0,32] * 2:4;
TMPQ4[32,32] = TMPQ3[32,32] * 2:4;
TMPQ4[64,32] = TMPQ3[64,32] * 2:4;
TMPQ4[96,32] = TMPQ3[96,32] * 2:4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ4[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ4[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ4[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2029 line 113549 MATCH x5e20b000/mask=xff20fc00
# CONSTRUCT x5ea0b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=-
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3
# AUNIT --inst x5ea0b000/mask=xffe0fc00 --status fail --comment "nointsat"
# scalar variant, size == 10 (always part == 0)
:sqdmlsl Rd_FPR64, Rn_FPR32, Rm_FPR32
is b_2431=0b01011110 & b_2223=0b10 & b_21=1 & b_1015=0b101100 & Rd_FPR64 & Rn_FPR32 & Rm_FPR32 & Zd
{
local tmp1:8 = sext(Rn_FPR32);
local tmp2:8 = sext(Rm_FPR32);
local tmp3:8 = tmp1 * tmp2;
local tmp4:8 = tmp3 * 2:8;
Rd_FPR64 = Rd_FPR64 - tmp4;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2029 line 113549 MATCH x5e20b000/mask=xff20fc00
# CONSTRUCT x5e60b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * &=-
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3
# AUNIT --inst x5e60b000/mask=xffe0fc00 --status fail --comment "nointsat"
# scalar variant, size == 01 (always part == 0)
:sqdmlsl Rd_FPR32, Rn_FPR16, Rm_FPR16
is b_2431=0b01011110 & b_2223=0b01 & b_21=1 & b_1015=0b101100 & Rd_FPR32 & Rn_FPR16 & Rm_FPR16 & Zd
{
local tmp1:4 = sext(Rn_FPR16);
local tmp2:4 = sext(Rm_FPR16);
local tmp3:4 = tmp1 * tmp2;
local tmp4:4 = tmp3 * 2:4;
Rd_FPR32 = Rd_FPR32 - tmp4;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2029 line 113549 MATCH x0e20b000/mask=xbf20fc00
# CONSTRUCT x0ea0b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 2:8 $* &=$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3
# AUNIT --inst x0ea0b000/mask=xffe0fc00 --status fail --comment "ext nointsat"
# vector variant, Q == 0, size == 10
:sqdmlsl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b101100 & Rn_VPR64.2S & Rd_VPR128.2D & Rm_VPR64.2S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8
TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
# simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8
TMPQ4[0,64] = TMPQ3[0,64] * 2:8;
TMPQ4[64,64] = TMPQ3[64,64] * 2:8;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ4 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ4[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ4[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2029 line 113549 MATCH x0e20b000/mask=xbf20fc00
# CONSTRUCT x0e60b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 2:4 $* &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@2
# AUNIT --inst x0e60b000/mask=xffe0fc00 --status fail --comment "ext nointsat"
# vector variant, Q = 0, size == 01
:sqdmlsl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b101100 & Rn_VPR64.4H & Rd_VPR128.4S & Rm_VPR64.4H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4
TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
# simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4
TMPQ4[0,32] = TMPQ3[0,32] * 2:4;
TMPQ4[32,32] = TMPQ3[32,32] * 2:4;
TMPQ4[64,32] = TMPQ3[64,32] * 2:4;
TMPQ4[96,32] = TMPQ3[96,32] * 2:4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ4[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ4[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ4[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2029 line 113549 MATCH x0e20b000/mask=xbf20fc00
# CONSTRUCT x4ea0b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 2:8 $* &=$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@4
# AUNIT --inst x4ea0b000/mask=xffe0fc00 --status fail --comment "ext nointsat"
# vector variant, Q = 1, size == 10
:sqdmlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b101100 & Rn_VPR128.4S & Rd_VPR128.2D & Rm_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = sext(TMPD3[0,32]);
TMPQ4[64,64] = sext(TMPD3[32,32]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
# simd infix TMPQ6 = TMPQ5 * 2:8 on lane size 8
TMPQ6[0,64] = TMPQ5[0,64] * 2:8;
TMPQ6[64,64] = TMPQ5[64,64] * 2:8;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ6 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ6[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ6[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2029 line 113549 MATCH x0e20b000/mask=xbf20fc00
# CONSTRUCT x4e60b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 2:4 $* &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@2
# AUNIT --inst x4e60b000/mask=xffe0fc00 --status fail --comment "ext nointsat"
# vector variant, Q = 1, size == 01
:sqdmlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b101100 & Rn_VPR128.8H & Rd_VPR128.4S & Rm_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = sext(TMPD3[0,16]);
TMPQ4[32,32] = sext(TMPD3[16,16]);
TMPQ4[64,32] = sext(TMPD3[32,16]);
TMPQ4[96,32] = sext(TMPD3[48,16]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
# simd infix TMPQ6 = TMPQ5 * 2:4 on lane size 4
TMPQ6[0,32] = TMPQ5[0,32] * 2:4;
TMPQ6[32,32] = TMPQ5[32,32] * 2:4;
TMPQ6[64,32] = TMPQ5[64,32] * 2:4;
TMPQ6[96,32] = TMPQ5[96,32] * 2:4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ6 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ6[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ6[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ6[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ6[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.288 SQDMULH (by element) page C7-2032 line 113722 MATCH x0f00c000/mask=xbf00f400
# CONSTRUCT x0f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$shuffle@1-0@3-1:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@4
# AUNIT --inst x0f80c000/mask=xffc0f400 --status pass --comment "ext nointsat"
:sqdmulh Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xc & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
# simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8
TMPQ3[0,64] = TMPQ2[0,64] * 2:8;
TMPQ3[64,64] = TMPQ2[64,64] * 2:8;
# simd shuffle Rd_VPR64.2S = TMPQ3 (@1-0@3-1) lane size 4
Rd_VPR64.2S[0,32] = TMPQ3[32,32];
Rd_VPR64.2S[32,32] = TMPQ3[96,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.288 SQDMULH (by element) page C7-2032 line 113722 MATCH x0f00c000/mask=xbf00f400
# CONSTRUCT x0f40c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$shuffle@1-0@3-1@5-2@7-3:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2
# AUNIT --inst x0f40c000/mask=xffc0f400 --status pass --comment "ext nointsat"
:sqdmulh Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xc & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
# simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4
TMPQ3[0,32] = TMPQ2[0,32] * 2:4;
TMPQ3[32,32] = TMPQ2[32,32] * 2:4;
TMPQ3[64,32] = TMPQ2[64,32] * 2:4;
TMPQ3[96,32] = TMPQ2[96,32] * 2:4;
# simd shuffle Rd_VPR64.4H = TMPQ3 (@1-0@3-1@5-2@7-3) lane size 2
Rd_VPR64.4H[0,16] = TMPQ3[16,16];
Rd_VPR64.4H[16,16] = TMPQ3[48,16];
Rd_VPR64.4H[32,16] = TMPQ3[80,16];
Rd_VPR64.4H[48,16] = TMPQ3[112,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.288 SQDMULH (by element) page C7-2032 line 113722 MATCH x0f00c000/mask=xbf00f400
# CONSTRUCT x4f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:32 ARG3 sext:8 $* 2:8 $* &=$shuffle@1-0@3-1@5-2@7-3:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@4
# AUNIT --inst x4f80c000/mask=xffc0f400 --status pass --comment "ext nointsat"
:sqdmulh Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xc & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd resize TMPZ1 = sext(Rn_VPR128.4S) (lane size 4 to 8)
TMPZ1[0,64] = sext(Rn_VPR128.4S[0,32]);
TMPZ1[64,64] = sext(Rn_VPR128.4S[32,32]);
TMPZ1[128,64] = sext(Rn_VPR128.4S[64,32]);
TMPZ1[192,64] = sext(Rn_VPR128.4S[96,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
# simd infix TMPZ2 = TMPZ1 * tmp3 on lane size 8
TMPZ2[0,64] = TMPZ1[0,64] * tmp3;
TMPZ2[64,64] = TMPZ1[64,64] * tmp3;
TMPZ2[128,64] = TMPZ1[128,64] * tmp3;
TMPZ2[192,64] = TMPZ1[192,64] * tmp3;
# simd infix TMPZ3 = TMPZ2 * 2:8 on lane size 8
TMPZ3[0,64] = TMPZ2[0,64] * 2:8;
TMPZ3[64,64] = TMPZ2[64,64] * 2:8;
TMPZ3[128,64] = TMPZ2[128,64] * 2:8;
TMPZ3[192,64] = TMPZ2[192,64] * 2:8;
# simd shuffle Rd_VPR128.4S = TMPZ3 (@1-0@3-1@5-2@7-3) lane size 4
Rd_VPR128.4S[0,32] = TMPZ3[32,32];
Rd_VPR128.4S[32,32] = TMPZ3[96,32];
Rd_VPR128.4S[64,32] = TMPZ3[160,32];
Rd_VPR128.4S[96,32] = TMPZ3[224,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.288 SQDMULH (by element) page C7-2032 line 113722 MATCH x0f00c000/mask=xbf00f400
# CONSTRUCT x4f40c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:32 ARG3 sext:4 $* 2:4 $* &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2
# AUNIT --inst x4f40c000/mask=xffc0f400 --status pass --comment "ext nointsat"
:sqdmulh Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xc & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd resize TMPZ1 = sext(Rn_VPR128.8H) (lane size 2 to 4)
TMPZ1[0,32] = sext(Rn_VPR128.8H[0,16]);
TMPZ1[32,32] = sext(Rn_VPR128.8H[16,16]);
TMPZ1[64,32] = sext(Rn_VPR128.8H[32,16]);
TMPZ1[96,32] = sext(Rn_VPR128.8H[48,16]);
TMPZ1[128,32] = sext(Rn_VPR128.8H[64,16]);
TMPZ1[160,32] = sext(Rn_VPR128.8H[80,16]);
TMPZ1[192,32] = sext(Rn_VPR128.8H[96,16]);
TMPZ1[224,32] = sext(Rn_VPR128.8H[112,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
# simd infix TMPZ2 = TMPZ1 * tmp3 on lane size 4
TMPZ2[0,32] = TMPZ1[0,32] * tmp3;
TMPZ2[32,32] = TMPZ1[32,32] * tmp3;
TMPZ2[64,32] = TMPZ1[64,32] * tmp3;
TMPZ2[96,32] = TMPZ1[96,32] * tmp3;
TMPZ2[128,32] = TMPZ1[128,32] * tmp3;
TMPZ2[160,32] = TMPZ1[160,32] * tmp3;
TMPZ2[192,32] = TMPZ1[192,32] * tmp3;
TMPZ2[224,32] = TMPZ1[224,32] * tmp3;
# simd infix TMPZ3 = TMPZ2 * 2:4 on lane size 4
TMPZ3[0,32] = TMPZ2[0,32] * 2:4;
TMPZ3[32,32] = TMPZ2[32,32] * 2:4;
TMPZ3[64,32] = TMPZ2[64,32] * 2:4;
TMPZ3[96,32] = TMPZ2[96,32] * 2:4;
TMPZ3[128,32] = TMPZ2[128,32] * 2:4;
TMPZ3[160,32] = TMPZ2[160,32] * 2:4;
TMPZ3[192,32] = TMPZ2[192,32] * 2:4;
TMPZ3[224,32] = TMPZ2[224,32] * 2:4;
# simd shuffle Rd_VPR128.8H = TMPZ3 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 2
Rd_VPR128.8H[0,16] = TMPZ3[16,16];
Rd_VPR128.8H[16,16] = TMPZ3[48,16];
Rd_VPR128.8H[32,16] = TMPZ3[80,16];
Rd_VPR128.8H[48,16] = TMPZ3[112,16];
Rd_VPR128.8H[64,16] = TMPZ3[144,16];
Rd_VPR128.8H[80,16] = TMPZ3[176,16];
Rd_VPR128.8H[96,16] = TMPZ3[208,16];
Rd_VPR128.8H[112,16] = TMPZ3[240,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.288 SQDMULH (by element) page C7-2032 line 113722 MATCH x5f00c000/mask=xff00f400
# CONSTRUCT x5f40c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * 16:1 >>:4 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2
# AUNIT --inst x5f40c000/mask=xffc0f400 --status pass --comment "nointsat"
# Scalar variant when size=01 suf=FPR16 elem=Re_VPR128Lo.H.vIndexHLM p1=Re_VPR128Lo.H p2=vIndexHLM
:sqdmulh Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b1100 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
{
local tmp1:4 = sext(Rn_FPR16);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
local tmp4:4 = tmp1 * tmp3;
local tmp5:4 = tmp4 * 2:4;
local tmp6:4 = tmp5 >> 16:1;
Rd_FPR16 = tmp6:2;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.288 SQDMULH (by element) page C7-2032 line 113722 MATCH x5f00c000/mask=xff00f400
# CONSTRUCT x5f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * 32:1 >>:8 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2
# AUNIT --inst x5f80c000/mask=xffc0f400 --status pass --comment "nointsat"
# Scalar variant when size=10 suf=FPR32 elem=Re_VPR128.S.vIndex p1=Re_VPR128.S p2=vIndex
:sqdmulh Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex
is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b1100 & b_10=0 & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd
{
local tmp1:8 = sext(Rn_FPR32);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
local tmp4:8 = tmp1 * tmp3;
local tmp5:8 = tmp4 * 2:8;
local tmp6:8 = tmp5 >> 32:1;
Rd_FPR32 = tmp6:4;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.289 SQDMULH (vector) page C7-2035 line 113898 MATCH x5e20b400/mask=xff20fc00
# CONSTRUCT x5e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2
# AUNIT --inst x5e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqdmulh Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x16 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_sqdmulh(Rn_FPR16, Rm_FPR16);
}
# C7.2.289 SQDMULH (vector) page C7-2035 line 113898 MATCH x5e20b400/mask=xff20fc00
# CONSTRUCT x5ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2
# AUNIT --inst x5ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqdmulh Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x16 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_sqdmulh(Rn_FPR32, Rm_FPR32);
}
# C7.2.289 SQDMULH (vector) page C7-2035 line 113898 MATCH x0e20b400/mask=xbf20fc00
# CONSTRUCT x0ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@4
# AUNIT --inst x0ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqdmulh Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x16 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqdmulh(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.289 SQDMULH (vector) page C7-2035 line 113898 MATCH x0e20b400/mask=xbf20fc00
# CONSTRUCT x0e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2
# AUNIT --inst x0e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqdmulh Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x16 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqdmulh(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.289 SQDMULH (vector) page C7-2035 line 113898 MATCH x0e20b400/mask=xbf20fc00
# CONSTRUCT x4ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@4
# AUNIT --inst x4ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqdmulh Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x16 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqdmulh(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.289 SQDMULH (vector) page C7-2035 line 113898 MATCH x0e20b400/mask=xbf20fc00
# CONSTRUCT x4e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2
# AUNIT --inst x4e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqdmulh Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x16 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqdmulh(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2037 line 114026 MATCH x0f00b000/mask=xbf00f400
# CONSTRUCT x0f80b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2@4
# AUNIT --inst x0f80b000/mask=xffc0f400 --status pass --comment "ext nointsat"
:sqdmull Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xb & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
# simd infix Rd_VPR128.2D = TMPQ2 * 2:8 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ2[0,64] * 2:8;
Rd_VPR128.2D[64,64] = TMPQ2[64,64] * 2:8;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2037 line 114026 MATCH x0f00b000/mask=xbf00f400
# CONSTRUCT x4f80b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* 2:8 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@4
# AUNIT --inst x4f80b000/mask=xffc0f400 --status pass --comment "ext nointsat"
:sqdmull2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xb & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp3:4 = Re_VPR128.S.vIndex;
local tmp4:8 = sext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
# simd infix Rd_VPR128.2D = TMPQ3 * 2:8 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ3[0,64] * 2:8;
Rd_VPR128.2D[64,64] = TMPQ3[64,64] * 2:8;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2037 line 114026 MATCH x0f00b000/mask=xbf00f400
# CONSTRUCT x0f40b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@2
# AUNIT --inst x0f40b000/mask=xffc0f400 --status pass --comment "ext nointsat"
:sqdmull Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xb & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
# simd infix Rd_VPR128.4S = TMPQ2 * 2:4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ2[0,32] * 2:4;
Rd_VPR128.4S[32,32] = TMPQ2[32,32] * 2:4;
Rd_VPR128.4S[64,32] = TMPQ2[64,32] * 2:4;
Rd_VPR128.4S[96,32] = TMPQ2[96,32] * 2:4;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2037 line 114026 MATCH x0f00b000/mask=xbf00f400
# CONSTRUCT x4f40b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* 2:4 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@2
# AUNIT --inst x4f40b000/mask=xffc0f400 --status pass --comment "ext nointsat"
:sqdmull2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xb & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp4:4 = sext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
# simd infix Rd_VPR128.4S = TMPQ3 * 2:4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ3[0,32] * 2:4;
Rd_VPR128.4S[32,32] = TMPQ3[32,32] * 2:4;
Rd_VPR128.4S[64,32] = TMPQ3[64,32] * 2:4;
Rd_VPR128.4S[96,32] = TMPQ3[96,32] * 2:4;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2037 line 114026 MATCH x5f00b000/mask=xff00f400
# CONSTRUCT x5f40b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 =*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2
# AUNIT --inst x5f40b000/mask=xffc0f400 --status pass --comment "nointsat"
# Scalar variant when size=01 Va=FPR32 Vb=FPR16 elem=Re_VPR128Lo.H.vIndexHLM p1=Re_VPR128Lo.H p2=vIndexHLM
:sqdmull Rd_FPR32, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b1011 & b_10=0 & Rd_FPR32 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
{
local tmp1:4 = sext(Rn_FPR16);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
local tmp4:4 = tmp1 * tmp3;
Rd_FPR32 = tmp4 * 2:4;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2037 line 114026 MATCH x5f00b000/mask=xff00f400
# CONSTRUCT x5f80b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 =*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2
# AUNIT --inst x5f80b000/mask=xffc0f400 --status pass --comment "nointsat"
# Scalar variant when size=10 Va=FPR64 Vb=FPR32 elem=Re_VPR128.S.vIndex p1=Re_VPR128.S p2=vIndex
:sqdmull Rd_FPR64, Rn_FPR32, Re_VPR128.S.vIndex
is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b1011 & b_10=0 & Rd_FPR64 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd
{
local tmp1:8 = sext(Rn_FPR32);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
local tmp4:8 = tmp1 * tmp3;
Rd_FPR64 = tmp4 * 2:8;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2040 line 114226 MATCH x0e20d000/mask=xbf20fc00
# CONSTRUCT x4ea0d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 2:8 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@4
# AUNIT --inst x4ea0d000/mask=xffe0fc00 --status pass --comment "ext nointsat"
:sqdmull2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xd & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = sext(TMPD3[0,32]);
TMPQ4[64,64] = sext(TMPD3[32,32]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
# simd infix Rd_VPR128.2D = TMPQ5 * 2:8 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ5[0,64] * 2:8;
Rd_VPR128.2D[64,64] = TMPQ5[64,64] * 2:8;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2040 line 114226 MATCH x0e20d000/mask=xbf20fc00
# CONSTRUCT x4e60d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 2:4 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@2
# AUNIT --inst x4e60d000/mask=xffe0fc00 --status pass --comment "ext nointsat"
:sqdmull2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xd & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = sext(TMPD3[0,16]);
TMPQ4[32,32] = sext(TMPD3[16,16]);
TMPQ4[64,32] = sext(TMPD3[32,16]);
TMPQ4[96,32] = sext(TMPD3[48,16]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
# simd infix Rd_VPR128.4S = TMPQ5 * 2:4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ5[0,32] * 2:4;
Rd_VPR128.4S[32,32] = TMPQ5[32,32] * 2:4;
Rd_VPR128.4S[64,32] = TMPQ5[64,32] * 2:4;
Rd_VPR128.4S[96,32] = TMPQ5[96,32] * 2:4;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2040 line 114226 MATCH x0e20d000/mask=xbf20fc00
# CONSTRUCT x0ea0d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2@4
# AUNIT --inst x0ea0d000/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqdmull Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xd & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_sqdmull(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2040 line 114226 MATCH x0e20d000/mask=xbf20fc00
# CONSTRUCT x0e60d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2@2
# AUNIT --inst x0e60d000/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqdmull Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xd & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqdmull(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2040 line 114226 MATCH x5e20d000/mask=xff20fc00
# CONSTRUCT x5e60d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 =*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2
# AUNIT --inst x5e60d000/mask=xffe0fc00 --status pass --comment "nointsat"
# Scalar variant when size=01 Va=FPR32 Vb=FPR16
:sqdmull Rd_FPR32, Rn_FPR16, Rm_FPR16
is b_2431=0b01011110 & b_2223=0b01 & b_21=1 & b_1015=0b110100 & Rd_FPR32 & Rn_FPR16 & Rm_FPR16 & Zd
{
local tmp1:4 = sext(Rn_FPR16);
local tmp2:4 = sext(Rm_FPR16);
local tmp3:4 = tmp1 * tmp2;
Rd_FPR32 = tmp3 * 2:4;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2040 line 114226 MATCH x5e20d000/mask=xff20fc00
# CONSTRUCT x5ea0d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 =*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2
# AUNIT --inst x5ea0d000/mask=xffe0fc00 --status pass --comment "nointsat"
# Scalar variant when size=10 Va=FPR64 Vb=FPR32
:sqdmull Rd_FPR64, Rn_FPR32, Rm_FPR32
is b_2431=0b01011110 & b_2223=0b10 & b_21=1 & b_1015=0b110100 & Rd_FPR64 & Rn_FPR32 & Rm_FPR32 & Zd
{
local tmp1:8 = sext(Rn_FPR32);
local tmp2:8 = sext(Rm_FPR32);
local tmp3:8 = tmp1 * tmp2;
Rd_FPR64 = tmp3 * 2:8;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.292 SQNEG page C7-2043 line 114388 MATCH x7e207800/mask=xff3ffc00
# CONSTRUCT x7e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =2comp
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1
# AUNIT --inst x7e207800/mask=xfffffc00 --status pass --comment "nointsat"
# Scalar variant when size=00 Q=1 aa=1 suf=FPR8
:sqneg Rd_FPR8, Rn_FPR8
is b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_FPR8 & Rn_FPR8 & Zd
{
Rd_FPR8 = - Rn_FPR8;
zext_zb(Zd); # zero upper 31 bytes of Zd
}
# C7.2.292 SQNEG page C7-2043 line 114388 MATCH x7e207800/mask=xff3ffc00
# CONSTRUCT x7e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =2comp
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1
# AUNIT --inst x7e607800/mask=xfffffc00 --status pass --comment "nointsat"
# Scalar variant when size=01 Q=1 aa=1 suf=FPR16
:sqneg Rd_FPR16, Rn_FPR16
is b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = - Rn_FPR16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.292 SQNEG page C7-2043 line 114388 MATCH x7e207800/mask=xff3ffc00
# CONSTRUCT x7ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =2comp
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1
# AUNIT --inst x7ea07800/mask=xfffffc00 --status pass --comment "nointsat"
# Scalar variant when size=10 Q=1 aa=1 suf=FPR32
:sqneg Rd_FPR32, Rn_FPR32
is b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = - Rn_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.292 SQNEG page C7-2043 line 114388 MATCH x7e207800/mask=xff3ffc00
# CONSTRUCT x7ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =2comp
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1
# AUNIT --inst x7ee07800/mask=xfffffc00 --status pass --comment "nointsat"
# Scalar variant when size=11 Q=1 aa=1 suf=FPR64
:sqneg Rd_FPR64, Rn_FPR64
is b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = - Rn_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.292 SQNEG page C7-2043 line 114388 MATCH x2e207800/mask=xbf3ffc00
# CONSTRUCT x2e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$2comp@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@1
# AUNIT --inst x2e207800/mask=xfffffc00 --status fail --comment "nointsat"
# Vector variant when when size = 00 , Q = 0 aa=0 esize=1 suf=VPR64.8B
:sqneg Rd_VPR64.8B, Rn_VPR64.8B
is b_31=0 & Q=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
{
# simd unary Rd_VPR64.8B = -(Rn_VPR64.8B) on lane size 1
Rd_VPR64.8B[0,8] = -(Rn_VPR64.8B[0,8]);
Rd_VPR64.8B[8,8] = -(Rn_VPR64.8B[8,8]);
Rd_VPR64.8B[16,8] = -(Rn_VPR64.8B[16,8]);
Rd_VPR64.8B[24,8] = -(Rn_VPR64.8B[24,8]);
Rd_VPR64.8B[32,8] = -(Rn_VPR64.8B[32,8]);
Rd_VPR64.8B[40,8] = -(Rn_VPR64.8B[40,8]);
Rd_VPR64.8B[48,8] = -(Rn_VPR64.8B[48,8]);
Rd_VPR64.8B[56,8] = -(Rn_VPR64.8B[56,8]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.292 SQNEG page C7-2043 line 114388 MATCH x2e207800/mask=xbf3ffc00
# CONSTRUCT x6e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$2comp@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@1
# AUNIT --inst x6e207800/mask=xfffffc00 --status fail --comment "nointsat"
# Vector variant when when size = 00 , Q = 1 aa=0 esize=1 suf=VPR128.16B
:sqneg Rd_VPR128.16B, Rn_VPR128.16B
is b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
{
# simd unary Rd_VPR128.16B = -(Rn_VPR128.16B) on lane size 1
Rd_VPR128.16B[0,8] = -(Rn_VPR128.16B[0,8]);
Rd_VPR128.16B[8,8] = -(Rn_VPR128.16B[8,8]);
Rd_VPR128.16B[16,8] = -(Rn_VPR128.16B[16,8]);
Rd_VPR128.16B[24,8] = -(Rn_VPR128.16B[24,8]);
Rd_VPR128.16B[32,8] = -(Rn_VPR128.16B[32,8]);
Rd_VPR128.16B[40,8] = -(Rn_VPR128.16B[40,8]);
Rd_VPR128.16B[48,8] = -(Rn_VPR128.16B[48,8]);
Rd_VPR128.16B[56,8] = -(Rn_VPR128.16B[56,8]);
Rd_VPR128.16B[64,8] = -(Rn_VPR128.16B[64,8]);
Rd_VPR128.16B[72,8] = -(Rn_VPR128.16B[72,8]);
Rd_VPR128.16B[80,8] = -(Rn_VPR128.16B[80,8]);
Rd_VPR128.16B[88,8] = -(Rn_VPR128.16B[88,8]);
Rd_VPR128.16B[96,8] = -(Rn_VPR128.16B[96,8]);
Rd_VPR128.16B[104,8] = -(Rn_VPR128.16B[104,8]);
Rd_VPR128.16B[112,8] = -(Rn_VPR128.16B[112,8]);
Rd_VPR128.16B[120,8] = -(Rn_VPR128.16B[120,8]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.292 SQNEG page C7-2043 line 114388 MATCH x2e207800/mask=xbf3ffc00
# CONSTRUCT x2e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$2comp@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@2
# AUNIT --inst x2e607800/mask=xfffffc00 --status pass --comment "nointsat"
# Vector variant when when size = 01 , Q = 0 aa=0 esize=2 suf=VPR64.4H
:sqneg Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & Q=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
# simd unary Rd_VPR64.4H = -(Rn_VPR64.4H) on lane size 2
Rd_VPR64.4H[0,16] = -(Rn_VPR64.4H[0,16]);
Rd_VPR64.4H[16,16] = -(Rn_VPR64.4H[16,16]);
Rd_VPR64.4H[32,16] = -(Rn_VPR64.4H[32,16]);
Rd_VPR64.4H[48,16] = -(Rn_VPR64.4H[48,16]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.292 SQNEG page C7-2043 line 114388 MATCH x2e207800/mask=xbf3ffc00
# CONSTRUCT x6e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$2comp@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@2
# AUNIT --inst x6e607800/mask=xfffffc00 --status pass --comment "nointsat"
# Vector variant when when size = 01 , Q = 1 aa=0 esize=2 suf=VPR128.8H
:sqneg Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
# simd unary Rd_VPR128.8H = -(Rn_VPR128.8H) on lane size 2
Rd_VPR128.8H[0,16] = -(Rn_VPR128.8H[0,16]);
Rd_VPR128.8H[16,16] = -(Rn_VPR128.8H[16,16]);
Rd_VPR128.8H[32,16] = -(Rn_VPR128.8H[32,16]);
Rd_VPR128.8H[48,16] = -(Rn_VPR128.8H[48,16]);
Rd_VPR128.8H[64,16] = -(Rn_VPR128.8H[64,16]);
Rd_VPR128.8H[80,16] = -(Rn_VPR128.8H[80,16]);
Rd_VPR128.8H[96,16] = -(Rn_VPR128.8H[96,16]);
Rd_VPR128.8H[112,16] = -(Rn_VPR128.8H[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.292 SQNEG page C7-2043 line 114388 MATCH x2e207800/mask=xbf3ffc00
# CONSTRUCT x2ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$2comp@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@4
# AUNIT --inst x2ea07800/mask=xfffffc00 --status pass --comment "nointsat"
# Vector variant when when size = 10 , Q = 0 aa=0 esize=4 suf=VPR64.2S
:sqneg Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & Q=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
# simd unary Rd_VPR64.2S = -(Rn_VPR64.2S) on lane size 4
Rd_VPR64.2S[0,32] = -(Rn_VPR64.2S[0,32]);
Rd_VPR64.2S[32,32] = -(Rn_VPR64.2S[32,32]);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.292 SQNEG page C7-2043 line 114388 MATCH x2e207800/mask=xbf3ffc00
# CONSTRUCT x6ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$2comp@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@4
# AUNIT --inst x6ea07800/mask=xfffffc00 --status pass --comment "nointsat"
# Vector variant when when size = 10 , Q = 1 aa=0 esize=4 suf=VPR128.4S
:sqneg Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
# simd unary Rd_VPR128.4S = -(Rn_VPR128.4S) on lane size 4
Rd_VPR128.4S[0,32] = -(Rn_VPR128.4S[0,32]);
Rd_VPR128.4S[32,32] = -(Rn_VPR128.4S[32,32]);
Rd_VPR128.4S[64,32] = -(Rn_VPR128.4S[64,32]);
Rd_VPR128.4S[96,32] = -(Rn_VPR128.4S[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.292 SQNEG page C7-2043 line 114388 MATCH x2e207800/mask=xbf3ffc00
# CONSTRUCT x6ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =$2comp@8
# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@8
# AUNIT --inst x6ee07800/mask=xfffffc00 --status pass --comment "nointsat"
# Vector variant when when size = 11 , Q = 1 aa=0 esize=8 suf=VPR128.2D
:sqneg Rd_VPR128.2D, Rn_VPR128.2D
is b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
{
# simd unary Rd_VPR128.2D = -(Rn_VPR128.2D) on lane size 8
Rd_VPR128.2D[0,64] = -(Rn_VPR128.2D[0,64]);
Rd_VPR128.2D[64,64] = -(Rn_VPR128.2D[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.277 SQRDMLAH (by element) page C7-1598 line 92254 KEEPWITH
# Integer saturating instruction (not implemented)
sqrdml_subop: "ah" is b_24=0 & b_11=0 { export 0:1; }
sqrdml_subop: "ah" is b_24=1 & b_13=0 { export 0:1; }
sqrdml_subop: "sh" is b_24=0 & b_11=1 { export 1:1; }
sqrdml_subop: "sh" is b_24=1 & b_13=1 { export 1:1; }
sqrdml_esize: "h" is b_2223=0b01 { export 16:1; }
sqrdml_esize: "s" is b_2223=0b10 { export 32:1; }
sqrdml_elements: "4h" is b_2223=0b01 & b_30=0 { export 4:1; }
sqrdml_elements: "8h" is b_2223=0b01 & b_30=1 { export 8:1; }
sqrdml_elements: "2s" is b_2223=0b10 & b_30=0 { export 2:1; }
sqrdml_elements: "4s" is b_2223=0b10 & b_30=1 { export 4:1; }
sqrdml_index: val is b_2223=0b01 & b_21 & b_20 & b_11 [ val = b_11 * 4 + b_21 * 2 + b_20; ] { export * [const]:1 val; }
sqrdml_index: val is b_2223=0b10 & b_21 & b_11 [ val = b_11 * 2 + b_21; ] { export * [const]:1 val; }
# We could be more specific about the size of the register, which
# depends on the variant and Q (b_30). For now, I've just made them
# all 128 bits.
sqrdml_vd: Rd_FPR16 is b_28=1 & b_2223=0b01 & Rd_FPR16 & Rd_VPR128 { export Rd_VPR128; }
sqrdml_vd: Rd_FPR32 is b_28=1 & b_2223=0b10 & Rd_FPR32 & Rd_VPR128 { export Rd_VPR128; }
sqrdml_vd: vRd_VPR128^"."^sqrdml_elements is b_28=0 & vRd_VPR128 & Rd_VPR128 & sqrdml_elements { export Rd_VPR128; }
sqrdml_vn: Rn_FPR16 is b_28=1 & b_2223=0b01 & Rn_FPR16 & Rn_VPR128 { export Rn_VPR128; }
sqrdml_vn: Rn_FPR32 is b_28=1 & b_2223=0b10 & Rn_FPR32 & Rn_VPR128 { export Rn_VPR128; }
sqrdml_vn: vRn_VPR128^"."^sqrdml_elements is b_28=0 & vRn_VPR128 & Rn_VPR128 & sqrdml_elements { export Rn_VPR128; }
# Decode Vm (in some cases) depending on size
# cases 34.1, 36.1
sqrdml_vm: Rm_FPR16 is b_28=1 & b_24=0 & b_2223=0b01 & Rm_FPR16 & Rm_VPR128 { export Rm_VPR128; }
sqrdml_vm: Rm_FPR32 is b_28=1 & b_24=0 & b_2223=0b10 & Rm_FPR32 & Rm_VPR128 { export Rm_VPR128; }
# cases 34.2, 36.2
sqrdml_vm: vRm_VPR128^"."^sqrdml_elements is b_28=0 & b_24=0 & vRm_VPR128 & sqrdml_elements & Rm_VPR128 { export Rm_VPR128; }
sqrdml_vmlo: vRm_VPR128Lo is b_2223=0b01 & vRm_VPR128Lo & Rm_VPR128Lo { export Rm_VPR128Lo; }
sqrdml_vmlo: vRm_VPR128 is b_2223=0b10 & vRm_VPR128 & Rm_VPR128 { export Rm_VPR128; }
# cases 33, 35
sqrdml_vm: sqrdml_vmlo^"."^sqrdml_esize[sqrdml_index] is b_24=1 & sqrdml_vmlo & sqrdml_esize & sqrdml_index { export sqrdml_vmlo; }
# SQRDML(Vd, Vn, Vm, esize, elements, subop[, index])
#
# performs the SQRDML operation
#
# Vd[e] = SignedSatQ(Vd[e]<<esize subop 2 (Vn[e] * Vm[index]) + rounding_const)
#
# on elements of size esize in the registers with optional index
# for the Vm element (uses e if not supplied). rounding_const is
# not captured.
# NOTE. These instructions should set the FPSR.QC flag (cumulative
# saturation bit) if saturation occurs. However, FPSR is not
# implemented in AARCH, nor are any of the SQ* instructions, nor do
# the UQ* instructions set any FPSR flags. This would prevent flow
# control analysis related to floating point exception handline.
# SQRDMLAH,SQRDMLSH (by element) scalar variant
# C7.2.293 SQRDMLAH (by element) page C7-2045 line 114508 MATCH x7f00d000/mask=xff00f400
# C7.2.295 SQRDMLSH (by element) page C7-2050 line 114838 MATCH x7f00f000/mask=xff00f400
# CONSTRUCT x7f00d000/mask=xff00d400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO(pseudo) Rd_VPR128 ARG2 ARG3 sqrdml_esize 1:1 sqrdml_subop sqrdml_index &=NEON_sqrdml_as_h/7
# AUNIT --inst x7f00d000/mask=xff00d400 --status noqemu --comment "nointsat"
:sqrdml^sqrdml_subop sqrdml_vd, sqrdml_vn, sqrdml_vm
is b_2431=0b01111111 & b_1415=0b11 & b_12=1 & b_10=0 & sqrdml_subop & sqrdml_vd & sqrdml_vn & sqrdml_vm & sqrdml_esize & sqrdml_index & Rd_VPR128 & Zd
{
Rd_VPR128 = NEON_sqrdml_as_h(Rd_VPR128, sqrdml_vn, sqrdml_vm, sqrdml_esize, 1:1, sqrdml_subop, sqrdml_index);
}
# C7.2.293 SQRDMLAH (by element) page C7-2045 line 114508 MATCH x2f00d000/mask=xbf00f400
# C7.2.295 SQRDMLSH (by element) page C7-2050 line 114838 MATCH x2f00f000/mask=xbf00f400
# CONSTRUCT x2f00d000/mask=xbf00d400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO(pseudo) Rd_VPR128 ARG2 ARG3 sqrdml_esize sqrdml_elements sqrdml_subop sqrdml_index &=NEON_sqrdml_as_h/7
# AUNIT --inst x2f00d000/mask=xbf00d400 --status noqemu --comment "nointsat"
:sqrdml^sqrdml_subop sqrdml_vd, sqrdml_vn, sqrdml_vm
is b_31=0 & b_2429=0b101111 & b_1415=0b11 & b_12=1 & b_10=0 & sqrdml_subop & sqrdml_elements & sqrdml_vm & sqrdml_esize & sqrdml_index & sqrdml_vd & sqrdml_vn & Rd_VPR128 & Zd
{
Rd_VPR128 = NEON_sqrdml_as_h(Rd_VPR128, sqrdml_vn, sqrdml_vm, sqrdml_esize, sqrdml_elements, sqrdml_subop, sqrdml_index);
}
# C7.2.294 SQRDMLAH (vector) page C7-2048 line 114696 MATCH x7e008400/mask=xff20fc00
# C7.2.296 SQRDMLSH (vector) page C7-2053 line 115026 MATCH x7e008c00/mask=xff20fc00
# CONSTRUCT x7e008400/mask=xff20f400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO(pseudo) Rd_VPR128 ARG2 ARG3 sqrdml_esize 1:1 sqrdml_subop &=NEON_sqrdml_as_h/6
# AUNIT --inst x7e008400/mask=xff20f400 --status noqemu --comment "nointsat"
:sqrdml^sqrdml_subop sqrdml_vd, sqrdml_vn, sqrdml_vm
is b_2431=0b01111110 & b_21=0 & b_1215=0b1000 & b_10=1 & sqrdml_subop & sqrdml_esize & sqrdml_vd & sqrdml_vn & sqrdml_vm & Rd_VPR128 & Zd
{
Rd_VPR128 = NEON_sqrdml_as_h(Rd_VPR128, sqrdml_vn, sqrdml_vm, sqrdml_esize, 1:1, sqrdml_subop);
}
# C7.2.294 SQRDMLAH (vector) page C7-2048 line 114696 MATCH x2e008400/mask=xbf20fc00
# C7.2.296 SQRDMLSH (vector) page C7-2053 line 115026 MATCH x2e008c00/mask=xbf20fc00
# CONSTRUCT x2e008400/mask=xbf20f400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO(pseudo) Rd_VPR128 ARG2 ARG3 sqrdml_esize sqrdml_elements sqrdml_subop &=NEON_sqrdml_as_h/6
# AUNIT --inst x2e008400/mask=xbf20f400 --status noqemu --comment "nointsat"
:sqrdml^sqrdml_subop sqrdml_vd, sqrdml_vn, sqrdml_vm
is b_31=0 & b_2429=0b101110 & b_21=0 & b_1215=0b1000 & b_10=1 & sqrdml_subop & sqrdml_elements & sqrdml_vd & sqrdml_vn & sqrdml_vm & sqrdml_esize & Rd_VPR128 & Zd
{
Rd_VPR128 = NEON_sqrdml_as_h(Rd_VPR128, sqrdml_vn, sqrdml_vm, sqrdml_esize, sqrdml_elements, sqrdml_subop);
}
# C7.2.297 SQRDMULH (by element) page C7-2055 line 115168 MATCH x0f00d000/mask=xbf00f400
# CONSTRUCT x0f80d000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$shuffle@1-0@3-1:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@4
# AUNIT --inst x0f80d000/mask=xffc0f400 --status fail --comment "ext nointround nointsat"
# Note: in this and all implemented semantics that ignore rounding,
# there is an error in about 50% of the lanes.
:sqrdmulh Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xd & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
# simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8
TMPQ3[0,64] = TMPQ2[0,64] * 2:8;
TMPQ3[64,64] = TMPQ2[64,64] * 2:8;
# simd shuffle Rd_VPR64.2S = TMPQ3 (@1-0@3-1) lane size 4
Rd_VPR64.2S[0,32] = TMPQ3[32,32];
Rd_VPR64.2S[32,32] = TMPQ3[96,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.297 SQRDMULH (by element) page C7-2055 line 115168 MATCH x0f00d000/mask=xbf00f400
# CONSTRUCT x0f40d000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$shuffle@1-0@3-1@5-2@7-3:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@2
# AUNIT --inst x0f40d000/mask=xffc0f400 --status fail --comment "ext nointround nointsat"
:sqrdmulh Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xd & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
# simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4
TMPQ3[0,32] = TMPQ2[0,32] * 2:4;
TMPQ3[32,32] = TMPQ2[32,32] * 2:4;
TMPQ3[64,32] = TMPQ2[64,32] * 2:4;
TMPQ3[96,32] = TMPQ2[96,32] * 2:4;
# simd shuffle Rd_VPR64.4H = TMPQ3 (@1-0@3-1@5-2@7-3) lane size 2
Rd_VPR64.4H[0,16] = TMPQ3[16,16];
Rd_VPR64.4H[16,16] = TMPQ3[48,16];
Rd_VPR64.4H[32,16] = TMPQ3[80,16];
Rd_VPR64.4H[48,16] = TMPQ3[112,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.297 SQRDMULH (by element) page C7-2055 line 115168 MATCH x0f00d000/mask=xbf00f400
# CONSTRUCT x4f80d000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:32 ARG3 sext:8 $* 2:8 $* &=$shuffle@1-0@3-1@5-2@7-3:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@4
# AUNIT --inst x4f80d000/mask=xffc0f400 --status fail --comment "ext nointround nointsat"
:sqrdmulh Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xd & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd resize TMPZ1 = sext(Rn_VPR128.4S) (lane size 4 to 8)
TMPZ1[0,64] = sext(Rn_VPR128.4S[0,32]);
TMPZ1[64,64] = sext(Rn_VPR128.4S[32,32]);
TMPZ1[128,64] = sext(Rn_VPR128.4S[64,32]);
TMPZ1[192,64] = sext(Rn_VPR128.4S[96,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
# simd infix TMPZ2 = TMPZ1 * tmp3 on lane size 8
TMPZ2[0,64] = TMPZ1[0,64] * tmp3;
TMPZ2[64,64] = TMPZ1[64,64] * tmp3;
TMPZ2[128,64] = TMPZ1[128,64] * tmp3;
TMPZ2[192,64] = TMPZ1[192,64] * tmp3;
# simd infix TMPZ3 = TMPZ2 * 2:8 on lane size 8
TMPZ3[0,64] = TMPZ2[0,64] * 2:8;
TMPZ3[64,64] = TMPZ2[64,64] * 2:8;
TMPZ3[128,64] = TMPZ2[128,64] * 2:8;
TMPZ3[192,64] = TMPZ2[192,64] * 2:8;
# simd shuffle Rd_VPR128.4S = TMPZ3 (@1-0@3-1@5-2@7-3) lane size 4
Rd_VPR128.4S[0,32] = TMPZ3[32,32];
Rd_VPR128.4S[32,32] = TMPZ3[96,32];
Rd_VPR128.4S[64,32] = TMPZ3[160,32];
Rd_VPR128.4S[96,32] = TMPZ3[224,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.297 SQRDMULH (by element) page C7-2055 line 115168 MATCH x0f00d000/mask=xbf00f400
# CONSTRUCT x4f40d000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:32 ARG3 sext:4 $* 2:4 $* &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@2
# AUNIT --inst x4f40d000/mask=xffc0f400 --status fail --comment "ext nointround nointsat"
:sqrdmulh Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xd & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd resize TMPZ1 = sext(Rn_VPR128.8H) (lane size 2 to 4)
TMPZ1[0,32] = sext(Rn_VPR128.8H[0,16]);
TMPZ1[32,32] = sext(Rn_VPR128.8H[16,16]);
TMPZ1[64,32] = sext(Rn_VPR128.8H[32,16]);
TMPZ1[96,32] = sext(Rn_VPR128.8H[48,16]);
TMPZ1[128,32] = sext(Rn_VPR128.8H[64,16]);
TMPZ1[160,32] = sext(Rn_VPR128.8H[80,16]);
TMPZ1[192,32] = sext(Rn_VPR128.8H[96,16]);
TMPZ1[224,32] = sext(Rn_VPR128.8H[112,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
# simd infix TMPZ2 = TMPZ1 * tmp3 on lane size 4
TMPZ2[0,32] = TMPZ1[0,32] * tmp3;
TMPZ2[32,32] = TMPZ1[32,32] * tmp3;
TMPZ2[64,32] = TMPZ1[64,32] * tmp3;
TMPZ2[96,32] = TMPZ1[96,32] * tmp3;
TMPZ2[128,32] = TMPZ1[128,32] * tmp3;
TMPZ2[160,32] = TMPZ1[160,32] * tmp3;
TMPZ2[192,32] = TMPZ1[192,32] * tmp3;
TMPZ2[224,32] = TMPZ1[224,32] * tmp3;
# simd infix TMPZ3 = TMPZ2 * 2:4 on lane size 4
TMPZ3[0,32] = TMPZ2[0,32] * 2:4;
TMPZ3[32,32] = TMPZ2[32,32] * 2:4;
TMPZ3[64,32] = TMPZ2[64,32] * 2:4;
TMPZ3[96,32] = TMPZ2[96,32] * 2:4;
TMPZ3[128,32] = TMPZ2[128,32] * 2:4;
TMPZ3[160,32] = TMPZ2[160,32] * 2:4;
TMPZ3[192,32] = TMPZ2[192,32] * 2:4;
TMPZ3[224,32] = TMPZ2[224,32] * 2:4;
# simd shuffle Rd_VPR128.8H = TMPZ3 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 2
Rd_VPR128.8H[0,16] = TMPZ3[16,16];
Rd_VPR128.8H[16,16] = TMPZ3[48,16];
Rd_VPR128.8H[32,16] = TMPZ3[80,16];
Rd_VPR128.8H[48,16] = TMPZ3[112,16];
Rd_VPR128.8H[64,16] = TMPZ3[144,16];
Rd_VPR128.8H[80,16] = TMPZ3[176,16];
Rd_VPR128.8H[96,16] = TMPZ3[208,16];
Rd_VPR128.8H[112,16] = TMPZ3[240,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.297 SQRDMULH (by element) page C7-2055 line 115168 MATCH x5f00d000/mask=xff00f400
# CONSTRUCT x5f40d000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * 16:4 >>:4 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2
# AUNIT --inst x5f40d000/mask=xffc0f400 --status fail --comment "nointround nointsat"
# Scalar variant when size=01 suf=FPR16 elem elem=Re_VPR128Lo.H.vIndexHLM p1=Re_VPR128Lo.H p2=vIndexHLM
:sqrdmulh Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b1101 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
{
local tmp1:4 = sext(Rn_FPR16);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = sext(tmp2);
local tmp4:4 = tmp1 * tmp3;
local tmp5:4 = tmp4 * 2:4;
local tmp6:4 = tmp5 >> 16:4;
Rd_FPR16 = tmp6:2;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.297 SQRDMULH (by element) page C7-2055 line 115168 MATCH x5f00d000/mask=xff00f400
# CONSTRUCT x5f80d000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * 32:8 >>:8 =
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2
# AUNIT --inst x5f80d000/mask=xffc0f400 --status fail --comment "nointround nointsat"
# Scalar variant when size=10 suf=FPR32 elem=Re_VPR128.S.vIndex p1=Re_VPR128.S p2=vIndex
:sqrdmulh Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex
is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b1101 & b_10=0 & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd
{
local tmp1:8 = sext(Rn_FPR32);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = sext(tmp2);
local tmp4:8 = tmp1 * tmp3;
local tmp5:8 = tmp4 * 2:8;
local tmp6:8 = tmp5 >> 32:8;
Rd_FPR32 = tmp6:4;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.298 SQRDMULH (vector) page C7-2058 line 115344 MATCH x7e20b400/mask=xff20fc00
# CONSTRUCT x7e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2
# AUNIT --inst x7e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrdmulh Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x16 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_sqrdmulh(Rn_FPR16, Rm_FPR16);
}
# C7.2.298 SQRDMULH (vector) page C7-2058 line 115344 MATCH x7e20b400/mask=xff20fc00
# CONSTRUCT x7ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2
# AUNIT --inst x7ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrdmulh Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x16 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_sqrdmulh(Rn_FPR32, Rm_FPR32);
}
# C7.2.298 SQRDMULH (vector) page C7-2058 line 115344 MATCH x2e20b400/mask=xbf20fc00
# CONSTRUCT x2ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@4
# AUNIT --inst x2ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrdmulh Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x16 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqrdmulh(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.298 SQRDMULH (vector) page C7-2058 line 115344 MATCH x2e20b400/mask=xbf20fc00
# CONSTRUCT x2e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@2
# AUNIT --inst x2e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrdmulh Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x16 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqrdmulh(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.298 SQRDMULH (vector) page C7-2058 line 115344 MATCH x2e20b400/mask=xbf20fc00
# CONSTRUCT x6ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@4
# AUNIT --inst x6ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrdmulh Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x16 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqrdmulh(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.298 SQRDMULH (vector) page C7-2058 line 115344 MATCH x2e20b400/mask=xbf20fc00
# CONSTRUCT x6e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@2
# AUNIT --inst x6e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrdmulh Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x16 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqrdmulh(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.299 SQRSHL page C7-2060 line 115472 MATCH x5e205c00/mask=xff20fc00
# CONSTRUCT x5e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2
# AUNIT --inst x5e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshl Rd_FPR8, Rn_FPR8, Rm_FPR8
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0xb & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_sqrshl(Rn_FPR8, Rm_FPR8);
}
# C7.2.299 SQRSHL page C7-2060 line 115472 MATCH x5e205c00/mask=xff20fc00
# CONSTRUCT x5ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2
# AUNIT --inst x5ee05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshl Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xb & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_sqrshl(Rn_FPR64, Rm_FPR64);
}
# C7.2.299 SQRSHL page C7-2060 line 115472 MATCH x5e205c00/mask=xff20fc00
# CONSTRUCT x5e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2
# AUNIT --inst x5e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshl Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0xb & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_sqrshl(Rn_FPR16, Rm_FPR16);
}
# C7.2.299 SQRSHL page C7-2060 line 115472 MATCH x5e205c00/mask=xff20fc00
# CONSTRUCT x5ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2
# AUNIT --inst x5ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshl Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0xb & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_sqrshl(Rn_FPR32, Rm_FPR32);
}
# C7.2.299 SQRSHL page C7-2060 line 115472 MATCH x0e205c00/mask=xbf20fc00
# CONSTRUCT x4e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@1
# AUNIT --inst x4e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xb & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sqrshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.299 SQRSHL page C7-2060 line 115472 MATCH x0e205c00/mask=xbf20fc00
# CONSTRUCT x4ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@8
# AUNIT --inst x4ee05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xb & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_sqrshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.299 SQRSHL page C7-2060 line 115472 MATCH x0e205c00/mask=xbf20fc00
# CONSTRUCT x0ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@4
# AUNIT --inst x0ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xb & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqrshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.299 SQRSHL page C7-2060 line 115472 MATCH x0e205c00/mask=xbf20fc00
# CONSTRUCT x0e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@2
# AUNIT --inst x0e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xb & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqrshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.299 SQRSHL page C7-2060 line 115472 MATCH x0e205c00/mask=xbf20fc00
# CONSTRUCT x4ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@4
# AUNIT --inst x4ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xb & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqrshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.299 SQRSHL page C7-2060 line 115472 MATCH x0e205c00/mask=xbf20fc00
# CONSTRUCT x0e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@1
# AUNIT --inst x0e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xb & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sqrshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.299 SQRSHL page C7-2060 line 115472 MATCH x0e205c00/mask=xbf20fc00
# CONSTRUCT x4e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@2
# AUNIT --inst x4e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xb & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqrshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2062 line 115610 MATCH x0f009c00/mask=xbf80fc00
# CONSTRUCT x4f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@2
# AUNIT --inst x4f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sqrshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2062 line 115610 MATCH x0f009c00/mask=xbf80fc00
# CONSTRUCT x0f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3@8
# AUNIT --inst x0f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqrshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2062 line 115610 MATCH x0f009c00/mask=xbf80fc00
# CONSTRUCT x0f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3@4
# AUNIT --inst x0f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqrshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2062 line 115610 MATCH x0f009c00/mask=xbf80fc00
# CONSTRUCT x4f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@8
# AUNIT --inst x4f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqrshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2062 line 115610 MATCH x0f009c00/mask=xbf80fc00
# CONSTRUCT x0f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@2
# AUNIT --inst x0f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sqrshrn2(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2062 line 115610 MATCH x0f009c00/mask=xbf80fc00
# CONSTRUCT x4f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@4
# AUNIT --inst x4f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqrshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2062 line 115610 MATCH x5f009c00/mask=xff80fc00
# CONSTRUCT x5f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3
# AUNIT --inst x5f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
:sqrshrn Rd_FPR8, Rn_FPR16, Imm_shr_imm8
is b_2331=0b010111110 & b_1922=0b0001 & b_1015=0b100111 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd
{
Rd_FPR8 = NEON_sqrshrn(Rd_FPR8, Rn_FPR16, Imm_shr_imm8:1);
}
# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2062 line 115610 MATCH x5f009c00/mask=xff80fc00
# CONSTRUCT x5f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3
# AUNIT --inst x5f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
:sqrshrn Rd_FPR16, Rn_FPR32, Imm_shr_imm16
is b_2331=0b010111110 & b_2022=0b001 & b_1015=0b100111 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd
{
Rd_FPR16 = NEON_sqrshrn(Rd_FPR16, Rn_FPR32, Imm_shr_imm16:1);
}
# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2062 line 115610 MATCH x5f009c00/mask=xff80fc00
# CONSTRUCT x5f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3
# AUNIT --inst x5f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
:sqrshrn Rd_FPR32, Rn_FPR64, Imm_shr_imm32
is b_2331=0b010111110 & b_2122=0b01 & b_1015=0b100111 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd
{
Rd_FPR32 = NEON_sqrshrn(Rd_FPR32, Rn_FPR64, Imm_shr_imm32:1);
}
# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2065 line 115795 MATCH x2f008c00/mask=xbf80fc00
# CONSTRUCT x6f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun2/3@2
# AUNIT --inst x6f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshrun2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sqrshrun2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2065 line 115795 MATCH x2f008c00/mask=xbf80fc00
# CONSTRUCT x2f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3@8
# AUNIT --inst x2f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshrun Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqrshrun(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2065 line 115795 MATCH x2f008c00/mask=xbf80fc00
# CONSTRUCT x2f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3@4
# AUNIT --inst x2f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshrun Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqrshrun(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2065 line 115795 MATCH x2f008c00/mask=xbf80fc00
# CONSTRUCT x6f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun2/3@8
# AUNIT --inst x6f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshrun2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqrshrun2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2065 line 115795 MATCH x2f008c00/mask=xbf80fc00
# CONSTRUCT x2f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3@2
# AUNIT --inst x2f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshrun Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sqrshrun(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2065 line 115795 MATCH x2f008c00/mask=xbf80fc00
# CONSTRUCT x6f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun2/3@4
# AUNIT --inst x6f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
:sqrshrun2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqrshrun2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2065 line 115795 MATCH x7f008c00/mask=xff80fc00
# CONSTRUCT x7f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3
# AUNIT --inst x7f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
:sqrshrun Rd_FPR8, Rn_FPR16, Imm_shr_imm8
is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100011 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd
{
Rd_FPR8 = NEON_sqrshrun(Rd_FPR8, Rn_FPR16, Imm_shr_imm8:1);
}
# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2065 line 115795 MATCH x7f008c00/mask=xff80fc00
# CONSTRUCT x7f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3
# AUNIT --inst x7f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
:sqrshrun Rd_FPR16, Rn_FPR32, Imm_shr_imm16
is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100011 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd
{
Rd_FPR16 = NEON_sqrshrun(Rd_FPR16, Rn_FPR32, Imm_shr_imm16:1);
}
# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2065 line 115795 MATCH x7f008c00/mask=xff80fc00
# CONSTRUCT x7f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3
# AUNIT --inst x7f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
:sqrshrun Rd_FPR32, Rn_FPR64, Imm_shr_imm32
is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100011 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd
{
Rd_FPR32 = NEON_sqrshrun(Rd_FPR32, Rn_FPR64, Imm_shr_imm32:1);
}
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x0f007400/mask=xbf80fc00
# CONSTRUCT x4f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@1
# AUNIT --inst x4f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sqshl(Rn_VPR128.16B, Imm_uimm3:1, 1:1);
}
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x0f007400/mask=xbf80fc00
# CONSTRUCT x4f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@8
# AUNIT --inst x4f407400/mask=xffc0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xe & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_sqshl(Rn_VPR128.2D, Imm_imm0_63:1, 8:1);
}
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x0f007400/mask=xbf80fc00
# CONSTRUCT x0f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@4
# AUNIT --inst x0f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqshl(Rn_VPR64.2S, Imm_uimm5:1, 4:1);
}
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x0f007400/mask=xbf80fc00
# CONSTRUCT x0f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@2
# AUNIT --inst x0f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqshl(Rn_VPR64.4H, Imm_uimm4:1, 2:1);
}
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x0f007400/mask=xbf80fc00
# CONSTRUCT x4f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@4
# AUNIT --inst x4f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqshl(Rn_VPR128.4S, Imm_uimm5:1, 4:1);
}
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x0f007400/mask=xbf80fc00
# CONSTRUCT x0f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@1
# AUNIT --inst x0f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sqshl(Rn_VPR64.8B, Imm_uimm3:1, 1:1);
}
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x0f007400/mask=xbf80fc00
# CONSTRUCT x4f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@2
# AUNIT --inst x4f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqshl(Rn_VPR128.8H, Imm_uimm4:1, 2:1);
}
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x5f007400/mask=xff80fc00
# CONSTRUCT x5f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2
# AUNIT --inst x5f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=0001 V=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
:sqshl Rd_FPR8, Rn_FPR8, Imm_shr_imm8
is b_2331=0b010111110 & b_1922=0b0001 & b_1015=0b011101 & Rd_FPR8 & Rn_FPR8 & Imm_shr_imm8 & Zd
{
Rd_FPR8 = NEON_sqshl(Rn_FPR8, Imm_shr_imm8:1);
}
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x5f007400/mask=xff80fc00
# CONSTRUCT x5f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2
# AUNIT --inst x5f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=001x V=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
:sqshl Rd_FPR16, Rn_FPR16, Imm_shr_imm16
is b_2331=0b010111110 & b_2022=0b001 & b_1015=0b011101 & Rd_FPR16 & Rn_FPR16 & Imm_shr_imm16 & Zd
{
Rd_FPR16 = NEON_sqshl(Rn_FPR16, Imm_shr_imm16:1);
}
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x5f007400/mask=xff80fc00
# CONSTRUCT x5f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2
# AUNIT --inst x5f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=01xx V=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
:sqshl Rd_FPR32, Rn_FPR32, Imm_shr_imm32
is b_2331=0b010111110 & b_2122=0b01 & b_1015=0b011101 & Rd_FPR32 & Rn_FPR32 & Imm_shr_imm32 & Zd
{
Rd_FPR32 = NEON_sqshl(Rn_FPR32, Imm_shr_imm32:1);
}
# C7.2.302 SQSHL (immediate) page C7-2068 line 115975 MATCH x5f007400/mask=xff80fc00
# CONSTRUCT x5f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2
# AUNIT --inst x5f407400/mask=xffc0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=1xxx V=FPR64 imm=Imm_shr_imm64 bb=b_22 aa=1
:sqshl Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_2331=0b010111110 & b_22=1 & b_1015=0b011101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
{
Rd_FPR64 = NEON_sqshl(Rn_FPR64, Imm_shr_imm64:1);
}
# C7.2.303 SQSHL (register) page C7-2071 line 116140 MATCH x5e204c00/mask=xff20fc00
# CONSTRUCT x5e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2
# AUNIT --inst x5e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_FPR8, Rn_FPR8, Rm_FPR8
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x9 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_sqshl(Rn_FPR8, Rm_FPR8);
}
# C7.2.303 SQSHL (register) page C7-2071 line 116140 MATCH x5e204c00/mask=xff20fc00
# CONSTRUCT x5ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2
# AUNIT --inst x5ee04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x9 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_sqshl(Rn_FPR64, Rm_FPR64);
}
# C7.2.303 SQSHL (register) page C7-2071 line 116140 MATCH x5e204c00/mask=xff20fc00
# CONSTRUCT x5e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2
# AUNIT --inst x5e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x9 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_sqshl(Rn_FPR16, Rm_FPR16);
}
# C7.2.303 SQSHL (register) page C7-2071 line 116140 MATCH x5e204c00/mask=xff20fc00
# CONSTRUCT x5ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2
# AUNIT --inst x5ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x9 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_sqshl(Rn_FPR32, Rm_FPR32);
}
# C7.2.303 SQSHL (register) page C7-2071 line 116140 MATCH x0e204c00/mask=xbf20fc00
# CONSTRUCT x4e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@1
# AUNIT --inst x4e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x9 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sqshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.303 SQSHL (register) page C7-2071 line 116140 MATCH x0e204c00/mask=xbf20fc00
# CONSTRUCT x4ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@8
# AUNIT --inst x4ee04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x9 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_sqshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.303 SQSHL (register) page C7-2071 line 116140 MATCH x0e204c00/mask=xbf20fc00
# CONSTRUCT x0ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@4
# AUNIT --inst x0ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x9 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.303 SQSHL (register) page C7-2071 line 116140 MATCH x0e204c00/mask=xbf20fc00
# CONSTRUCT x0e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@2
# AUNIT --inst x0e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x9 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.303 SQSHL (register) page C7-2071 line 116140 MATCH x0e204c00/mask=xbf20fc00
# CONSTRUCT x4ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@4
# AUNIT --inst x4ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x9 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.303 SQSHL (register) page C7-2071 line 116140 MATCH x0e204c00/mask=xbf20fc00
# CONSTRUCT x0e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@1
# AUNIT --inst x0e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x9 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sqshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.303 SQSHL (register) page C7-2071 line 116140 MATCH x0e204c00/mask=xbf20fc00
# CONSTRUCT x4e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@2
# AUNIT --inst x4e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x9 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x2f006400/mask=xbf80fc00
# CONSTRUCT x6f086400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@1
# AUNIT --inst x6f086400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
:sqshlu Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xc & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sqshlu(Rn_VPR128.16B, Imm_uimm3:1, 1:1);
}
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x2f006400/mask=xbf80fc00
# CONSTRUCT x6f406400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@8
# AUNIT --inst x6f406400/mask=xffc0fc00 --status nopcodeop --comment "nointsat"
:sqshlu Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xc & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_sqshlu(Rn_VPR128.2D, Imm_imm0_63:1, 8:1);
}
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x2f006400/mask=xbf80fc00
# CONSTRUCT x2f206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@4
# AUNIT --inst x2f206400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshlu Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xc & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqshlu(Rn_VPR64.2S, Imm_uimm5:1, 4:1);
}
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x2f006400/mask=xbf80fc00
# CONSTRUCT x2f106400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@2
# AUNIT --inst x2f106400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
:sqshlu Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xc & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqshlu(Rn_VPR64.4H, Imm_uimm4:1, 2:1);
}
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x2f006400/mask=xbf80fc00
# CONSTRUCT x6f206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@4
# AUNIT --inst x6f206400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshlu Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xc & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqshlu(Rn_VPR128.4S, Imm_uimm5:1, 4:1);
}
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x2f006400/mask=xbf80fc00
# CONSTRUCT x2f086400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@1
# AUNIT --inst x2f086400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
:sqshlu Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xc & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sqshlu(Rn_VPR64.8B, Imm_uimm3:1, 1:1);
}
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x2f006400/mask=xbf80fc00
# CONSTRUCT x6f106400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@2
# AUNIT --inst x6f106400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
:sqshlu Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xc & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqshlu(Rn_VPR128.8H, Imm_uimm4:1, 2:1);
}
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x7f006400/mask=xff80fc00
# CONSTRUCT x7f086400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2
# AUNIT --inst x7f086400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=0001 V=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
:sqshlu Rd_FPR8, Rn_FPR8, Imm_shr_imm8
is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b011001 & Rd_FPR8 & Rn_FPR8 & Imm_shr_imm8 & Zd
{
Rd_FPR8 = NEON_sqshlu(Rn_FPR8, Imm_shr_imm8:1);
}
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x7f006400/mask=xff80fc00
# CONSTRUCT x7f106400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2
# AUNIT --inst x7f106400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=001x V=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
:sqshlu Rd_FPR16, Rn_FPR16, Imm_shr_imm16
is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b011001 & Rd_FPR16 & Rn_FPR16 & Imm_shr_imm16 & Zd
{
Rd_FPR16 = NEON_sqshlu(Rn_FPR16, Imm_shr_imm16:1);
}
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x7f006400/mask=xff80fc00
# CONSTRUCT x7f206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2
# AUNIT --inst x7f206400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=01xx V=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
:sqshlu Rd_FPR32, Rn_FPR32, Imm_shr_imm32
is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b011001 & Rd_FPR32 & Rn_FPR32 & Imm_shr_imm32 & Zd
{
Rd_FPR32 = NEON_sqshlu(Rn_FPR32, Imm_shr_imm32:1);
}
# C7.2.304 SQSHLU page C7-2073 line 116278 MATCH x7f006400/mask=xff80fc00
# CONSTRUCT x7f406400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2
# AUNIT --inst x7f406400/mask=xffc0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=1xxx V=FPR64 imm=Imm_shr_imm64 bb=b_22 aa=1
:sqshlu Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_2331=0b011111110 & b_22=1 & b_1015=0b011001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
{
Rd_FPR64 = NEON_sqshlu(Rn_FPR64, Imm_shr_imm64:1);
}
# C7.2.305 SQSHRN, SQSHRN2 page C7-2076 line 116443 MATCH x0f009400/mask=xbf80fc00
# CONSTRUCT x4f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn2/3@2
# AUNIT --inst x4f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
:sqshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sqshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.305 SQSHRN, SQSHRN2 page C7-2076 line 116443 MATCH x0f009400/mask=xbf80fc00
# CONSTRUCT x0f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3@8
# AUNIT --inst x0f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.305 SQSHRN, SQSHRN2 page C7-2076 line 116443 MATCH x0f009400/mask=xbf80fc00
# CONSTRUCT x0f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3@4
# AUNIT --inst x0f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
:sqshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.305 SQSHRN, SQSHRN2 page C7-2076 line 116443 MATCH x0f009400/mask=xbf80fc00
# CONSTRUCT x4f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn2/3@8
# AUNIT --inst x4f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.305 SQSHRN, SQSHRN2 page C7-2076 line 116443 MATCH x0f009400/mask=xbf80fc00
# CONSTRUCT x0f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3@2
# AUNIT --inst x0f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
:sqshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sqshrn(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.305 SQSHRN, SQSHRN2 page C7-2076 line 116443 MATCH x0f009400/mask=xbf80fc00
# CONSTRUCT x4f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn2/3@4
# AUNIT --inst x4f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
:sqshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.305 SQSHRN, SQSHRN2 page C7-2076 line 116443 MATCH x5f009400/mask=xff80fc00
# CONSTRUCT x5f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3
# AUNIT --inst x5f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
:sqshrn Rd_FPR8, Rd_FPR16, Imm_shr_imm8
is b_2331=0b010111110 & b_1922=0b0001 & b_1015=0b100101 & Rd_FPR8 & Rd_FPR16 & Imm_shr_imm8 & Zd
{
Rd_FPR8 = NEON_sqshrn(Rd_FPR8, Rd_FPR16, Imm_shr_imm8:1);
}
# C7.2.305 SQSHRN, SQSHRN2 page C7-2076 line 116443 MATCH x5f009400/mask=xff80fc00
# CONSTRUCT x5f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3
# AUNIT --inst x5f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
:sqshrn Rd_FPR16, Rd_FPR32, Imm_shr_imm16
is b_2331=0b010111110 & b_2022=0b001 & b_1015=0b100101 & Rd_FPR16 & Rd_FPR32 & Imm_shr_imm16 & Zd
{
Rd_FPR16 = NEON_sqshrn(Rd_FPR16, Rd_FPR32, Imm_shr_imm16:1);
}
# C7.2.305 SQSHRN, SQSHRN2 page C7-2076 line 116443 MATCH x5f009400/mask=xff80fc00
# CONSTRUCT x5f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3
# AUNIT --inst x5f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
:sqshrn Rd_FPR32, Rd_FPR64, Imm_shr_imm32
is b_2331=0b010111110 & b_2122=0b01 & b_1015=0b100101 & Rd_FPR32 & Rd_FPR64 & Imm_shr_imm32 & Zd
{
Rd_FPR32 = NEON_sqshrn(Rd_FPR32, Rd_FPR64, Imm_shr_imm32:1);
}
# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2079 line 116627 MATCH x2f008400/mask=xbf80fc00
# CONSTRUCT x6f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun2/3@2
# AUNIT --inst x6f088400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
:sqshrun2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sqshrun2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2079 line 116627 MATCH x2f008400/mask=xbf80fc00
# CONSTRUCT x2f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3@8
# AUNIT --inst x2f208400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshrun Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqshrun(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2079 line 116627 MATCH x2f008400/mask=xbf80fc00
# CONSTRUCT x2f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3@4
# AUNIT --inst x2f108400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
:sqshrun Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqshrun(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2079 line 116627 MATCH x2f008400/mask=xbf80fc00
# CONSTRUCT x6f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun2/3@8
# AUNIT --inst x6f208400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqshrun2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqshrun2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2079 line 116627 MATCH x2f008400/mask=xbf80fc00
# CONSTRUCT x2f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3@2
# AUNIT --inst x2f088400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
:sqshrun Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sqshrun(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2079 line 116627 MATCH x2f008400/mask=xbf80fc00
# CONSTRUCT x6f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun2/3@4
# AUNIT --inst x6f108400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
:sqshrun2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqshrun2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2079 line 116627 MATCH x7f008400/mask=xff80fc00
# CONSTRUCT x7f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3
# AUNIT --inst x7f088400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
:sqshrun Rd_FPR8, Rd_FPR16, Imm_shr_imm8
is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100001 & Rd_FPR8 & Rd_FPR16 & Imm_shr_imm8 & Zd
{
Rd_FPR8 = NEON_sqshrun(Rd_FPR8, Rd_FPR16, Imm_shr_imm8:1);
}
# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2079 line 116627 MATCH x7f008400/mask=xff80fc00
# CONSTRUCT x7f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3
# AUNIT --inst x7f108400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
:sqshrun Rd_FPR16, Rd_FPR32, Imm_shr_imm16
is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100001 & Rd_FPR16 & Rd_FPR32 & Imm_shr_imm16 & Zd
{
Rd_FPR16 = NEON_sqshrun(Rd_FPR16, Rd_FPR32, Imm_shr_imm16:1);
}
# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2079 line 116627 MATCH x7f008400/mask=xff80fc00
# CONSTRUCT x7f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3
# AUNIT --inst x7f208400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
:sqshrun Rd_FPR32, Rd_FPR64, Imm_shr_imm32
is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100001 & Rd_FPR32 & Rd_FPR64 & Imm_shr_imm32 & Zd
{
Rd_FPR32 = NEON_sqshrun(Rd_FPR32, Rd_FPR64, Imm_shr_imm32:1);
}
# C7.2.307 SQSUB page C7-2082 line 116807 MATCH x5e202c00/mask=xff20fc00
# CONSTRUCT x5e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2
# AUNIT --inst x5e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqsub Rd_FPR8, Rn_FPR8, Rm_FPR8
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x5 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_sqsub(Rn_FPR8, Rm_FPR8);
}
# C7.2.307 SQSUB page C7-2082 line 116807 MATCH x5e202c00/mask=xff20fc00
# CONSTRUCT x5ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2
# AUNIT --inst x5ee02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqsub Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x5 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_sqsub(Rn_FPR64, Rm_FPR64);
}
# C7.2.307 SQSUB page C7-2082 line 116807 MATCH x5e202c00/mask=xff20fc00
# CONSTRUCT x5e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2
# AUNIT --inst x5e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqsub Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x5 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_sqsub(Rn_FPR16, Rm_FPR16);
}
# C7.2.307 SQSUB page C7-2082 line 116807 MATCH x5e202c00/mask=xff20fc00
# CONSTRUCT x5ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2
# AUNIT --inst x5ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqsub Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x5 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_sqsub(Rn_FPR32, Rm_FPR32);
}
# C7.2.307 SQSUB page C7-2082 line 116807 MATCH x0e202c00/mask=xbf20fc00
# CONSTRUCT x4e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@1
# AUNIT --inst x4e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x5 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sqsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.307 SQSUB page C7-2082 line 116807 MATCH x0e202c00/mask=xbf20fc00
# CONSTRUCT x4ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@8
# AUNIT --inst x4ee02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqsub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x5 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_sqsub(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.307 SQSUB page C7-2082 line 116807 MATCH x0e202c00/mask=xbf20fc00
# CONSTRUCT x0ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@4
# AUNIT --inst x0ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x5 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.307 SQSUB page C7-2082 line 116807 MATCH x0e202c00/mask=xbf20fc00
# CONSTRUCT x0e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@2
# AUNIT --inst x0e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x5 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.307 SQSUB page C7-2082 line 116807 MATCH x0e202c00/mask=xbf20fc00
# CONSTRUCT x4ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@4
# AUNIT --inst x4ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x5 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.307 SQSUB page C7-2082 line 116807 MATCH x0e202c00/mask=xbf20fc00
# CONSTRUCT x0e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@1
# AUNIT --inst x0e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x5 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sqsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.307 SQSUB page C7-2082 line 116807 MATCH x0e202c00/mask=xbf20fc00
# CONSTRUCT x4e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@2
# AUNIT --inst x4e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:sqsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x5 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.308 SQXTN, SQXTN2 page C7-2084 line 116932 MATCH x5e214800/mask=xff3ffc00
# CONSTRUCT x5e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2
# AUNIT --inst x5e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
:sqxtn Rd_FPR8, Rn_FPR16
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_FPR16 & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_sqxtn(Rd_FPR8, Rn_FPR16);
}
# C7.2.308 SQXTN, SQXTN2 page C7-2084 line 116932 MATCH x5e214800/mask=xff3ffc00
# CONSTRUCT x5e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2
# AUNIT --inst x5e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
:sqxtn Rd_FPR16, Rn_FPR32
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_FPR32 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_sqxtn(Rd_FPR16, Rn_FPR32);
}
# C7.2.308 SQXTN, SQXTN2 page C7-2084 line 116932 MATCH x5e214800/mask=xff3ffc00
# CONSTRUCT x5ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2
# AUNIT --inst x5ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
:sqxtn Rd_FPR32, Rn_FPR64
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_FPR64 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_sqxtn(Rd_FPR32, Rn_FPR64);
}
# C7.2.308 SQXTN, SQXTN2 page C7-2084 line 116932 MATCH x0e214800/mask=xbf3ffc00
# CONSTRUCT x4e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn2/2@2
# AUNIT --inst x4e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
:sqxtn2 Rd_VPR128.16B, Rn_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sqxtn2(Rd_VPR128.16B, Rn_VPR128.8H, 2:1);
}
# C7.2.308 SQXTN, SQXTN2 page C7-2084 line 116932 MATCH x0e214800/mask=xbf3ffc00
# CONSTRUCT x4e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn2/2@4
# AUNIT --inst x4e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
:sqxtn2 Rd_VPR128.8H, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sqxtn2(Rd_VPR128.8H, Rn_VPR128.4S, 4:1);
}
# C7.2.308 SQXTN, SQXTN2 page C7-2084 line 116932 MATCH x0e214800/mask=xbf3ffc00
# CONSTRUCT x4ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn2/2@8
# AUNIT --inst x4ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
:sqxtn2 Rd_VPR128.4S, Rn_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sqxtn2(Rd_VPR128.4S, Rn_VPR128.2D, 8:1);
}
# C7.2.308 SQXTN, SQXTN2 page C7-2084 line 116932 MATCH x0e214800/mask=xbf3ffc00
# CONSTRUCT x0ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2@8
# AUNIT --inst x0ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
:sqxtn Rd_VPR64.2S, Rn_VPR128.2D
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sqxtn(Rd_VPR64.2S, Rn_VPR128.2D, 8:1);
}
# C7.2.308 SQXTN, SQXTN2 page C7-2084 line 116932 MATCH x0e214800/mask=xbf3ffc00
# CONSTRUCT x0e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2@4
# AUNIT --inst x0e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
:sqxtn Rd_VPR64.4H, Rn_VPR128.4S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sqxtn(Rd_VPR64.4H, Rn_VPR128.4S, 4:1);
}
# C7.2.308 SQXTN, SQXTN2 page C7-2084 line 116932 MATCH x0e214800/mask=xbf3ffc00
# CONSTRUCT x0e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2@2
# AUNIT --inst x0e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
:sqxtn Rd_VPR64.8B, Rn_VPR128.8H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sqxtn(Rd_VPR64.8B, Rn_VPR128.8H, 2:1);
}
# C7.2.309 SQXTUN, SQXTUN2 page C7-2087 line 117086 MATCH x7e212800/mask=xff3ffc00
# CONSTRUCT x7e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2
# AUNIT --inst x7e212800/mask=xfffffc00 --status noqemu --comment "nointsat"
# Scalar variant when size=00 Q=1 bb=1 Ta=FPR16 Tb=FPR8
:sqxtun Rd_FPR8, Rn_FPR16
is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100001001010 & Rd_FPR8 & Rn_FPR16 & Zd
{
Rd_FPR8 = NEON_sqxtun(Rd_FPR8, Rn_FPR16);
}
# C7.2.309 SQXTUN, SQXTUN2 page C7-2087 line 117086 MATCH x7e212800/mask=xff3ffc00
# CONSTRUCT x7e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2
# AUNIT --inst x7e612800/mask=xfffffc00 --status noqemu --comment "nointsat"
# Scalar variant when size=01 Q=1 bb=1 Ta=FPR32 Tb=FPR16
:sqxtun Rd_FPR16, Rn_FPR32
is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100001001010 & Rd_FPR16 & Rn_FPR32 & Zd
{
Rd_FPR16 = NEON_sqxtun(Rd_FPR16, Rn_FPR32);
}
# C7.2.309 SQXTUN, SQXTUN2 page C7-2087 line 117086 MATCH x7e212800/mask=xff3ffc00
# CONSTRUCT x7ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2
# AUNIT --inst x7ea12800/mask=xfffffc00 --status noqemu --comment "nointsat"
# Scalar variant when size=10 Q=1 bb=1 Ta=FPR64 Tb=FPR32
:sqxtun Rd_FPR32, Rn_FPR64
is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100001001010 & Rd_FPR32 & Rn_FPR64 & Zd
{
Rd_FPR32 = NEON_sqxtun(Rd_FPR32, Rn_FPR64);
}
# C7.2.309 SQXTUN, SQXTUN2 page C7-2087 line 117086 MATCH x2e212800/mask=xbf3ffc00
# CONSTRUCT x2e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2@2
# AUNIT --inst x2e212800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=00 Q=0 bb=0 Ta=VPR128.8H Tb=VPR64.8B esize=2
:sqxtun Rd_VPR64.8B, Rn_VPR128.8H
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001001010 & Rd_VPR64.8B & Rn_VPR128.8H & Zd
{
Rd_VPR64.8B = NEON_sqxtun(Rd_VPR64.8B, Rn_VPR128.8H, 2:1);
}
# C7.2.309 SQXTUN, SQXTUN2 page C7-2087 line 117086 MATCH x2e212800/mask=xbf3ffc00
# CONSTRUCT x6e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun2/2@2
# AUNIT --inst x6e212800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=00 Q=1 bb=0 Ta=VPR128.8H Tb=VPR128.16B esize=2
:sqxtun2 Rd_VPR128.16B, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001001010 & Rd_VPR128.16B & Rn_VPR128.8H & Zd
{
Rd_VPR128.16B = NEON_sqxtun2(Rd_VPR128.16B, Rn_VPR128.8H, 2:1);
}
# C7.2.309 SQXTUN, SQXTUN2 page C7-2087 line 117086 MATCH x2e212800/mask=xbf3ffc00
# CONSTRUCT x2e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2@4
# AUNIT --inst x2e612800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=01 Q=0 bb=0 Ta=VPR128.4S Tb=VPR64.4H esize=4
:sqxtun Rd_VPR64.4H, Rn_VPR128.4S
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001001010 & Rd_VPR64.4H & Rn_VPR128.4S & Zd
{
Rd_VPR64.4H = NEON_sqxtun(Rd_VPR64.4H, Rn_VPR128.4S, 4:1);
}
# C7.2.309 SQXTUN, SQXTUN2 page C7-2087 line 117086 MATCH x2e212800/mask=xbf3ffc00
# CONSTRUCT x6e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun2/2@4
# AUNIT --inst x6e612800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=01 Q=1 bb=0 Ta=VPR128.4S Tb=VPR128.8H esize=4
:sqxtun2 Rd_VPR128.8H, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001001010 & Rd_VPR128.8H & Rn_VPR128.4S & Zd
{
Rd_VPR128.8H = NEON_sqxtun2(Rd_VPR128.8H, Rn_VPR128.4S, 4:1);
}
# C7.2.309 SQXTUN, SQXTUN2 page C7-2087 line 117086 MATCH x2e212800/mask=xbf3ffc00
# CONSTRUCT x2ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2@8
# AUNIT --inst x2ea12800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=10 Q=0 bb=0 Ta=VPR128.2D Tb=VPR64.2S esize=8
:sqxtun Rd_VPR64.2S, Rn_VPR128.2D
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001001010 & Rd_VPR64.2S & Rn_VPR128.2D & Zd
{
Rd_VPR64.2S = NEON_sqxtun(Rd_VPR64.2S, Rn_VPR128.2D, 8:1);
}
# C7.2.309 SQXTUN, SQXTUN2 page C7-2087 line 117086 MATCH x2e212800/mask=xbf3ffc00
# CONSTRUCT x6ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun2/2@8
# AUNIT --inst x6ea12800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=10 Q=1 bb=0 Ta=VPR128.2D Tb=VPR128.4S esize=8
:sqxtun2 Rd_VPR128.4S, Rn_VPR128.2D
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001001010 & Rd_VPR128.4S & Rn_VPR128.2D & Zd
{
Rd_VPR128.4S = NEON_sqxtun2(Rd_VPR128.4S, Rn_VPR128.2D, 8:1);
}
# C7.2.310 SRHADD page C7-2090 line 117237 MATCH x0e201400/mask=xbf20fc00
# CONSTRUCT x4e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@1
# AUNIT --inst x4e201400/mask=xffe0fc00 --status nopcodeop
:srhadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rn_VPR128.16B = NEON_srhadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.310 SRHADD page C7-2090 line 117237 MATCH x0e201400/mask=xbf20fc00
# CONSTRUCT x0ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@4
# AUNIT --inst x0ea01400/mask=xffe0fc00 --status nopcodeop
:srhadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rn_VPR64.2S = NEON_srhadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.310 SRHADD page C7-2090 line 117237 MATCH x0e201400/mask=xbf20fc00
# CONSTRUCT x0e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@2
# AUNIT --inst x0e601400/mask=xffe0fc00 --status nopcodeop
:srhadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rn_VPR64.4H = NEON_srhadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.310 SRHADD page C7-2090 line 117237 MATCH x0e201400/mask=xbf20fc00
# CONSTRUCT x4ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@4
# AUNIT --inst x4ea01400/mask=xffe0fc00 --status nopcodeop
:srhadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rn_VPR128.4S = NEON_srhadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.310 SRHADD page C7-2090 line 117237 MATCH x0e201400/mask=xbf20fc00
# CONSTRUCT x0e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@1
# AUNIT --inst x0e201400/mask=xffe0fc00 --status nopcodeop
:srhadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rn_VPR64.8B = NEON_srhadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.310 SRHADD page C7-2090 line 117237 MATCH x0e201400/mask=xbf20fc00
# CONSTRUCT x4e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@2
# AUNIT --inst x4e601400/mask=xffe0fc00 --status nopcodeop
:srhadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rn_VPR128.8H = NEON_srhadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.311 SRI page C7-2092 line 117324 MATCH x2f004400/mask=xbf80fc00
# CONSTRUCT x6f084400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@1
# AUNIT --inst x6f084400/mask=xfff8fc00 --status nopcodeop
:sri Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x8 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sri(Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8:4, 1:1);
}
# C7.2.311 SRI page C7-2092 line 117324 MATCH x2f004400/mask=xbf80fc00
# CONSTRUCT x6f404400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@8
# AUNIT --inst x6f404400/mask=xffc0fc00 --status nopcodeop
:sri Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x8 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_sri(Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64:4, 8:1);
}
# C7.2.311 SRI page C7-2092 line 117324 MATCH x2f004400/mask=xbf80fc00
# CONSTRUCT x2f204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@4
# AUNIT --inst x2f204400/mask=xffe0fc00 --status nopcodeop
:sri Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x8 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sri(Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32:4, 4:1);
}
# C7.2.311 SRI page C7-2092 line 117324 MATCH x2f004400/mask=xbf80fc00
# CONSTRUCT x2f104400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@2
# AUNIT --inst x2f104400/mask=xfff0fc00 --status nopcodeop
:sri Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x8 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sri(Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16:4, 2:1);
}
# C7.2.311 SRI page C7-2092 line 117324 MATCH x2f004400/mask=xbf80fc00
# CONSTRUCT x6f204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@4
# AUNIT --inst x6f204400/mask=xffe0fc00 --status nopcodeop
:sri Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x8 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sri(Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32:4, 4:1);
}
# C7.2.311 SRI page C7-2092 line 117324 MATCH x2f004400/mask=xbf80fc00
# CONSTRUCT x2f084400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@1
# AUNIT --inst x2f084400/mask=xfff8fc00 --status nopcodeop
:sri Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x8 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sri(Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8:4, 1:1);
}
# C7.2.311 SRI page C7-2092 line 117324 MATCH x2f004400/mask=xbf80fc00
# CONSTRUCT x6f104400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@2
# AUNIT --inst x6f104400/mask=xfff0fc00 --status nopcodeop
:sri Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x8 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sri(Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16:4, 2:1);
}
# C7.2.311 SRI page C7-2092 line 117324 MATCH x7f004400/mask=xff80fc00
# CONSTRUCT x7f404400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sri/3
# AUNIT --inst x7f404400/mask=xffc0fc00 --status nopcodeop
:sri Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_2331=0b011111110 & b_22=1 & b_1015=0b010001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
{
Rd_FPR64 = NEON_sri(Rd_FPR64, Rn_FPR64, Imm_shr_imm64:1);
}
# C7.2.312 SRSHL page C7-2095 line 117488 MATCH x5e205400/mask=xff20fc00
# CONSTRUCT x5ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2
# AUNIT --inst x5ee05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:srshl Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xa & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_srshl(Rn_FPR64, Rm_FPR64);
}
# C7.2.312 SRSHL page C7-2095 line 117488 MATCH x0e205400/mask=xbf20fc00
# CONSTRUCT x4e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@1
# AUNIT --inst x4e205400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:srshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_srshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.312 SRSHL page C7-2095 line 117488 MATCH x0e205400/mask=xbf20fc00
# CONSTRUCT x4ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@8
# AUNIT --inst x4ee05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:srshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_srshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.312 SRSHL page C7-2095 line 117488 MATCH x0e205400/mask=xbf20fc00
# CONSTRUCT x0ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@4
# AUNIT --inst x0ea05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:srshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_srshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.312 SRSHL page C7-2095 line 117488 MATCH x0e205400/mask=xbf20fc00
# CONSTRUCT x0e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@2
# AUNIT --inst x0e605400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:srshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_srshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.312 SRSHL page C7-2095 line 117488 MATCH x0e205400/mask=xbf20fc00
# CONSTRUCT x4ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@4
# AUNIT --inst x4ea05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:srshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_srshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.312 SRSHL page C7-2095 line 117488 MATCH x0e205400/mask=xbf20fc00
# CONSTRUCT x0e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@1
# AUNIT --inst x0e205400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:srshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_srshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.312 SRSHL page C7-2095 line 117488 MATCH x0e205400/mask=xbf20fc00
# CONSTRUCT x4e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@2
# AUNIT --inst x4e605400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:srshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_srshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.313 SRSHR page C7-2097 line 117624 MATCH x0f002400/mask=xbf80fc00
# CONSTRUCT x4f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@1
# AUNIT --inst x4f082400/mask=xfff8fc00 --status nopcodeop --comment "nointround"
:srshr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_srshr(Rn_VPR128.16B, Imm_shr_imm8:1, 1:1);
}
# C7.2.313 SRSHR page C7-2097 line 117624 MATCH x0f002400/mask=xbf80fc00
# CONSTRUCT x4f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@8
# AUNIT --inst x4f402400/mask=xffc0fc00 --status nopcodeop --comment "nointround"
:srshr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x4 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_srshr(Rn_VPR128.2D, Imm_shr_imm64:1, 8:1);
}
# C7.2.313 SRSHR page C7-2097 line 117624 MATCH x0f002400/mask=xbf80fc00
# CONSTRUCT x0f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@4
# AUNIT --inst x0f202400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:srshr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_srshr(Rn_VPR64.2S, Imm_shr_imm32:1, 4:1);
}
# C7.2.313 SRSHR page C7-2097 line 117624 MATCH x0f002400/mask=xbf80fc00
# CONSTRUCT x0f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@2
# AUNIT --inst x0f102400/mask=xfff0fc00 --status nopcodeop --comment "nointround"
:srshr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_srshr(Rn_VPR64.4H, Imm_shr_imm16:1, 2:1);
}
# C7.2.313 SRSHR page C7-2097 line 117624 MATCH x0f002400/mask=xbf80fc00
# CONSTRUCT x4f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@4
# AUNIT --inst x4f202400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:srshr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_srshr(Rn_VPR128.4S, Imm_shr_imm32:1, 4:1);
}
# C7.2.313 SRSHR page C7-2097 line 117624 MATCH x0f002400/mask=xbf80fc00
# CONSTRUCT x0f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@1
# AUNIT --inst x0f082400/mask=xfff8fc00 --status nopcodeop --comment "nointround"
:srshr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_srshr(Rn_VPR64.8B, Imm_shr_imm8:1, 1:1);
}
# C7.2.313 SRSHR page C7-2097 line 117624 MATCH x0f002400/mask=xbf80fc00
# CONSTRUCT x4f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@2
# AUNIT --inst x4f102400/mask=xfff0fc00 --status nopcodeop --comment "nointround"
:srshr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_srshr(Rn_VPR128.8H, Imm_shr_imm16:1, 2:1);
}
# C7.2.313 SRSHR page C7-2097 line 117624 MATCH x5f002400/mask=xff80fc00
# CONSTRUCT x5f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2
# AUNIT --inst x5f402400/mask=xffc0fc00 --status nopcodeop --comment "nointround"
:srshr Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_2331=0b010111110 & b_22=1 & b_1015=0b001001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
{
Rd_FPR64 = NEON_srshr(Rn_FPR64, Imm_shr_imm64:1);
}
# C7.2.314 SRSRA page C7-2099 line 117760 MATCH x0f003400/mask=xbf80fc00
# CONSTRUCT x4f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@1
# AUNIT --inst x4f083400/mask=xfff8fc00 --status fail --comment "nointround"
:srsra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix TMPQ1 = Rn_VPR128.16B s>> Imm_shr_imm8:1 on lane size 1
TMPQ1[0,8] = Rn_VPR128.16B[0,8] s>> Imm_shr_imm8:1;
TMPQ1[8,8] = Rn_VPR128.16B[8,8] s>> Imm_shr_imm8:1;
TMPQ1[16,8] = Rn_VPR128.16B[16,8] s>> Imm_shr_imm8:1;
TMPQ1[24,8] = Rn_VPR128.16B[24,8] s>> Imm_shr_imm8:1;
TMPQ1[32,8] = Rn_VPR128.16B[32,8] s>> Imm_shr_imm8:1;
TMPQ1[40,8] = Rn_VPR128.16B[40,8] s>> Imm_shr_imm8:1;
TMPQ1[48,8] = Rn_VPR128.16B[48,8] s>> Imm_shr_imm8:1;
TMPQ1[56,8] = Rn_VPR128.16B[56,8] s>> Imm_shr_imm8:1;
TMPQ1[64,8] = Rn_VPR128.16B[64,8] s>> Imm_shr_imm8:1;
TMPQ1[72,8] = Rn_VPR128.16B[72,8] s>> Imm_shr_imm8:1;
TMPQ1[80,8] = Rn_VPR128.16B[80,8] s>> Imm_shr_imm8:1;
TMPQ1[88,8] = Rn_VPR128.16B[88,8] s>> Imm_shr_imm8:1;
TMPQ1[96,8] = Rn_VPR128.16B[96,8] s>> Imm_shr_imm8:1;
TMPQ1[104,8] = Rn_VPR128.16B[104,8] s>> Imm_shr_imm8:1;
TMPQ1[112,8] = Rn_VPR128.16B[112,8] s>> Imm_shr_imm8:1;
TMPQ1[120,8] = Rn_VPR128.16B[120,8] s>> Imm_shr_imm8:1;
# simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1
Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];
Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];
Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];
Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];
Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];
Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];
Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];
Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];
Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];
Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];
Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];
Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];
Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];
Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];
Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];
Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.314 SRSRA page C7-2099 line 117760 MATCH x0f003400/mask=xbf80fc00
# CONSTRUCT x4f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 $s>>@8 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@8
# AUNIT --inst x4f403400/mask=xffc0fc00 --status fail --comment "nointround"
:srsra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
# simd infix TMPQ1 = Rn_VPR128.2D s>> tmp1 on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] s>> tmp1;
TMPQ1[64,64] = Rn_VPR128.2D[64,64] s>> tmp1;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.314 SRSRA page C7-2099 line 117760 MATCH x0f003400/mask=xbf80fc00
# CONSTRUCT x0f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:4 $s>>@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@4
# AUNIT --inst x0f203400/mask=xffe0fc00 --status fail --comment "nointround"
:srsra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix TMPD1 = Rn_VPR64.2S s>> Imm_shr_imm32:4 on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] s>> Imm_shr_imm32:4;
TMPD1[32,32] = Rn_VPR64.2S[32,32] s>> Imm_shr_imm32:4;
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.314 SRSRA page C7-2099 line 117760 MATCH x0f003400/mask=xbf80fc00
# CONSTRUCT x0f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@2
# AUNIT --inst x0f103400/mask=xfff0fc00 --status fail --comment "nointround"
:srsra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd infix TMPD1 = Rn_VPR64.4H s>> Imm_shr_imm16:2 on lane size 2
TMPD1[0,16] = Rn_VPR64.4H[0,16] s>> Imm_shr_imm16:2;
TMPD1[16,16] = Rn_VPR64.4H[16,16] s>> Imm_shr_imm16:2;
TMPD1[32,16] = Rn_VPR64.4H[32,16] s>> Imm_shr_imm16:2;
TMPD1[48,16] = Rn_VPR64.4H[48,16] s>> Imm_shr_imm16:2;
# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.314 SRSRA page C7-2099 line 117760 MATCH x0f003400/mask=xbf80fc00
# CONSTRUCT x4f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:4 $s>>@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@4
# AUNIT --inst x4f203400/mask=xffe0fc00 --status fail --comment "nointround"
:srsra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S s>> Imm_shr_imm32:4 on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] s>> Imm_shr_imm32:4;
TMPQ1[32,32] = Rn_VPR128.4S[32,32] s>> Imm_shr_imm32:4;
TMPQ1[64,32] = Rn_VPR128.4S[64,32] s>> Imm_shr_imm32:4;
TMPQ1[96,32] = Rn_VPR128.4S[96,32] s>> Imm_shr_imm32:4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.314 SRSRA page C7-2099 line 117760 MATCH x0f003400/mask=xbf80fc00
# CONSTRUCT x0f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@1
# AUNIT --inst x0f083400/mask=xfff8fc00 --status fail --comment "nointround"
:srsra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix TMPD1 = Rn_VPR64.8B s>> Imm_shr_imm8:1 on lane size 1
TMPD1[0,8] = Rn_VPR64.8B[0,8] s>> Imm_shr_imm8:1;
TMPD1[8,8] = Rn_VPR64.8B[8,8] s>> Imm_shr_imm8:1;
TMPD1[16,8] = Rn_VPR64.8B[16,8] s>> Imm_shr_imm8:1;
TMPD1[24,8] = Rn_VPR64.8B[24,8] s>> Imm_shr_imm8:1;
TMPD1[32,8] = Rn_VPR64.8B[32,8] s>> Imm_shr_imm8:1;
TMPD1[40,8] = Rn_VPR64.8B[40,8] s>> Imm_shr_imm8:1;
TMPD1[48,8] = Rn_VPR64.8B[48,8] s>> Imm_shr_imm8:1;
TMPD1[56,8] = Rn_VPR64.8B[56,8] s>> Imm_shr_imm8:1;
# simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1
Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];
Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];
Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];
Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];
Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];
Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];
Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];
Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.314 SRSRA page C7-2099 line 117760 MATCH x0f003400/mask=xbf80fc00
# CONSTRUCT x4f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@2
# AUNIT --inst x4f103400/mask=xfff0fc00 --status fail --comment "nointround"
:srsra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H s>> Imm_shr_imm16:2 on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] s>> Imm_shr_imm16:2;
TMPQ1[16,16] = Rn_VPR128.8H[16,16] s>> Imm_shr_imm16:2;
TMPQ1[32,16] = Rn_VPR128.8H[32,16] s>> Imm_shr_imm16:2;
TMPQ1[48,16] = Rn_VPR128.8H[48,16] s>> Imm_shr_imm16:2;
TMPQ1[64,16] = Rn_VPR128.8H[64,16] s>> Imm_shr_imm16:2;
TMPQ1[80,16] = Rn_VPR128.8H[80,16] s>> Imm_shr_imm16:2;
TMPQ1[96,16] = Rn_VPR128.8H[96,16] s>> Imm_shr_imm16:2;
TMPQ1[112,16] = Rn_VPR128.8H[112,16] s>> Imm_shr_imm16:2;
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.314 SRSRA page C7-2099 line 117760 MATCH x5f003400/mask=xff80fc00
# CONSTRUCT x5f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 s>> &=+
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3
# AUNIT --inst x5f403400/mask=xffc0fc00 --status fail --comment "nointround"
:srsra Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_2331=0b010111110 & b_22=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
local tmp2:8 = Rn_FPR64 s>> tmp1;
Rd_FPR64 = Rd_FPR64 + tmp2;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.315 SSHL page C7-2101 line 117896 MATCH x5e204400/mask=xff20fc00
# CONSTRUCT x5ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2
# AUNIT --inst x5ee04400/mask=xffe0fc00 --status nopcodeop
:sshl Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x8 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_sshl(Rn_FPR64, Rm_FPR64);
}
# C7.2.315 SSHL page C7-2101 line 117896 MATCH x0e204400/mask=xbf20fc00
# CONSTRUCT x4e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@1
# AUNIT --inst x4e204400/mask=xffe0fc00 --status nopcodeop
:sshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x8 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_sshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.315 SSHL page C7-2101 line 117896 MATCH x0e204400/mask=xbf20fc00
# CONSTRUCT x4ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@8
# AUNIT --inst x4ee04400/mask=xffe0fc00 --status nopcodeop
:sshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x8 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_sshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.315 SSHL page C7-2101 line 117896 MATCH x0e204400/mask=xbf20fc00
# CONSTRUCT x0ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@4
# AUNIT --inst x0ea04400/mask=xffe0fc00 --status nopcodeop
:sshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x8 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_sshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.315 SSHL page C7-2101 line 117896 MATCH x0e204400/mask=xbf20fc00
# CONSTRUCT x0e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@2
# AUNIT --inst x0e604400/mask=xffe0fc00 --status nopcodeop
:sshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x8 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_sshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.315 SSHL page C7-2101 line 117896 MATCH x0e204400/mask=xbf20fc00
# CONSTRUCT x4ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@4
# AUNIT --inst x4ea04400/mask=xffe0fc00 --status nopcodeop
:sshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x8 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_sshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.315 SSHL page C7-2101 line 117896 MATCH x0e204400/mask=xbf20fc00
# CONSTRUCT x0e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@1
# AUNIT --inst x0e204400/mask=xffe0fc00 --status nopcodeop
:sshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x8 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_sshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.315 SSHL page C7-2101 line 117896 MATCH x0e204400/mask=xbf20fc00
# CONSTRUCT x4e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@2
# AUNIT --inst x4e604400/mask=xffe0fc00 --status nopcodeop
:sshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x8 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_sshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# CONSTRUCT x4f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3 =var:2 =$<<@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll2/2@1
# AUNIT --inst x4f08a400/mask=xfff8fc00 --status pass --comment "ext"
:sshll2 Rd_VPR128.8H, Rn_VPR128.16B, Imm_uimm3
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = sext(TMPD1[0,8]);
TMPQ2[16,16] = sext(TMPD1[8,8]);
TMPQ2[32,16] = sext(TMPD1[16,8]);
TMPQ2[48,16] = sext(TMPD1[24,8]);
TMPQ2[64,16] = sext(TMPD1[32,8]);
TMPQ2[80,16] = sext(TMPD1[40,8]);
TMPQ2[96,16] = sext(TMPD1[48,8]);
TMPQ2[112,16] = sext(TMPD1[56,8]);
local tmp3:2 = Imm_uimm3;
# simd infix Rd_VPR128.8H = TMPQ2 << tmp3 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ2[0,16] << tmp3;
Rd_VPR128.8H[16,16] = TMPQ2[16,16] << tmp3;
Rd_VPR128.8H[32,16] = TMPQ2[32,16] << tmp3;
Rd_VPR128.8H[48,16] = TMPQ2[48,16] << tmp3;
Rd_VPR128.8H[64,16] = TMPQ2[64,16] << tmp3;
Rd_VPR128.8H[80,16] = TMPQ2[80,16] << tmp3;
Rd_VPR128.8H[96,16] = TMPQ2[96,16] << tmp3;
Rd_VPR128.8H[112,16] = TMPQ2[112,16] << tmp3;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# CONSTRUCT x0f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 =var:8 =$<<@8
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll/2@4
# AUNIT --inst x0f20a400/mask=xffe0fc00 --status pass --comment "ext"
:sshll Rd_VPR128.2D, Rn_VPR64.2S, Imm_uimm5
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
local tmp2:8 = Imm_uimm5;
# simd infix Rd_VPR128.2D = TMPQ1 << tmp2 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64] << tmp2;
Rd_VPR128.2D[64,64] = TMPQ1[64,64] << tmp2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# CONSTRUCT x0f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 =var:4 =$<<@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll/2@2
# AUNIT --inst x0f10a400/mask=xfff0fc00 --status pass --comment "ext"
:sshll Rd_VPR128.4S, Rn_VPR64.4H, Imm_uimm4
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
local tmp2:4 = Imm_uimm4;
# simd infix Rd_VPR128.4S = TMPQ1 << tmp2 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32] << tmp2;
Rd_VPR128.4S[32,32] = TMPQ1[32,32] << tmp2;
Rd_VPR128.4S[64,32] = TMPQ1[64,32] << tmp2;
Rd_VPR128.4S[96,32] = TMPQ1[96,32] << tmp2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# CONSTRUCT x4f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 =var:8 =$<<@8
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll2/2@4
# AUNIT --inst x4f20a400/mask=xffe0fc00 --status pass --comment "ext"
:sshll2 Rd_VPR128.2D, Rn_VPR128.4S, Imm_uimm5
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
local tmp3:8 = Imm_uimm5;
# simd infix Rd_VPR128.2D = TMPQ2 << tmp3 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ2[0,64] << tmp3;
Rd_VPR128.2D[64,64] = TMPQ2[64,64] << tmp3;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# CONSTRUCT x0f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@1:16 ARG3 =var:2 =$<<@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll/2@1
# AUNIT --inst x0f08a400/mask=xfff8fc00 --status pass --comment "ext"
:sshll Rd_VPR128.8H, Rn_VPR64.8B, Imm_uimm3
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
local tmp2:2 = Imm_uimm3;
# simd infix Rd_VPR128.8H = TMPQ1 << tmp2 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[0,16] << tmp2;
Rd_VPR128.8H[16,16] = TMPQ1[16,16] << tmp2;
Rd_VPR128.8H[32,16] = TMPQ1[32,16] << tmp2;
Rd_VPR128.8H[48,16] = TMPQ1[48,16] << tmp2;
Rd_VPR128.8H[64,16] = TMPQ1[64,16] << tmp2;
Rd_VPR128.8H[80,16] = TMPQ1[80,16] << tmp2;
Rd_VPR128.8H[96,16] = TMPQ1[96,16] << tmp2;
Rd_VPR128.8H[112,16] = TMPQ1[112,16] << tmp2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# CONSTRUCT x4f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 =var:4 =$<<@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll2/2@2
# AUNIT --inst x4f10a400/mask=xfff0fc00 --status pass --comment "ext"
:sshll2 Rd_VPR128.4S, Rn_VPR128.8H, Imm_uimm4
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
local tmp3:4 = Imm_uimm4;
# simd infix Rd_VPR128.4S = TMPQ2 << tmp3 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ2[0,32] << tmp3;
Rd_VPR128.4S[32,32] = TMPQ2[32,32] << tmp3;
Rd_VPR128.4S[64,32] = TMPQ2[64,32] << tmp3;
Rd_VPR128.4S[96,32] = TMPQ2[96,32] << tmp3;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.317 SSHR page C7-2106 line 118183 MATCH x5f000400/mask=xff80fc00
# CONSTRUCT x5f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2
# AUNIT --inst x5f400400/mask=xffc0fc00 --status nopcodeop
:sshr Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_3031=1 & u=0 & b_2428=0x1f & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x0 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_sshr(Rn_FPR64, Imm_shr_imm64:1);
}
# C7.2.317 SSHR page C7-2106 line 118183 MATCH x0f000400/mask=xbf80fc00
# CONSTRUCT x4f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:1 =$s>>@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@1
# AUNIT --inst x4f080400/mask=xfff8fc00 --status pass
:sshr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix Rd_VPR128.16B = Rn_VPR128.16B s>> Imm_shr_imm8:1 on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] s>> Imm_shr_imm8:1;
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] s>> Imm_shr_imm8:1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.317 SSHR page C7-2106 line 118183 MATCH x0f000400/mask=xbf80fc00
# CONSTRUCT x4f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 =$s>>@8
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@8
# AUNIT --inst x4f400400/mask=xffc0fc00 --status pass
:sshr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x0 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
# simd infix Rd_VPR128.2D = Rn_VPR128.2D s>> tmp1 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] s>> tmp1;
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] s>> tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.317 SSHR page C7-2106 line 118183 MATCH x0f000400/mask=xbf80fc00
# CONSTRUCT x0f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:4 =$s>>@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@4
# AUNIT --inst x0f200400/mask=xffe0fc00 --status pass
:sshr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
local tmp1:4 = Imm_shr_imm32;
# simd infix Rd_VPR64.2S = Rn_VPR64.2S s>> tmp1 on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] s>> tmp1;
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] s>> tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.317 SSHR page C7-2106 line 118183 MATCH x0f000400/mask=xbf80fc00
# CONSTRUCT x0f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 =$s>>@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@2
# AUNIT --inst x0f100400/mask=xfff0fc00 --status pass
:sshr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd infix Rd_VPR64.4H = Rn_VPR64.4H s>> Imm_shr_imm16:2 on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] s>> Imm_shr_imm16:2;
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] s>> Imm_shr_imm16:2;
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] s>> Imm_shr_imm16:2;
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] s>> Imm_shr_imm16:2;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.317 SSHR page C7-2106 line 118183 MATCH x0f000400/mask=xbf80fc00
# CONSTRUCT x4f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:4 =$s>>@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@4
# AUNIT --inst x4f200400/mask=xffe0fc00 --status pass
:sshr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
local tmp1:4 = Imm_shr_imm32;
# simd infix Rd_VPR128.4S = Rn_VPR128.4S s>> tmp1 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] s>> tmp1;
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] s>> tmp1;
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] s>> tmp1;
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] s>> tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.317 SSHR page C7-2106 line 118183 MATCH x0f000400/mask=xbf80fc00
# CONSTRUCT x0f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:1 =$s>>@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@1
# AUNIT --inst x0f080400/mask=xfff8fc00 --status pass
:sshr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix Rd_VPR64.8B = Rn_VPR64.8B s>> Imm_shr_imm8:1 on lane size 1
Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] s>> Imm_shr_imm8:1;
Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] s>> Imm_shr_imm8:1;
Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] s>> Imm_shr_imm8:1;
Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] s>> Imm_shr_imm8:1;
Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] s>> Imm_shr_imm8:1;
Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] s>> Imm_shr_imm8:1;
Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] s>> Imm_shr_imm8:1;
Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] s>> Imm_shr_imm8:1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.317 SSHR page C7-2106 line 118183 MATCH x0f000400/mask=xbf80fc00
# CONSTRUCT x4f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 =$s>>@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@2
# AUNIT --inst x4f100400/mask=xfff0fc00 --status pass
:sshr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd infix Rd_VPR128.8H = Rn_VPR128.8H s>> Imm_shr_imm16:2 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] s>> Imm_shr_imm16:2;
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] s>> Imm_shr_imm16:2;
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] s>> Imm_shr_imm16:2;
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] s>> Imm_shr_imm16:2;
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] s>> Imm_shr_imm16:2;
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] s>> Imm_shr_imm16:2;
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] s>> Imm_shr_imm16:2;
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] s>> Imm_shr_imm16:2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.318 SSRA page C7-2109 line 118340 MATCH x0f001400/mask=xbf80fc00
# CONSTRUCT x4f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@1
# AUNIT --inst x4f081400/mask=xfff8fc00 --status pass
:ssra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix TMPQ1 = Rn_VPR128.16B s>> Imm_shr_imm8:1 on lane size 1
TMPQ1[0,8] = Rn_VPR128.16B[0,8] s>> Imm_shr_imm8:1;
TMPQ1[8,8] = Rn_VPR128.16B[8,8] s>> Imm_shr_imm8:1;
TMPQ1[16,8] = Rn_VPR128.16B[16,8] s>> Imm_shr_imm8:1;
TMPQ1[24,8] = Rn_VPR128.16B[24,8] s>> Imm_shr_imm8:1;
TMPQ1[32,8] = Rn_VPR128.16B[32,8] s>> Imm_shr_imm8:1;
TMPQ1[40,8] = Rn_VPR128.16B[40,8] s>> Imm_shr_imm8:1;
TMPQ1[48,8] = Rn_VPR128.16B[48,8] s>> Imm_shr_imm8:1;
TMPQ1[56,8] = Rn_VPR128.16B[56,8] s>> Imm_shr_imm8:1;
TMPQ1[64,8] = Rn_VPR128.16B[64,8] s>> Imm_shr_imm8:1;
TMPQ1[72,8] = Rn_VPR128.16B[72,8] s>> Imm_shr_imm8:1;
TMPQ1[80,8] = Rn_VPR128.16B[80,8] s>> Imm_shr_imm8:1;
TMPQ1[88,8] = Rn_VPR128.16B[88,8] s>> Imm_shr_imm8:1;
TMPQ1[96,8] = Rn_VPR128.16B[96,8] s>> Imm_shr_imm8:1;
TMPQ1[104,8] = Rn_VPR128.16B[104,8] s>> Imm_shr_imm8:1;
TMPQ1[112,8] = Rn_VPR128.16B[112,8] s>> Imm_shr_imm8:1;
TMPQ1[120,8] = Rn_VPR128.16B[120,8] s>> Imm_shr_imm8:1;
# simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1
Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];
Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];
Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];
Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];
Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];
Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];
Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];
Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];
Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];
Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];
Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];
Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];
Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];
Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];
Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];
Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.318 SSRA page C7-2109 line 118340 MATCH x0f001400/mask=xbf80fc00
# CONSTRUCT x4f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 $s>>@8 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@8
# AUNIT --inst x4f401400/mask=xffc0fc00 --status pass
:ssra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x2 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
# simd infix TMPQ1 = Rn_VPR128.2D s>> tmp1 on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] s>> tmp1;
TMPQ1[64,64] = Rn_VPR128.2D[64,64] s>> tmp1;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.318 SSRA page C7-2109 line 118340 MATCH x0f001400/mask=xbf80fc00
# CONSTRUCT x0f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:4 $s>>@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@4
# AUNIT --inst x0f201400/mask=xffe0fc00 --status pass
:ssra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
local tmp1:4 = Imm_shr_imm32;
# simd infix TMPD1 = Rn_VPR64.2S s>> tmp1 on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] s>> tmp1;
TMPD1[32,32] = Rn_VPR64.2S[32,32] s>> tmp1;
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.318 SSRA page C7-2109 line 118340 MATCH x0f001400/mask=xbf80fc00
# CONSTRUCT x0f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@2
# AUNIT --inst x0f101400/mask=xfff0fc00 --status pass
:ssra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd infix TMPD1 = Rn_VPR64.4H s>> Imm_shr_imm16:2 on lane size 2
TMPD1[0,16] = Rn_VPR64.4H[0,16] s>> Imm_shr_imm16:2;
TMPD1[16,16] = Rn_VPR64.4H[16,16] s>> Imm_shr_imm16:2;
TMPD1[32,16] = Rn_VPR64.4H[32,16] s>> Imm_shr_imm16:2;
TMPD1[48,16] = Rn_VPR64.4H[48,16] s>> Imm_shr_imm16:2;
# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.318 SSRA page C7-2109 line 118340 MATCH x0f001400/mask=xbf80fc00
# CONSTRUCT x4f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:4 $s>>@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@4
# AUNIT --inst x4f201400/mask=xffe0fc00 --status pass
:ssra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
local tmp1:4 = Imm_shr_imm32;
# simd infix TMPQ1 = Rn_VPR128.4S s>> tmp1 on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] s>> tmp1;
TMPQ1[32,32] = Rn_VPR128.4S[32,32] s>> tmp1;
TMPQ1[64,32] = Rn_VPR128.4S[64,32] s>> tmp1;
TMPQ1[96,32] = Rn_VPR128.4S[96,32] s>> tmp1;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.318 SSRA page C7-2109 line 118340 MATCH x0f001400/mask=xbf80fc00
# CONSTRUCT x0f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@1
# AUNIT --inst x0f081400/mask=xfff8fc00 --status pass
:ssra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix TMPD1 = Rn_VPR64.8B s>> Imm_shr_imm8:1 on lane size 1
TMPD1[0,8] = Rn_VPR64.8B[0,8] s>> Imm_shr_imm8:1;
TMPD1[8,8] = Rn_VPR64.8B[8,8] s>> Imm_shr_imm8:1;
TMPD1[16,8] = Rn_VPR64.8B[16,8] s>> Imm_shr_imm8:1;
TMPD1[24,8] = Rn_VPR64.8B[24,8] s>> Imm_shr_imm8:1;
TMPD1[32,8] = Rn_VPR64.8B[32,8] s>> Imm_shr_imm8:1;
TMPD1[40,8] = Rn_VPR64.8B[40,8] s>> Imm_shr_imm8:1;
TMPD1[48,8] = Rn_VPR64.8B[48,8] s>> Imm_shr_imm8:1;
TMPD1[56,8] = Rn_VPR64.8B[56,8] s>> Imm_shr_imm8:1;
# simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1
Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];
Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];
Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];
Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];
Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];
Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];
Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];
Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.318 SSRA page C7-2109 line 118340 MATCH x0f001400/mask=xbf80fc00
# CONSTRUCT x4f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@2
# AUNIT --inst x4f101400/mask=xfff0fc00 --status pass
:ssra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H s>> Imm_shr_imm16:2 on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] s>> Imm_shr_imm16:2;
TMPQ1[16,16] = Rn_VPR128.8H[16,16] s>> Imm_shr_imm16:2;
TMPQ1[32,16] = Rn_VPR128.8H[32,16] s>> Imm_shr_imm16:2;
TMPQ1[48,16] = Rn_VPR128.8H[48,16] s>> Imm_shr_imm16:2;
TMPQ1[64,16] = Rn_VPR128.8H[64,16] s>> Imm_shr_imm16:2;
TMPQ1[80,16] = Rn_VPR128.8H[80,16] s>> Imm_shr_imm16:2;
TMPQ1[96,16] = Rn_VPR128.8H[96,16] s>> Imm_shr_imm16:2;
TMPQ1[112,16] = Rn_VPR128.8H[112,16] s>> Imm_shr_imm16:2;
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.318 SSRA page C7-2109 line 118340 MATCH x5f001400/mask=xff80fc00
# CONSTRUCT x5f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 s>> &=+
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3
# AUNIT --inst x5f401400/mask=xffc0fc00 --status pass
:ssra Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_2331=0b010111110 & b_22=1 & b_1015=0b000101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
local tmp2:8 = Rn_FPR64 s>> tmp1;
Rd_FPR64 = Rd_FPR64 + tmp2;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.319 SSUBL, SSUBL2 page C7-2112 line 118497 MATCH x0e202000/mask=xbf20fc00
# CONSTRUCT x4ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 =$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl2/2@4
# AUNIT --inst x4ea02000/mask=xffe0fc00 --status pass --comment "ext"
:ssubl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x2 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = sext(TMPD3[0,32]);
TMPQ4[64,64] = sext(TMPD3[32,32]);
# simd infix Rd_VPR128.2D = TMPQ2 - TMPQ4 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ2[0,64] - TMPQ4[0,64];
Rd_VPR128.2D[64,64] = TMPQ2[64,64] - TMPQ4[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.319 SSUBL, SSUBL2 page C7-2112 line 118497 MATCH x0e202000/mask=xbf20fc00
# CONSTRUCT x4e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 =$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl2/2@2
# AUNIT --inst x4e602000/mask=xffe0fc00 --status pass --comment "ext"
:ssubl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x2 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = sext(TMPD3[0,16]);
TMPQ4[32,32] = sext(TMPD3[16,16]);
TMPQ4[64,32] = sext(TMPD3[32,16]);
TMPQ4[96,32] = sext(TMPD3[48,16]);
# simd infix Rd_VPR128.4S = TMPQ2 - TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ2[0,32] - TMPQ4[0,32];
Rd_VPR128.4S[32,32] = TMPQ2[32,32] - TMPQ4[32,32];
Rd_VPR128.4S[64,32] = TMPQ2[64,32] - TMPQ4[64,32];
Rd_VPR128.4S[96,32] = TMPQ2[96,32] - TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.319 SSUBL, SSUBL2 page C7-2112 line 118497 MATCH x0e202000/mask=xbf20fc00
# CONSTRUCT x4e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 =$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl2/2@1
# AUNIT --inst x4e202000/mask=xffe0fc00 --status pass --comment "ext"
:ssubl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x2 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = sext(TMPD1[0,8]);
TMPQ2[16,16] = sext(TMPD1[8,8]);
TMPQ2[32,16] = sext(TMPD1[16,8]);
TMPQ2[48,16] = sext(TMPD1[24,8]);
TMPQ2[64,16] = sext(TMPD1[32,8]);
TMPQ2[80,16] = sext(TMPD1[40,8]);
TMPQ2[96,16] = sext(TMPD1[48,8]);
TMPQ2[112,16] = sext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = sext(TMPD3[0,8]);
TMPQ4[16,16] = sext(TMPD3[8,8]);
TMPQ4[32,16] = sext(TMPD3[16,8]);
TMPQ4[48,16] = sext(TMPD3[24,8]);
TMPQ4[64,16] = sext(TMPD3[32,8]);
TMPQ4[80,16] = sext(TMPD3[40,8]);
TMPQ4[96,16] = sext(TMPD3[48,8]);
TMPQ4[112,16] = sext(TMPD3[56,8]);
# simd infix Rd_VPR128.8H = TMPQ2 - TMPQ4 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ2[0,16] - TMPQ4[0,16];
Rd_VPR128.8H[16,16] = TMPQ2[16,16] - TMPQ4[16,16];
Rd_VPR128.8H[32,16] = TMPQ2[32,16] - TMPQ4[32,16];
Rd_VPR128.8H[48,16] = TMPQ2[48,16] - TMPQ4[48,16];
Rd_VPR128.8H[64,16] = TMPQ2[64,16] - TMPQ4[64,16];
Rd_VPR128.8H[80,16] = TMPQ2[80,16] - TMPQ4[80,16];
Rd_VPR128.8H[96,16] = TMPQ2[96,16] - TMPQ4[96,16];
Rd_VPR128.8H[112,16] = TMPQ2[112,16] - TMPQ4[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.319 SSUBL, SSUBL2 page C7-2112 line 118497 MATCH x0e202000/mask=xbf20fc00
# CONSTRUCT x0ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 =$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl/2@4
# AUNIT --inst x0ea02000/mask=xffe0fc00 --status pass --comment "ext"
:ssubl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x2 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
# simd infix Rd_VPR128.2D = TMPQ1 - TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64] - TMPQ2[0,64];
Rd_VPR128.2D[64,64] = TMPQ1[64,64] - TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.319 SSUBL, SSUBL2 page C7-2112 line 118497 MATCH x0e202000/mask=xbf20fc00
# CONSTRUCT x0e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 =$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl/2@2
# AUNIT --inst x0e602000/mask=xffe0fc00 --status pass --comment "ext"
:ssubl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x2 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
# simd infix Rd_VPR128.4S = TMPQ1 - TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32] - TMPQ2[0,32];
Rd_VPR128.4S[32,32] = TMPQ1[32,32] - TMPQ2[32,32];
Rd_VPR128.4S[64,32] = TMPQ1[64,32] - TMPQ2[64,32];
Rd_VPR128.4S[96,32] = TMPQ1[96,32] - TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.319 SSUBL, SSUBL2 page C7-2112 line 118497 MATCH x0e202000/mask=xbf20fc00
# CONSTRUCT x0e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 =$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl/2@1
# AUNIT --inst x0e202000/mask=xffe0fc00 --status pass --comment "ext"
:ssubl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x2 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
# simd infix Rd_VPR128.8H = TMPQ1 - TMPQ2 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[0,16] - TMPQ2[0,16];
Rd_VPR128.8H[16,16] = TMPQ1[16,16] - TMPQ2[16,16];
Rd_VPR128.8H[32,16] = TMPQ1[32,16] - TMPQ2[32,16];
Rd_VPR128.8H[48,16] = TMPQ1[48,16] - TMPQ2[48,16];
Rd_VPR128.8H[64,16] = TMPQ1[64,16] - TMPQ2[64,16];
Rd_VPR128.8H[80,16] = TMPQ1[80,16] - TMPQ2[80,16];
Rd_VPR128.8H[96,16] = TMPQ1[96,16] - TMPQ2[96,16];
Rd_VPR128.8H[112,16] = TMPQ1[112,16] - TMPQ2[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.320 SSUBW, SSUBW2 page C7-2114 line 118617 MATCH x0e203000/mask=xbf20fc00
# CONSTRUCT x4ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@4:16 =$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw2/2@4
# AUNIT --inst x4ea03000/mask=xffe0fc00 --status pass --comment "ext"
:ssubw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Rm_VPR128 & Zd
{
TMPD1 = Rm_VPR128.4S[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = sext(TMPD1[0,32]);
TMPQ2[64,64] = sext(TMPD1[32,32]);
# simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ2[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.320 SSUBW, SSUBW2 page C7-2114 line 118617 MATCH x0e203000/mask=xbf20fc00
# CONSTRUCT x4e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@2:16 =$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw2/2@2
# AUNIT --inst x4e603000/mask=xffe0fc00 --status pass --comment "ext"
:ssubw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
TMPD1 = Rm_VPR128.8H[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = sext(TMPD1[0,16]);
TMPQ2[32,32] = sext(TMPD1[16,16]);
TMPQ2[64,32] = sext(TMPD1[32,16]);
TMPQ2[96,32] = sext(TMPD1[48,16]);
# simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ2[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ2[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ2[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.320 SSUBW, SSUBW2 page C7-2114 line 118617 MATCH x0e203000/mask=xbf20fc00
# CONSTRUCT x4e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@1:16 =$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw2/2@1
# AUNIT --inst x4e203000/mask=xffe0fc00 --status pass --comment "ext"
:ssubw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
TMPD1 = Rm_VPR128.16B[64,64];
# simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = sext(TMPD1[0,8]);
TMPQ2[16,16] = sext(TMPD1[8,8]);
TMPQ2[32,16] = sext(TMPD1[16,8]);
TMPQ2[48,16] = sext(TMPD1[24,8]);
TMPQ2[64,16] = sext(TMPD1[32,8]);
TMPQ2[80,16] = sext(TMPD1[40,8]);
TMPQ2[96,16] = sext(TMPD1[48,8]);
TMPQ2[112,16] = sext(TMPD1[56,8]);
# simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ2 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ2[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ2[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ2[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ2[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ2[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ2[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ2[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ2[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.320 SSUBW, SSUBW2 page C7-2114 line 118617 MATCH x0e203000/mask=xbf20fc00
# CONSTRUCT x0ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $sext@4:16 =$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw/2@4
# AUNIT --inst x0ea03000/mask=xffe0fc00 --status pass --comment "ext"
:ssubw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = sext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = sext(Rm_VPR64.2S[0,32]);
TMPQ1[64,64] = sext(Rm_VPR64.2S[32,32]);
# simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.320 SSUBW, SSUBW2 page C7-2114 line 118617 MATCH x0e203000/mask=xbf20fc00
# CONSTRUCT x0e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $sext@2:16 =$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw/2@2
# AUNIT --inst x0e603000/mask=xffe0fc00 --status pass --comment "ext"
:ssubw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = sext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = sext(Rm_VPR64.4H[0,16]);
TMPQ1[32,32] = sext(Rm_VPR64.4H[16,16]);
TMPQ1[64,32] = sext(Rm_VPR64.4H[32,16]);
TMPQ1[96,32] = sext(Rm_VPR64.4H[48,16]);
# simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.320 SSUBW, SSUBW2 page C7-2114 line 118617 MATCH x0e203000/mask=xbf20fc00
# CONSTRUCT x0e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $sext@1:16 =$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw/2@1
# AUNIT --inst x0e203000/mask=xffe0fc00 --status pass --comment "ext"
:ssubw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = sext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = sext(Rm_VPR64.8B[0,8]);
TMPQ1[16,16] = sext(Rm_VPR64.8B[8,8]);
TMPQ1[32,16] = sext(Rm_VPR64.8B[16,8]);
TMPQ1[48,16] = sext(Rm_VPR64.8B[24,8]);
TMPQ1[64,16] = sext(Rm_VPR64.8B[32,8]);
TMPQ1[80,16] = sext(Rm_VPR64.8B[40,8]);
TMPQ1[96,16] = sext(Rm_VPR64.8B[48,8]);
TMPQ1[112,16] = sext(Rm_VPR64.8B[56,8]);
# simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.329 STNP (SIMD&FP) page C7-2145 line 120535 MATCH x2c000000/mask=x3fc00000
# CONSTRUCT x2c000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 4 +:8 =store pop
# SMACRO(pseudo) null ARG1 ARG3 =NEON_stnp1/2 null ARG2 ARG3 =NEON_stnp2/2
# AUNIT --inst x2c000000/mask=xffc00000 --status nomem
:stnp Rt_FPR32, Rt2_FPR32, addrPairIndexed
is b_3031=0b00 & b_2229=0b10110000 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32
{
* addrPairIndexed = Rt_FPR32;
local tmp1:8 = addrPairIndexed + 4;
* tmp1 = Rt2_FPR32;
}
# C7.2.329 STNP (SIMD&FP) page C7-2145 line 120535 MATCH x2c000000/mask=x3fc00000
# CONSTRUCT x6c000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 8 +:8 =store pop
# SMACRO(pseudo) null ARG1 ARG3 =NEON_stnp1/2 null ARG2 ARG3 =NEON_stnp2/2
# AUNIT --inst x6c000000/mask=xffc00000 --status nomem
:stnp Rt_FPR64, Rt2_FPR64, addrPairIndexed
is b_3031=0b01 & b_2229=0b10110000 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64
{
* addrPairIndexed = Rt_FPR64;
local tmp1:8 = addrPairIndexed + 8;
* tmp1 = Rt2_FPR64;
}
# C7.2.329 STNP (SIMD&FP) page C7-2145 line 120535 MATCH x2c000000/mask=x3fc00000
# CONSTRUCT xac000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 16 +:8 =store pop
# SMACRO(pseudo) null ARG1 ARG3 =NEON_stnp1/2 null ARG2 ARG3 =NEON_stnp2/2
# AUNIT --inst xac000000/mask=xffc00000 --status nomem
:stnp Rt_FPR128, Rt2_FPR128, addrPairIndexed
is b_3031=0b10 & b_2229=0b10110000 & Rt2_FPR64 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128
{
* addrPairIndexed = Rt_FPR128;
local tmp1:8 = addrPairIndexed + 16;
* tmp1 = Rt2_FPR128;
}
# C7.2.330 STP (SIMD&FP) page C7-2147 line 120656 MATCH x2c800000/mask=x3fc00000
# C7.2.330 STP (SIMD&FP) page C7-2147 line 120656 MATCH x2d800000/mask=x3fc00000
# C7.2.330 STP (SIMD&FP) page C7-2147 line 120656 MATCH x2d000000/mask=x3fc00000
# C7.2.329 STNP (SIMD&FP) page C7-2145 line 120535 MATCH x2c000000/mask=x3fc00000
# CONSTRUCT xac000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 16 +:8 =store pop
# SMACRO(pseudo) null ARG1 ARG3 =NEON_stp1/2 null ARG2 ARG3 =NEON_stp2/2
# AUNIT --inst xac000000/mask=xfe400000 --status nomem
# 128-bit variant (post-index, pre-index, and signed offset)
:stp Rt_FPR128, Rt2_FPR128, addrPairIndexed
is b_3031=0b10 & b_2529=0b10110 & b_22=0 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128
{
* addrPairIndexed = Rt_FPR128;
local tmp1:8 = addrPairIndexed + 16;
* tmp1 = Rt2_FPR128;
}
# C7.2.330 STP (SIMD&FP) page C7-2147 line 120656 MATCH x2c800000/mask=x3fc00000
# C7.2.330 STP (SIMD&FP) page C7-2147 line 120656 MATCH x2d800000/mask=x3fc00000
# C7.2.330 STP (SIMD&FP) page C7-2147 line 120656 MATCH x2d000000/mask=x3fc00000
# C7.2.329 STNP (SIMD&FP) page C7-2145 line 120535 MATCH x2c000000/mask=x3fc00000
# CONSTRUCT x2c000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 4 +:8 =store pop
# SMACRO(pseudo) null ARG1 ARG3 =NEON_stp1/2 null ARG2 ARG3 =NEON_stp2/2
# AUNIT --inst x2c000000/mask=xfe400000 --status nomem
# 32-bit variant (post-index, pre-index, and signed offset)
:stp Rt_FPR32, Rt2_FPR32, addrPairIndexed
is b_3031=0b00 & b_2529=0b10110 & b_22=0 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32
{
* addrPairIndexed = Rt_FPR32;
local tmp1:8 = addrPairIndexed + 4;
* tmp1 = Rt2_FPR32;
}
# C7.2.330 STP (SIMD&FP) page C7-2147 line 120656 MATCH x2c800000/mask=x3fc00000
# C7.2.330 STP (SIMD&FP) page C7-2147 line 120656 MATCH x2d800000/mask=x3fc00000
# C7.2.330 STP (SIMD&FP) page C7-2147 line 120656 MATCH x2d000000/mask=x3fc00000
# C7.2.329 STNP (SIMD&FP) page C7-2145 line 120535 MATCH x2c000000/mask=x3fc00000
# CONSTRUCT x6c000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 8 +:8 =store pop
# SMACRO(pseudo) null ARG1 ARG3 =NEON_stp1/2 null ARG2 ARG3 =NEON_stp2/2
# AUNIT --inst x6c000000/mask=xfe400000 --status nomem
# 64-bit variant (post-index, pre-index, and signed offset)
:stp Rt_FPR64, Rt2_FPR64, addrPairIndexed
is b_3031=0b01 & b_2529=0b10110 & b_22=0 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64
{
* addrPairIndexed = Rt_FPR64;
local tmp1:8 = addrPairIndexed + 8;
* tmp1 = Rt2_FPR64;
}
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3c000400/mask=x3f600c00
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3c000c00/mask=x3f600c00
# CONSTRUCT x3c000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
# AUNIT --inst x3c000400/mask=xffe00400 --status nomem
# Post- and Pre-offset 8-bit variant when size == 00 && opc == 00 F=FPR8
:str Rt_FPR8, addrIndexed
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR8 & addrIndexed & Zt
{
* addrIndexed = Rt_FPR8;
}
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3c000400/mask=x3f600c00
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3c000c00/mask=x3f600c00
# CONSTRUCT x7c000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
# AUNIT --inst x7c000400/mask=xffe00400 --status nomem
# Post- and Pre-offset 16-bit variant when size == 01 && opc == 00 F=FPR16
:str Rt_FPR16, addrIndexed
is b_3031=0b01 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR16 & addrIndexed & Zt
{
* addrIndexed = Rt_FPR16;
}
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3c000400/mask=x3f600c00
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3c000c00/mask=x3f600c00
# CONSTRUCT xbc000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
# AUNIT --inst xbc000400/mask=xffe00400 --status nomem
# Post- and Pre-offset 32-bit variant when size == 10 && opc == 00 F=FPR32
:str Rt_FPR32, addrIndexed
is b_3031=0b10 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR32 & addrIndexed & Zt
{
* addrIndexed = Rt_FPR32;
}
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3c000400/mask=x3f600c00
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3c000c00/mask=x3f600c00
# CONSTRUCT xfc000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
# AUNIT --inst xfc000400/mask=xffe00400 --status nomem
# Post- and Pre-offset 64-bit variant when size == 11 && opc == 00 F=FPR64
:str Rt_FPR64, addrIndexed
is b_3031=0b11 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR64 & addrIndexed & Zt
{
* addrIndexed = Rt_FPR64;
}
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3c000400/mask=x3f600c00
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3c000c00/mask=x3f600c00
# CONSTRUCT x3c800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
# AUNIT --inst x3c800400/mask=xffe00400 --status nomem
# Post- and Pre-offset 128-bit variant when size == 00 && opc == 10 F=FPR128
:str Rt_FPR128, addrIndexed
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b10 & b_21=0 & b_10=1 & Rt_FPR128 & addrIndexed & Zt
{
* addrIndexed = Rt_FPR128;
}
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3d000000/mask=x3f400000
# CONSTRUCT x3d000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
# AUNIT --inst x3d000000/mask=xffc00000 --status nomem
# Unsigned offset 8-bit variant when size == 00 && opc == 00 F=FPR8
:str Rt_FPR8, addrUIMM
is b_3031=0b00 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR8 & addrUIMM & Zt
{
* addrUIMM = Rt_FPR8;
}
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3d000000/mask=x3f400000
# CONSTRUCT x7d000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
# AUNIT --inst x7d000000/mask=xffc00000 --status nomem
# Unsigned offset 16-bit variant when size == 01 && opc == 00 F=FPR16
:str Rt_FPR16, addrUIMM
is b_3031=0b01 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR16 & addrUIMM & Zt
{
* addrUIMM = Rt_FPR16;
}
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3d000000/mask=x3f400000
# CONSTRUCT xbd000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
# AUNIT --inst xbd000000/mask=xffc00000 --status nomem
# Unsigned offset 32-bit variant when size == 10 && opc == 00 F=FPR32
:str Rt_FPR32, addrUIMM
is b_3031=0b10 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR32 & addrUIMM & Zt
{
* addrUIMM = Rt_FPR32;
}
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3d000000/mask=x3f400000
# CONSTRUCT xfd000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
# AUNIT --inst xfd000000/mask=xffc00000 --status nomem
# Unsigned offset 64-bit variant when size == 11 && opc == 00 F=FPR64
:str Rt_FPR64, addrUIMM
is b_3031=0b11 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR64 & addrUIMM & Zt
{
* addrUIMM = Rt_FPR64;
}
# C7.2.331 STR (immediate, SIMD&FP) page C7-2150 line 120865 MATCH x3d000000/mask=x3f400000
# CONSTRUCT x3d800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
# AUNIT --inst x3d800000/mask=xffc00000 --status nomem
# Unsigned offset 128-bit variant when size == 00 && opc == 10 F=FPR128
:str Rt_FPR128, addrUIMM
is b_3031=0b00 & b_2429=0b111101 & b_2223=0b10 & Rt_FPR128 & addrUIMM & Zt
{
* addrUIMM = Rt_FPR128;
}
# C7.2.332 STR (register, SIMD&FP) page C7-2154 line 121123 MATCH x3c200800/mask=x3f600c00
# CONSTRUCT x3c200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
# AUNIT --inst x3c200800/mask=xffe02c00 --status nomem
# 8-fsreg,STR-8-fsreg variant when size == 00 && opc == 00 && option is not 011 bb=b_13 option=0 F=FPR8 G=GPR32
:str Rt_FPR8, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
* tmp2 = Rt_FPR8;
}
# C7.2.332 STR (register, SIMD&FP) page C7-2154 line 121123 MATCH x3c200800/mask=x3f600c00
# CONSTRUCT x3c202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
# AUNIT --inst x3c202800/mask=xffe02c00 --status nomem
# 8-fsreg,STR-8-fsreg variant when size == 00 && opc == 00 && option is not 011 bb=b_13 option=1 F=FPR8 G=GPR64
:str Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
* tmp2 = Rt_FPR8;
}
# C7.2.332 STR (register, SIMD&FP) page C7-2154 line 121123 MATCH x3c200800/mask=x3f600c00
# CONSTRUCT x3c206800/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
# AUNIT --inst x3c206800/mask=xffe0ec00 --status nomem
# 8-fsreg,STR-8-fsreg variant when size == 00 && opc == 00 && option is 011 bb=b_1315 option=0b011 F=FPR8 G=GPR64
:str Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_1315=0b011 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
* tmp2 = Rt_FPR8;
}
# C7.2.332 STR (register, SIMD&FP) page C7-2154 line 121123 MATCH x3c200800/mask=x3f600c00
# CONSTRUCT x7c200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
# AUNIT --inst x7c200800/mask=xffe02c00 --status nomem
# 16-fsreg,STR-16-fsreg variant when size == 01 && opc == 00 bb=b_13 option=0 F=FPR16 G=GPR32
:str Rt_FPR16, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
is b_3031=0b01 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
* tmp2 = Rt_FPR16;
}
# C7.2.332 STR (register, SIMD&FP) page C7-2154 line 121123 MATCH x3c200800/mask=x3f600c00
# CONSTRUCT x7c202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
# AUNIT --inst x7c202800/mask=xffe02c00 --status nomem
# 16-fsreg,STR-16-fsreg variant when size == 01 && opc == 00 bb=b_13 option=1 F=FPR16 G=GPR64
:str Rt_FPR16, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
is b_3031=0b01 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
* tmp2 = Rt_FPR16;
}
# C7.2.332 STR (register, SIMD&FP) page C7-2154 line 121123 MATCH x3c200800/mask=x3f600c00
# CONSTRUCT xbc200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
# AUNIT --inst xbc200800/mask=xffe02c00 --status nomem
# 32-fsreg,STR-32-fsreg variant when size == 10 && opc == 00 bb=b_13 option=0 F=FPR32 G=GPR32
:str Rt_FPR32, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
is b_3031=0b10 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
* tmp2 = Rt_FPR32;
}
# C7.2.332 STR (register, SIMD&FP) page C7-2154 line 121123 MATCH x3c200800/mask=x3f600c00
# CONSTRUCT xbc202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
# AUNIT --inst xbc202800/mask=xffe02c00 --status nomem
# 32-fsreg,STR-32-fsreg variant when size == 10 && opc == 00 bb=b_13 option=1 F=FPR32 G=GPR64
:str Rt_FPR32, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
is b_3031=0b10 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
* tmp2 = Rt_FPR32;
}
# C7.2.332 STR (register, SIMD&FP) page C7-2154 line 121123 MATCH x3c200800/mask=x3f600c00
# CONSTRUCT xfc200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
# AUNIT --inst xfc200800/mask=xffe02c00 --status nomem
# 64-fsreg,STR-64-fsreg variant when size == 11 && opc == 00 bb=b_13 option=0 F=FPR64 G=GPR32
:str Rt_FPR64, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
is b_3031=0b11 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
* tmp2 = Rt_FPR64;
}
# C7.2.332 STR (register, SIMD&FP) page C7-2154 line 121123 MATCH x3c200800/mask=x3f600c00
# CONSTRUCT xfc202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
# AUNIT --inst xfc202800/mask=xffe02c00 --status nomem
# 64-fsreg,STR-64-fsreg variant when size == 11 && opc == 00 bb=b_13 option=1 F=FPR64 G=GPR64
:str Rt_FPR64, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
is b_3031=0b11 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
* tmp2 = Rt_FPR64;
}
# C7.2.332 STR (register, SIMD&FP) page C7-2154 line 121123 MATCH x3c200800/mask=x3f600c00
# CONSTRUCT x3ca00800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
# AUNIT --inst x3ca00800/mask=xffe02c00 --status nomem
# 128-fsreg,STR-128-fsreg variant when size == 00 && opc == 10 bb=b_13 option=0 F=FPR128 G=GPR32
:str Rt_FPR128, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b10 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
* tmp2 = Rt_FPR128;
}
# C7.2.332 STR (register, SIMD&FP) page C7-2154 line 121123 MATCH x3c200800/mask=x3f600c00
# CONSTRUCT x3ca02800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
# AUNIT --inst x3ca02800/mask=xffe02c00 --status nomem
# 128-fsreg,STR-128-fsreg variant when size == 00 && opc == 10 bb=b_13 option=1 F=FPR128 G=GPR64
:str Rt_FPR128, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
is b_3031=0b00 & b_2429=0b111100 & b_2223=0b10 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd
{
local tmp1:8 = extend_spec << extend_amount;
local tmp2:8 = Rn_GPR64xsp + tmp1;
* tmp2 = Rt_FPR128;
}
# C7.2.333 STUR (SIMD&FP) page C7-2157 line 121306 MATCH x3c000000/mask=x3f600c00
# CONSTRUCT x3c800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2
# AUNIT --inst x3c800000/mask=xffe00c00 --status nomem
:stur Rt_FPR128, addrIndexed
is size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=1 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR128
{
* addrIndexed = Rt_FPR128;
}
# C7.2.333 STUR (SIMD&FP) page C7-2157 line 121306 MATCH x3c000000/mask=x3f600c00
# CONSTRUCT x7c000000/mask=xffc00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2
# AUNIT --inst x7c000000/mask=xffc00c00 --status nomem
:stur Rt_FPR16, addrIndexed
is size.ldstr=1 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_1011=0 & addrIndexed & Rt_FPR16
{
* addrIndexed = Rt_FPR16;
}
# C7.2.333 STUR (SIMD&FP) page C7-2157 line 121306 MATCH x3c000000/mask=x3f600c00
# CONSTRUCT xbc000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2
# AUNIT --inst xbc000000/mask=xffe00c00 --status nomem
:stur Rt_FPR32, addrIndexed
is size.ldstr=2 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR32
{
* addrIndexed = Rt_FPR32;
}
# C7.2.333 STUR (SIMD&FP) page C7-2157 line 121306 MATCH x3c000000/mask=x3f600c00
# CONSTRUCT xfc000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2
# AUNIT --inst xfc000000/mask=xffe00c00 --status nomem
:stur Rt_FPR64, addrIndexed
is size.ldstr=3 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR64
{
* addrIndexed = Rt_FPR64;
}
# C7.2.333 STUR (SIMD&FP) page C7-2157 line 121306 MATCH x3c000000/mask=x3f600c00
# CONSTRUCT x3c000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =store pop
# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2
# AUNIT --inst x3c000000/mask=xffe00c00 --status nomem
:stur Rt_FPR8, addrIndexed
is size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR8
{
* addrIndexed = Rt_FPR8;
}
# C7.2.334 SUB (vector) page C7-2159 line 121431 MATCH x7e208400/mask=xff20fc00
# CONSTRUCT x7ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =-
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2
# AUNIT --inst x7ee08400/mask=xffe0fc00 --status pass
:sub Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x10 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = Rn_FPR64 - Rm_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.334 SUB (vector) page C7-2159 line 121431 MATCH x2e208400/mask=xbf20fc00
# CONSTRUCT x6e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$-@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@1
# AUNIT --inst x6e208400/mask=xffe0fc00 --status pass
:sub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x10 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix Rd_VPR128.16B = Rn_VPR128.16B - Rm_VPR128.16B on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] - Rm_VPR128.16B[0,8];
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] - Rm_VPR128.16B[8,8];
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] - Rm_VPR128.16B[16,8];
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] - Rm_VPR128.16B[24,8];
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] - Rm_VPR128.16B[32,8];
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] - Rm_VPR128.16B[40,8];
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] - Rm_VPR128.16B[48,8];
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] - Rm_VPR128.16B[56,8];
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] - Rm_VPR128.16B[64,8];
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] - Rm_VPR128.16B[72,8];
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] - Rm_VPR128.16B[80,8];
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] - Rm_VPR128.16B[88,8];
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] - Rm_VPR128.16B[96,8];
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] - Rm_VPR128.16B[104,8];
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] - Rm_VPR128.16B[112,8];
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] - Rm_VPR128.16B[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.334 SUB (vector) page C7-2159 line 121431 MATCH x2e208400/mask=xbf20fc00
# CONSTRUCT x6ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@8
# AUNIT --inst x6ee08400/mask=xffe0fc00 --status pass
:sub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd infix Rd_VPR128.2D = Rn_VPR128.2D - Rm_VPR128.2D on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - Rm_VPR128.2D[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - Rm_VPR128.2D[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.334 SUB (vector) page C7-2159 line 121431 MATCH x2e208400/mask=xbf20fc00
# CONSTRUCT x2ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@4
# AUNIT --inst x2ea08400/mask=xffe0fc00 --status pass
:sub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x10 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix Rd_VPR64.2S = Rn_VPR64.2S - Rm_VPR64.2S on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] - Rm_VPR64.2S[0,32];
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] - Rm_VPR64.2S[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.334 SUB (vector) page C7-2159 line 121431 MATCH x2e208400/mask=xbf20fc00
# CONSTRUCT x2e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@2
# AUNIT --inst x2e608400/mask=xffe0fc00 --status pass
:sub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x10 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd infix Rd_VPR64.4H = Rn_VPR64.4H - Rm_VPR64.4H on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] - Rm_VPR64.4H[0,16];
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] - Rm_VPR64.4H[16,16];
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] - Rm_VPR64.4H[32,16];
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] - Rm_VPR64.4H[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.334 SUB (vector) page C7-2159 line 121431 MATCH x2e208400/mask=xbf20fc00
# CONSTRUCT x6ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@4
# AUNIT --inst x6ea08400/mask=xffe0fc00 --status pass
:sub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd infix Rd_VPR128.4S = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.334 SUB (vector) page C7-2159 line 121431 MATCH x2e208400/mask=xbf20fc00
# CONSTRUCT x2e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$-@1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@1
# AUNIT --inst x2e208400/mask=xffe0fc00 --status pass
:sub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x10 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix Rd_VPR64.8B = Rn_VPR64.8B - Rm_VPR64.8B on lane size 1
Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] - Rm_VPR64.8B[0,8];
Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] - Rm_VPR64.8B[8,8];
Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] - Rm_VPR64.8B[16,8];
Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] - Rm_VPR64.8B[24,8];
Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] - Rm_VPR64.8B[32,8];
Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] - Rm_VPR64.8B[40,8];
Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] - Rm_VPR64.8B[48,8];
Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] - Rm_VPR64.8B[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.334 SUB (vector) page C7-2159 line 121431 MATCH x2e208400/mask=xbf20fc00
# CONSTRUCT x6e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@2
# AUNIT --inst x6e608400/mask=xffe0fc00 --status pass
:sub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd infix Rd_VPR128.8H = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.335 SUBHN, SUBHN2 page C7-2161 line 121565 MATCH x0e206000/mask=xbf20fc00
# CONSTRUCT x4e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $-@2 &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@2
# AUNIT --inst x4e206000/mask=xffe0fc00 --status pass
:subhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16];
TMPQ1[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16];
TMPQ1[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16];
TMPQ1[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16];
TMPQ1[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16];
TMPQ1[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16];
TMPQ1[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16];
TMPQ1[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16];
# simd shuffle Rd_VPR128.16B = TMPQ1 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1
Rd_VPR128.16B[64,8] = TMPQ1[8,8];
Rd_VPR128.16B[72,8] = TMPQ1[24,8];
Rd_VPR128.16B[80,8] = TMPQ1[40,8];
Rd_VPR128.16B[88,8] = TMPQ1[56,8];
Rd_VPR128.16B[96,8] = TMPQ1[72,8];
Rd_VPR128.16B[104,8] = TMPQ1[88,8];
Rd_VPR128.16B[112,8] = TMPQ1[104,8];
Rd_VPR128.16B[120,8] = TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.335 SUBHN, SUBHN2 page C7-2161 line 121565 MATCH x0e206000/mask=xbf20fc00
# CONSTRUCT x4ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $-@8 &=$shuffle@1-2@3-3:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@8
# AUNIT --inst x4ea06000/mask=xffe0fc00 --status pass
:subhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
# simd infix TMPQ1 = Rn_VPR128.2D - Rm_VPR128.2D on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] - Rm_VPR128.2D[0,64];
TMPQ1[64,64] = Rn_VPR128.2D[64,64] - Rm_VPR128.2D[64,64];
# simd shuffle Rd_VPR128.4S = TMPQ1 (@1-2@3-3) lane size 4
Rd_VPR128.4S[64,32] = TMPQ1[32,32];
Rd_VPR128.4S[96,32] = TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.335 SUBHN, SUBHN2 page C7-2161 line 121565 MATCH x0e206000/mask=xbf20fc00
# CONSTRUCT x4e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $-@4 &=$shuffle@1-4@3-5@5-6@7-7:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn2/3@4
# AUNIT --inst x4e606000/mask=xffe0fc00 --status pass
:subhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32];
TMPQ1[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32];
TMPQ1[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32];
TMPQ1[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32];
# simd shuffle Rd_VPR128.8H = TMPQ1 (@1-4@3-5@5-6@7-7) lane size 2
Rd_VPR128.8H[64,16] = TMPQ1[16,16];
Rd_VPR128.8H[80,16] = TMPQ1[48,16];
Rd_VPR128.8H[96,16] = TMPQ1[80,16];
Rd_VPR128.8H[112,16] = TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.335 SUBHN, SUBHN2 page C7-2161 line 121565 MATCH x0e206000/mask=xbf20fc00
# CONSTRUCT x0ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $-@8 &=$shuffle@1-0@3-1:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn/3@8
# AUNIT --inst x0ea06000/mask=xffe0fc00 --status pass
:subhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
# simd infix TMPQ1 = Rn_VPR128.2D - Rm_VPR128.2D on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] - Rm_VPR128.2D[0,64];
TMPQ1[64,64] = Rn_VPR128.2D[64,64] - Rm_VPR128.2D[64,64];
# simd shuffle Rd_VPR64.2S = TMPQ1 (@1-0@3-1) lane size 4
Rd_VPR64.2S[0,32] = TMPQ1[32,32];
Rd_VPR64.2S[32,32] = TMPQ1[96,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.335 SUBHN, SUBHN2 page C7-2161 line 121565 MATCH x0e206000/mask=xbf20fc00
# CONSTRUCT x0e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $-@4 &=$shuffle@1-0@3-1@5-2@7-3:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn/3@4
# AUNIT --inst x0e606000/mask=xffe0fc00 --status pass
:subhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32];
TMPQ1[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32];
TMPQ1[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32];
TMPQ1[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32];
# simd shuffle Rd_VPR64.4H = TMPQ1 (@1-0@3-1@5-2@7-3) lane size 2
Rd_VPR64.4H[0,16] = TMPQ1[16,16];
Rd_VPR64.4H[16,16] = TMPQ1[48,16];
Rd_VPR64.4H[32,16] = TMPQ1[80,16];
Rd_VPR64.4H[48,16] = TMPQ1[112,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.335 SUBHN, SUBHN2 page C7-2161 line 121565 MATCH x0e206000/mask=xbf20fc00
# CONSTRUCT x0e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $-@2 &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn/3@2
# AUNIT --inst x0e206000/mask=xffe0fc00 --status pass
:subhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16];
TMPQ1[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16];
TMPQ1[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16];
TMPQ1[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16];
TMPQ1[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16];
TMPQ1[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16];
TMPQ1[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16];
TMPQ1[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16];
# simd shuffle Rd_VPR64.8B = TMPQ1 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 1
Rd_VPR64.8B[0,8] = TMPQ1[8,8];
Rd_VPR64.8B[8,8] = TMPQ1[24,8];
Rd_VPR64.8B[16,8] = TMPQ1[40,8];
Rd_VPR64.8B[24,8] = TMPQ1[56,8];
Rd_VPR64.8B[32,8] = TMPQ1[72,8];
Rd_VPR64.8B[40,8] = TMPQ1[88,8];
Rd_VPR64.8B[48,8] = TMPQ1[104,8];
Rd_VPR64.8B[56,8] = TMPQ1[120,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.337 SUQADD page C7-2165 line 121781 MATCH x5e203800/mask=xff3ffc00
# CONSTRUCT x5e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=+
# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2
# AUNIT --inst x5e203800/mask=xfffffc00 --status fail --comment "nointsat"
# Scalar variant when size=00 Q=1 bb=1 V=FPR8 s2=2
:suqadd Rd_FPR8, Rn_FPR8
is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_FPR8 & Rn_FPR8 & Zd
{
Rd_FPR8 = Rd_FPR8 + Rn_FPR8;
zext_zb(Zd); # zero upper 31 bytes of Zd
}
# C7.2.337 SUQADD page C7-2165 line 121781 MATCH x5e203800/mask=xff3ffc00
# CONSTRUCT x5e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=+
# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2
# AUNIT --inst x5e603800/mask=xfffffc00 --status fail --comment "nointsat"
# Scalar variant when size=01 Q=1 bb=1 V=FPR16 s2=4
:suqadd Rd_FPR16, Rn_FPR16
is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = Rd_FPR16 + Rn_FPR16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.337 SUQADD page C7-2165 line 121781 MATCH x5e203800/mask=xff3ffc00
# CONSTRUCT x5ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=+
# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2
# AUNIT --inst x5ea03800/mask=xfffffc00 --status fail --comment "nointsat"
# Scalar variant when size=10 Q=1 bb=1 V=FPR32 s2=8
:suqadd Rd_FPR32, Rn_FPR32
is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = Rd_FPR32 + Rn_FPR32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.337 SUQADD page C7-2165 line 121781 MATCH x5e203800/mask=xff3ffc00
# CONSTRUCT x5ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=+
# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2
# AUNIT --inst x5ee03800/mask=xfffffc00 --status fail --comment "nointsat"
# Scalar variant when size=11 Q=1 bb=1 V=FPR64 s2=16
:suqadd Rd_FPR64, Rn_FPR64
is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = Rd_FPR64 + Rn_FPR64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.337 SUQADD page C7-2165 line 121781 MATCH x0e203800/mask=xbf3ffc00
# CONSTRUCT x0e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$+@1
# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@1
# AUNIT --inst x0e203800/mask=xfffffc00 --status fail --comment "nointsat"
# Vector variant when size=00 Q=0 bb=0 V=VPR64.8B e1=1 s2=16
:suqadd Rd_VPR64.8B, Rn_VPR64.8B
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
{
# simd infix Rd_VPR64.8B = Rd_VPR64.8B + Rn_VPR64.8B on lane size 1
Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + Rn_VPR64.8B[0,8];
Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + Rn_VPR64.8B[8,8];
Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + Rn_VPR64.8B[16,8];
Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + Rn_VPR64.8B[24,8];
Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + Rn_VPR64.8B[32,8];
Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + Rn_VPR64.8B[40,8];
Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + Rn_VPR64.8B[48,8];
Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + Rn_VPR64.8B[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.337 SUQADD page C7-2165 line 121781 MATCH x0e203800/mask=xbf3ffc00
# CONSTRUCT x4e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$+@1
# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@1
# AUNIT --inst x4e203800/mask=xfffffc00 --status fail --comment "nointsat"
# Vector variant when size=00 Q=1 bb=0 V=VPR128.16B e1=1 s2=32
:suqadd Rd_VPR128.16B, Rn_VPR128.16B
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
{
# simd infix Rd_VPR128.16B = Rd_VPR128.16B + Rn_VPR128.16B on lane size 1
Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + Rn_VPR128.16B[0,8];
Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + Rn_VPR128.16B[8,8];
Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + Rn_VPR128.16B[16,8];
Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + Rn_VPR128.16B[24,8];
Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + Rn_VPR128.16B[32,8];
Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + Rn_VPR128.16B[40,8];
Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + Rn_VPR128.16B[48,8];
Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + Rn_VPR128.16B[56,8];
Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + Rn_VPR128.16B[64,8];
Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + Rn_VPR128.16B[72,8];
Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + Rn_VPR128.16B[80,8];
Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + Rn_VPR128.16B[88,8];
Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + Rn_VPR128.16B[96,8];
Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + Rn_VPR128.16B[104,8];
Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + Rn_VPR128.16B[112,8];
Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + Rn_VPR128.16B[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.337 SUQADD page C7-2165 line 121781 MATCH x0e203800/mask=xbf3ffc00
# CONSTRUCT x0e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@2
# AUNIT --inst x0e603800/mask=xfffffc00 --status fail --comment "nointsat"
# Vector variant when size=01 Q=0 bb=0 V=VPR64.4H e1=2 s2=16
:suqadd Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
# simd infix Rd_VPR64.4H = Rd_VPR64.4H + Rn_VPR64.4H on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + Rn_VPR64.4H[0,16];
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + Rn_VPR64.4H[16,16];
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + Rn_VPR64.4H[32,16];
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + Rn_VPR64.4H[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.337 SUQADD page C7-2165 line 121781 MATCH x0e203800/mask=xbf3ffc00
# CONSTRUCT x4e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@2
# AUNIT --inst x4e603800/mask=xfffffc00 --status fail --comment "nointsat"
# Vector variant when size=01 Q=1 bb=0 V=VPR128.8H e1=2 s2=32
:suqadd Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + Rn_VPR128.8H on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + Rn_VPR128.8H[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + Rn_VPR128.8H[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + Rn_VPR128.8H[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + Rn_VPR128.8H[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + Rn_VPR128.8H[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + Rn_VPR128.8H[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + Rn_VPR128.8H[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + Rn_VPR128.8H[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.337 SUQADD page C7-2165 line 121781 MATCH x0e203800/mask=xbf3ffc00
# CONSTRUCT x0ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@4
# AUNIT --inst x0ea03800/mask=xfffffc00 --status fail --comment "nointsat"
# Vector variant when size=10 Q=0 bb=0 V=VPR64.2S e1=4 s2=16
:suqadd Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + Rn_VPR64.2S on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + Rn_VPR64.2S[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + Rn_VPR64.2S[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.337 SUQADD page C7-2165 line 121781 MATCH x0e203800/mask=xbf3ffc00
# CONSTRUCT x4ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@4
# AUNIT --inst x4ea03800/mask=xfffffc00 --status fail --comment "nointsat"
# Vector variant when size=10 Q=1 bb=0 V=VPR128.4S e1=4 s2=32
:suqadd Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + Rn_VPR128.4S on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + Rn_VPR128.4S[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + Rn_VPR128.4S[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + Rn_VPR128.4S[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + Rn_VPR128.4S[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.337 SUQADD page C7-2165 line 121781 MATCH x0e203800/mask=xbf3ffc00
# CONSTRUCT x4ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@8
# AUNIT --inst x4ee03800/mask=xfffffc00 --status fail --comment "nointsat"
# Vector variant when size=11 Q=1 bb=0 V=VPR128.2D e1=8 s2=32
:suqadd Rd_VPR128.2D, Rn_VPR128.2D
is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
{
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + Rn_VPR128.2D on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + Rn_VPR128.2D[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + Rn_VPR128.2D[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# CONSTRUCT x4f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 =$sext@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl2/1@1
# AUNIT --inst x4f08a400/mask=xfffffc00 --status pass --comment "ext"
:sxtl2 Rd_VPR128.8H, Rn_VPR128.16B
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize Rd_VPR128.8H = sext(TMPD1) (lane size 1 to 2)
Rd_VPR128.8H[0,16] = sext(TMPD1[0,8]);
Rd_VPR128.8H[16,16] = sext(TMPD1[8,8]);
Rd_VPR128.8H[32,16] = sext(TMPD1[16,8]);
Rd_VPR128.8H[48,16] = sext(TMPD1[24,8]);
Rd_VPR128.8H[64,16] = sext(TMPD1[32,8]);
Rd_VPR128.8H[80,16] = sext(TMPD1[40,8]);
Rd_VPR128.8H[96,16] = sext(TMPD1[48,8]);
Rd_VPR128.8H[112,16] = sext(TMPD1[56,8]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# CONSTRUCT x0f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =$sext@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl/1@4
# AUNIT --inst x0f20a400/mask=xfffffc00 --status pass --comment "ext"
:sxtl Rd_VPR128.2D, Rn_VPR64.2S
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR64.2S;
# simd resize Rd_VPR128.2D = sext(TMPD1) (lane size 4 to 8)
Rd_VPR128.2D[0,64] = sext(TMPD1[0,32]);
Rd_VPR128.2D[64,64] = sext(TMPD1[32,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# CONSTRUCT x0f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =$sext@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl/1@2
# AUNIT --inst x0f10a400/mask=xfffffc00 --status pass --comment "ext"
:sxtl Rd_VPR128.4S, Rn_VPR64.4H
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR64.4H;
# simd resize Rd_VPR128.4S = sext(TMPD1) (lane size 2 to 4)
Rd_VPR128.4S[0,32] = sext(TMPD1[0,16]);
Rd_VPR128.4S[32,32] = sext(TMPD1[16,16]);
Rd_VPR128.4S[64,32] = sext(TMPD1[32,16]);
Rd_VPR128.4S[96,32] = sext(TMPD1[48,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# CONSTRUCT x4f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 =$sext@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl2/1@4
# AUNIT --inst x4f20a400/mask=xfffffc00 --status pass --comment "ext"
:sxtl2 Rd_VPR128.2D, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize Rd_VPR128.2D = sext(TMPD1) (lane size 4 to 8)
Rd_VPR128.2D[0,64] = sext(TMPD1[0,32]);
Rd_VPR128.2D[64,64] = sext(TMPD1[32,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# CONSTRUCT x0f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =$sext@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl/1@1
# AUNIT --inst x0f08a400/mask=xfffffc00 --status pass --comment "ext"
:sxtl Rd_VPR128.8H, Rn_VPR64.8B
is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Rn_VPR128 & Zd
{
TMPD1 = Rn_VPR64.8B;
# simd resize Rd_VPR128.8H = sext(TMPD1) (lane size 1 to 2)
Rd_VPR128.8H[0,16] = sext(TMPD1[0,8]);
Rd_VPR128.8H[16,16] = sext(TMPD1[8,8]);
Rd_VPR128.8H[32,16] = sext(TMPD1[16,8]);
Rd_VPR128.8H[48,16] = sext(TMPD1[24,8]);
Rd_VPR128.8H[64,16] = sext(TMPD1[32,8]);
Rd_VPR128.8H[80,16] = sext(TMPD1[40,8]);
Rd_VPR128.8H[96,16] = sext(TMPD1[48,8]);
Rd_VPR128.8H[112,16] = sext(TMPD1[56,8]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.338 SXTL, SXTL2 page C7-2167 line 121903 MATCH x0f00a400/mask=xbf87fc00
# C7.2.316 SSHLL, SSHLL2 page C7-2104 line 118053 MATCH x0f00a400/mask=xbf80fc00
# CONSTRUCT x4f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 =$sext@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl2/1@2
# AUNIT --inst x4f10a400/mask=xfffffc00 --status pass --comment "ext"
:sxtl2 Rd_VPR128.4S, Rn_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize Rd_VPR128.4S = sext(TMPD1) (lane size 2 to 4)
Rd_VPR128.4S[0,32] = sext(TMPD1[0,16]);
Rd_VPR128.4S[32,32] = sext(TMPD1[16,16]);
Rd_VPR128.4S[64,32] = sext(TMPD1[32,16]);
Rd_VPR128.4S[96,32] = sext(TMPD1[48,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.322 TBL page C7-1717 line 99409 KEEPWITH
tblx: "tbl" is b_12=0 { local tmp:16 = zext(0:8); export tmp; }
tblx: "tbx" is b_12=1 & Rd_VPR128 { export Rd_VPR128; }
# C7.2.339 TBL page C7-2169 line 122002 MATCH x0e000000/mask=xbfe09c00
# C7.2.340 TBX page C7-2171 line 122128 MATCH x0e001000/mask=xbfe09c00
# CONSTRUCT x0e000000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 tblx Rn_VPR128.16B ARG3 =a64_TBL/3
# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B ARG3 =NEON_tblx/3@1
# AUNIT --inst x0e000000/mask=xffe0ec00 --status pass
# Q == 0 && len == 00 8B, Single register table variant
:^tblx Rd_VPR64.8B, "{"^Rn_VPR128.16B^"}", Rm_VPR64.8B
is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b00 & Rm_VPR64.8B & Rn_VPR128.16B & Rd_VPR64.8B & tblx & Zd
{
Rd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rm_VPR64.8B);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.339 TBL page C7-2169 line 122002 MATCH x0e000000/mask=xbfe09c00
# C7.2.340 TBX page C7-2171 line 122128 MATCH x0e001000/mask=xbfe09c00
# CONSTRUCT x4e000000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 tblx Rn_VPR128.16B ARG3 =a64_TBL/3
# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B ARG3 =NEON_tblx/3@1
# AUNIT --inst x4e000000/mask=xffe0ec00 --status pass
# Q == 1 && len == 00 16B, Single register table variant
:^tblx Rd_VPR128.16B, "{"^Rn_VPR128.16B^"}", Rm_VPR128.16B
is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b00 & Rm_VPR128.16B & Rn_VPR128.16B & Rd_VPR128.16B & tblx & Zd
{
Rd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rm_VPR128.16B);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.339 TBL page C7-2169 line 122002 MATCH x0e000000/mask=xbfe09c00
# C7.2.340 TBX page C7-2171 line 122128 MATCH x0e001000/mask=xbfe09c00
# CONSTRUCT x0e002000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =a64_TBL/4
# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =NEON_tblx/4
# AUNIT --inst x0e002000/mask=xffe0ec00 --status pass
# Q == 0 && len == 01 8B, Two register table variant
:^tblx Rd_VPR64.8B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^"}", Rm_VPR64.8B
is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b01 & Rm_VPR64.8B & Rn_VPR128.16B & Rnn_VPR128.16B & Rd_VPR64.8B & tblx & Zd
{
Rd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rm_VPR64.8B);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.339 TBL page C7-2169 line 122002 MATCH x0e000000/mask=xbfe09c00
# C7.2.340 TBX page C7-2171 line 122128 MATCH x0e001000/mask=xbfe09c00
# CONSTRUCT x4e002000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =a64_TBL/4
# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =NEON_tblx/4
# AUNIT --inst x4e002000/mask=xffe0ec00 --status pass
# Q == 1 && len == 01 16B, Two register table variant
:^tblx Rd_VPR128.16B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^"}", Rm_VPR128.16B
is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b01 & Rm_VPR128.16B & Rn_VPR128.16B & Rnn_VPR128.16B & Rd_VPR128.16B & tblx & Zd
{
Rd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rm_VPR128.16B);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.339 TBL page C7-2169 line 122002 MATCH x0e000000/mask=xbfe09c00
# C7.2.340 TBX page C7-2171 line 122128 MATCH x0e001000/mask=xbfe09c00
# CONSTRUCT x0e004000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =a64_TBL/5
# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =NEON_tblx/5
# AUNIT --inst x0e004000/mask=xffe0ec00 --status pass
# Q == 0 && len == 10 8B, Three register table variant
:^tblx Rd_VPR64.8B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^", "^Rnnn_VPR128.16B^"}", Rm_VPR64.8B
is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b10 & Rm_VPR64.8B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rd_VPR64.8B & tblx & Zd
{
Rd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rm_VPR64.8B);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.339 TBL page C7-2169 line 122002 MATCH x0e000000/mask=xbfe09c00
# C7.2.340 TBX page C7-2171 line 122128 MATCH x0e001000/mask=xbfe09c00
# CONSTRUCT x4e004000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =a64_TBL/5
# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =NEON_tblx/5
# AUNIT --inst x4e004000/mask=xffe0ec00 --status pass
# Q == 1 && len == 10 16B, Three register table variant
:^tblx Rd_VPR128.16B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^", "^Rnnn_VPR128.16B^"}", Rm_VPR128.16B
is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b10 & Rm_VPR128.16B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rd_VPR128.16B & tblx & Zd
{
Rd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rm_VPR128.16B);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.339 TBL page C7-2169 line 122002 MATCH x0e000000/mask=xbfe09c00
# C7.2.340 TBX page C7-2171 line 122128 MATCH x0e001000/mask=xbfe09c00
# CONSTRUCT x0e006000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =a64_TBL/6
# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =NEON_tblx/6
# AUNIT --inst x0e006000/mask=xffe0ec00 --status pass
# Q == 0 && len == 11 8B, Four register table variant
:^tblx Rd_VPR64.8B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^", "^Rnnn_VPR128.16B^", "^Rnnnn_VPR128.16B^"}", Rm_VPR64.8B
is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b11 & Rm_VPR64.8B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rnnnn_VPR128.16B & Rd_VPR64.8B & tblx & Zd
{
Rd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rnnnn_VPR128.16B, Rm_VPR64.8B);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.339 TBL page C7-2169 line 122002 MATCH x0e000000/mask=xbfe09c00
# C7.2.340 TBX page C7-2171 line 122128 MATCH x0e001000/mask=xbfe09c00
# CONSTRUCT x4e006000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =a64_TBL/6
# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =NEON_tblx/6
# AUNIT --inst x4e006000/mask=xffe0ec00 --status pass
# Q == 1 && len == 11 16B, Four register table variant
:^tblx Rd_VPR128.16B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^", "^Rnnn_VPR128.16B^", "^Rnnnn_VPR128.16B^"}", Rm_VPR128.16B
is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b11 & Rm_VPR128.16B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rnnnn_VPR128.16B & Rd_VPR128.16B & tblx & Zd
{
Rd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rnnnn_VPR128.16B, Rm_VPR128.16B);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.341 TRN1 page C7-2173 line 122256 MATCH x0e002800/mask=xbf20fc00
# CONSTRUCT x4e002800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2@4-4@6-6@8-8@10-10@12-12@14-14:1 swap &=$shuffle@0-1@2-3@4-5@6-7@8-9@10-11@12-13@14-15:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@1
# AUNIT --inst x4e002800/mask=xffe0fc00 --status pass
:trn1 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
TMPQ2 = Rm_VPR128.16B;
TMPQ1 = Rn_VPR128.16B;
# simd shuffle Rd_VPR128.16B = TMPQ1 (@0-0@2-2@4-4@6-6@8-8@10-10@12-12@14-14) lane size 1
Rd_VPR128.16B[0,8] = TMPQ1[0,8];
Rd_VPR128.16B[16,8] = TMPQ1[16,8];
Rd_VPR128.16B[32,8] = TMPQ1[32,8];
Rd_VPR128.16B[48,8] = TMPQ1[48,8];
Rd_VPR128.16B[64,8] = TMPQ1[64,8];
Rd_VPR128.16B[80,8] = TMPQ1[80,8];
Rd_VPR128.16B[96,8] = TMPQ1[96,8];
Rd_VPR128.16B[112,8] = TMPQ1[112,8];
# simd shuffle Rd_VPR128.16B = TMPQ2 (@0-1@2-3@4-5@6-7@8-9@10-11@12-13@14-15) lane size 1
Rd_VPR128.16B[8,8] = TMPQ2[0,8];
Rd_VPR128.16B[24,8] = TMPQ2[16,8];
Rd_VPR128.16B[40,8] = TMPQ2[32,8];
Rd_VPR128.16B[56,8] = TMPQ2[48,8];
Rd_VPR128.16B[72,8] = TMPQ2[64,8];
Rd_VPR128.16B[88,8] = TMPQ2[80,8];
Rd_VPR128.16B[104,8] = TMPQ2[96,8];
Rd_VPR128.16B[120,8] = TMPQ2[112,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.341 TRN1 page C7-2173 line 122256 MATCH x0e002800/mask=xbf20fc00
# CONSTRUCT x4ec02800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:8 swap &=$shuffle@0-1:8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@8
# AUNIT --inst x4ec02800/mask=xffe0fc00 --status pass
:trn1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
TMPQ2 = Rm_VPR128.2D;
TMPQ1 = Rn_VPR128.2D;
# simd shuffle Rd_VPR128.2D = TMPQ1 (@0-0) lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64];
# simd shuffle Rd_VPR128.2D = TMPQ2 (@0-1) lane size 8
Rd_VPR128.2D[64,64] = TMPQ2[0,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.341 TRN1 page C7-2173 line 122256 MATCH x0e002800/mask=xbf20fc00
# CONSTRUCT x0e802800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:4 swap &=$shuffle@0-1:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@4
# AUNIT --inst x0e802800/mask=xffe0fc00 --status pass
:trn1 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
TMPD2 = Rm_VPR64.2S;
TMPD1 = Rn_VPR64.2S;
# simd shuffle Rd_VPR64.2S = TMPD1 (@0-0) lane size 4
Rd_VPR64.2S[0,32] = TMPD1[0,32];
# simd shuffle Rd_VPR64.2S = TMPD2 (@0-1) lane size 4
Rd_VPR64.2S[32,32] = TMPD2[0,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.341 TRN1 page C7-2173 line 122256 MATCH x0e002800/mask=xbf20fc00
# CONSTRUCT x0e402800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2:2 swap &=$shuffle@0-1@2-3:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@2
# AUNIT --inst x0e402800/mask=xffe0fc00 --status pass
:trn1 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
TMPD2 = Rm_VPR64.4H;
TMPD1 = Rn_VPR64.4H;
# simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@2-2) lane size 2
Rd_VPR64.4H[0,16] = TMPD1[0,16];
Rd_VPR64.4H[32,16] = TMPD1[32,16];
# simd shuffle Rd_VPR64.4H = TMPD2 (@0-1@2-3) lane size 2
Rd_VPR64.4H[16,16] = TMPD2[0,16];
Rd_VPR64.4H[48,16] = TMPD2[32,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.341 TRN1 page C7-2173 line 122256 MATCH x0e002800/mask=xbf20fc00
# CONSTRUCT x4e802800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2:4 swap &=$shuffle@0-1@2-3:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@4
# AUNIT --inst x4e802800/mask=xffe0fc00 --status pass
:trn1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
TMPQ2 = Rm_VPR128.4S;
TMPQ1 = Rn_VPR128.4S;
# simd shuffle Rd_VPR128.4S = TMPQ1 (@0-0@2-2) lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32];
Rd_VPR128.4S[64,32] = TMPQ1[64,32];
# simd shuffle Rd_VPR128.4S = TMPQ2 (@0-1@2-3) lane size 4
Rd_VPR128.4S[32,32] = TMPQ2[0,32];
Rd_VPR128.4S[96,32] = TMPQ2[64,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.341 TRN1 page C7-2173 line 122256 MATCH x0e002800/mask=xbf20fc00
# CONSTRUCT x0e002800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2@4-4@6-6:1 swap &=$shuffle@0-1@2-3@4-5@6-7:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@1
# AUNIT --inst x0e002800/mask=xffe0fc00 --status pass
:trn1 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
TMPD2 = Rm_VPR64.8B;
TMPD1 = Rn_VPR64.8B;
# simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@2-2@4-4@6-6) lane size 1
Rd_VPR64.8B[0,8] = TMPD1[0,8];
Rd_VPR64.8B[16,8] = TMPD1[16,8];
Rd_VPR64.8B[32,8] = TMPD1[32,8];
Rd_VPR64.8B[48,8] = TMPD1[48,8];
# simd shuffle Rd_VPR64.8B = TMPD2 (@0-1@2-3@4-5@6-7) lane size 1
Rd_VPR64.8B[8,8] = TMPD2[0,8];
Rd_VPR64.8B[24,8] = TMPD2[16,8];
Rd_VPR64.8B[40,8] = TMPD2[32,8];
Rd_VPR64.8B[56,8] = TMPD2[48,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.341 TRN1 page C7-2173 line 122256 MATCH x0e002800/mask=xbf20fc00
# CONSTRUCT x4e402800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2@4-4@6-6:2 swap &=$shuffle@0-1@2-3@4-5@6-7:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@2
# AUNIT --inst x4e402800/mask=xffe0fc00 --status pass
:trn1 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
TMPQ2 = Rm_VPR128.8H;
TMPQ1 = Rn_VPR128.8H;
# simd shuffle Rd_VPR128.8H = TMPQ1 (@0-0@2-2@4-4@6-6) lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[0,16];
Rd_VPR128.8H[32,16] = TMPQ1[32,16];
Rd_VPR128.8H[64,16] = TMPQ1[64,16];
Rd_VPR128.8H[96,16] = TMPQ1[96,16];
# simd shuffle Rd_VPR128.8H = TMPQ2 (@0-1@2-3@4-5@6-7) lane size 2
Rd_VPR128.8H[16,16] = TMPQ2[0,16];
Rd_VPR128.8H[48,16] = TMPQ2[32,16];
Rd_VPR128.8H[80,16] = TMPQ2[64,16];
Rd_VPR128.8H[112,16] = TMPQ2[96,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.342 TRN2 page C7-2175 line 122373 MATCH x0e006800/mask=xbf20fc00
# CONSTRUCT x4e006800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2@5-4@7-6@9-8@11-10@13-12@15-14:1 swap &=$shuffle@1-1@3-3@5-5@7-7@9-9@11-11@13-13@15-15:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@1
# AUNIT --inst x4e006800/mask=xffe0fc00 --status pass
:trn2 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
TMPQ2 = Rm_VPR128.16B;
TMPQ1 = Rn_VPR128.16B;
# simd shuffle Rd_VPR128.16B = TMPQ1 (@1-0@3-2@5-4@7-6@9-8@11-10@13-12@15-14) lane size 1
Rd_VPR128.16B[0,8] = TMPQ1[8,8];
Rd_VPR128.16B[16,8] = TMPQ1[24,8];
Rd_VPR128.16B[32,8] = TMPQ1[40,8];
Rd_VPR128.16B[48,8] = TMPQ1[56,8];
Rd_VPR128.16B[64,8] = TMPQ1[72,8];
Rd_VPR128.16B[80,8] = TMPQ1[88,8];
Rd_VPR128.16B[96,8] = TMPQ1[104,8];
Rd_VPR128.16B[112,8] = TMPQ1[120,8];
# simd shuffle Rd_VPR128.16B = TMPQ2 (@1-1@3-3@5-5@7-7@9-9@11-11@13-13@15-15) lane size 1
Rd_VPR128.16B[8,8] = TMPQ2[8,8];
Rd_VPR128.16B[24,8] = TMPQ2[24,8];
Rd_VPR128.16B[40,8] = TMPQ2[40,8];
Rd_VPR128.16B[56,8] = TMPQ2[56,8];
Rd_VPR128.16B[72,8] = TMPQ2[72,8];
Rd_VPR128.16B[88,8] = TMPQ2[88,8];
Rd_VPR128.16B[104,8] = TMPQ2[104,8];
Rd_VPR128.16B[120,8] = TMPQ2[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.342 TRN2 page C7-2175 line 122373 MATCH x0e006800/mask=xbf20fc00
# CONSTRUCT x4ec06800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:8 swap &=$shuffle@1-1:8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@8
# AUNIT --inst x4ec06800/mask=xffe0fc00 --status pass
:trn2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
TMPQ2 = Rm_VPR128.2D;
TMPQ1 = Rn_VPR128.2D;
# simd shuffle Rd_VPR128.2D = TMPQ1 (@1-0) lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[64,64];
# simd shuffle Rd_VPR128.2D = TMPQ2 (@1-1) lane size 8
Rd_VPR128.2D[64,64] = TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.342 TRN2 page C7-2175 line 122373 MATCH x0e006800/mask=xbf20fc00
# CONSTRUCT x0e806800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:4 swap &=$shuffle@1-1:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@4
# AUNIT --inst x0e806800/mask=xffe0fc00 --status pass
:trn2 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
TMPD2 = Rm_VPR64.2S;
TMPD1 = Rn_VPR64.2S;
# simd shuffle Rd_VPR64.2S = TMPD1 (@1-0) lane size 4
Rd_VPR64.2S[0,32] = TMPD1[32,32];
# simd shuffle Rd_VPR64.2S = TMPD2 (@1-1) lane size 4
Rd_VPR64.2S[32,32] = TMPD2[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.342 TRN2 page C7-2175 line 122373 MATCH x0e006800/mask=xbf20fc00
# CONSTRUCT x0e406800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2:2 swap &=$shuffle@1-1@3-3:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@2
# AUNIT --inst x0e406800/mask=xffe0fc00 --status pass
:trn2 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
TMPD2 = Rm_VPR64.4H;
TMPD1 = Rn_VPR64.4H;
# simd shuffle Rd_VPR64.4H = TMPD1 (@1-0@3-2) lane size 2
Rd_VPR64.4H[0,16] = TMPD1[16,16];
Rd_VPR64.4H[32,16] = TMPD1[48,16];
# simd shuffle Rd_VPR64.4H = TMPD2 (@1-1@3-3) lane size 2
Rd_VPR64.4H[16,16] = TMPD2[16,16];
Rd_VPR64.4H[48,16] = TMPD2[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.342 TRN2 page C7-2175 line 122373 MATCH x0e006800/mask=xbf20fc00
# CONSTRUCT x4e806800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2:4 swap &=$shuffle@1-1@3-3:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@4
# AUNIT --inst x4e806800/mask=xffe0fc00 --status pass
:trn2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
TMPQ2 = Rm_VPR128.4S;
TMPQ1 = Rn_VPR128.4S;
# simd shuffle Rd_VPR128.4S = TMPQ1 (@1-0@3-2) lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[32,32];
Rd_VPR128.4S[64,32] = TMPQ1[96,32];
# simd shuffle Rd_VPR128.4S = TMPQ2 (@1-1@3-3) lane size 4
Rd_VPR128.4S[32,32] = TMPQ2[32,32];
Rd_VPR128.4S[96,32] = TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.342 TRN2 page C7-2175 line 122373 MATCH x0e006800/mask=xbf20fc00
# CONSTRUCT x0e006800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2@5-4@7-6:1 swap &=$shuffle@1-1@3-3@5-5@7-7:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@1
# AUNIT --inst x0e006800/mask=xffe0fc00 --status pass
:trn2 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
TMPD2 = Rm_VPR64.8B;
TMPD1 = Rn_VPR64.8B;
# simd shuffle Rd_VPR64.8B = TMPD1 (@1-0@3-2@5-4@7-6) lane size 1
Rd_VPR64.8B[0,8] = TMPD1[8,8];
Rd_VPR64.8B[16,8] = TMPD1[24,8];
Rd_VPR64.8B[32,8] = TMPD1[40,8];
Rd_VPR64.8B[48,8] = TMPD1[56,8];
# simd shuffle Rd_VPR64.8B = TMPD2 (@1-1@3-3@5-5@7-7) lane size 1
Rd_VPR64.8B[8,8] = TMPD2[8,8];
Rd_VPR64.8B[24,8] = TMPD2[24,8];
Rd_VPR64.8B[40,8] = TMPD2[40,8];
Rd_VPR64.8B[56,8] = TMPD2[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.342 TRN2 page C7-2175 line 122373 MATCH x0e006800/mask=xbf20fc00
# CONSTRUCT x4e406800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2@5-4@7-6:2 swap &=$shuffle@1-1@3-3@5-5@7-7:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@2
# AUNIT --inst x4e406800/mask=xffe0fc00 --status pass
:trn2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
TMPQ2 = Rm_VPR128.8H;
TMPQ1 = Rn_VPR128.8H;
# simd shuffle Rd_VPR128.8H = TMPQ1 (@1-0@3-2@5-4@7-6) lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[16,16];
Rd_VPR128.8H[32,16] = TMPQ1[48,16];
Rd_VPR128.8H[64,16] = TMPQ1[80,16];
Rd_VPR128.8H[96,16] = TMPQ1[112,16];
# simd shuffle Rd_VPR128.8H = TMPQ2 (@1-1@3-3@5-5@7-7) lane size 2
Rd_VPR128.8H[16,16] = TMPQ2[16,16];
Rd_VPR128.8H[48,16] = TMPQ2[48,16];
Rd_VPR128.8H[80,16] = TMPQ2[80,16];
Rd_VPR128.8H[112,16] = TMPQ2[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.343 UABA page C7-2177 line 122490 MATCH x2e207c00/mask=xbf20fc00
# CONSTRUCT x6e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@1
# AUNIT --inst x6e207c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
:uaba Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xf & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_uaba(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.343 UABA page C7-2177 line 122490 MATCH x2e207c00/mask=xbf20fc00
# CONSTRUCT x2ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@4
# AUNIT --inst x2ea07c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
:uaba Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xf & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_uaba(Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.343 UABA page C7-2177 line 122490 MATCH x2e207c00/mask=xbf20fc00
# CONSTRUCT x2e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@2
# AUNIT --inst x2e607c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
:uaba Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xf & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_uaba(Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.343 UABA page C7-2177 line 122490 MATCH x2e207c00/mask=xbf20fc00
# CONSTRUCT x6ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@4
# AUNIT --inst x6ea07c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
:uaba Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xf & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_uaba(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.343 UABA page C7-2177 line 122490 MATCH x2e207c00/mask=xbf20fc00
# CONSTRUCT x2e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@1
# AUNIT --inst x2e207c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
:uaba Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xf & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_uaba(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.343 UABA page C7-2177 line 122490 MATCH x2e207c00/mask=xbf20fc00
# CONSTRUCT x6e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@2
# AUNIT --inst x6e607c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
:uaba Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xf & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_uaba(Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.344 UABAL, UABAL2 page C7-2179 line 122590 MATCH x2e205000/mask=xbf20fc00
# CONSTRUCT x6ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $-@8 $abs@8 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal2/3@4
# AUNIT --inst x6ea05000/mask=xffe0fc00 --status pass --comment "ext abd"
:uabal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x5 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = zext(TMPD3[0,32]);
TMPQ4[64,64] = zext(TMPD3[32,32]);
# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8
TMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64];
TMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64];
# simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 8
TMPQ6[0,64] = MP_INT_ABS(TMPQ5[0,64]);
TMPQ6[64,64] = MP_INT_ABS(TMPQ5[64,64]);
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ6 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ6[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ6[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.344 UABAL, UABAL2 page C7-2179 line 122590 MATCH x2e205000/mask=xbf20fc00
# CONSTRUCT x6e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $-@4 $abs@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal2/3@2
# AUNIT --inst x6e605000/mask=xffe0fc00 --status pass --comment "ext abd"
:uabal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x5 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = zext(TMPD3[0,16]);
TMPQ4[32,32] = zext(TMPD3[16,16]);
TMPQ4[64,32] = zext(TMPD3[32,16]);
TMPQ4[96,32] = zext(TMPD3[48,16]);
# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4
TMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32];
TMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32];
TMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32];
TMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32];
# simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 4
TMPQ6[0,32] = MP_INT_ABS(TMPQ5[0,32]);
TMPQ6[32,32] = MP_INT_ABS(TMPQ5[32,32]);
TMPQ6[64,32] = MP_INT_ABS(TMPQ5[64,32]);
TMPQ6[96,32] = MP_INT_ABS(TMPQ5[96,32]);
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ6 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ6[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ6[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ6[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ6[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.344 UABAL, UABAL2 page C7-2179 line 122590 MATCH x2e205000/mask=xbf20fc00
# CONSTRUCT x6e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $-@2 $abs@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal2/3@1
# AUNIT --inst x6e205000/mask=xffe0fc00 --status pass --comment "ext abd"
:uabal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x5 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = zext(TMPD1[0,8]);
TMPQ2[16,16] = zext(TMPD1[8,8]);
TMPQ2[32,16] = zext(TMPD1[16,8]);
TMPQ2[48,16] = zext(TMPD1[24,8]);
TMPQ2[64,16] = zext(TMPD1[32,8]);
TMPQ2[80,16] = zext(TMPD1[40,8]);
TMPQ2[96,16] = zext(TMPD1[48,8]);
TMPQ2[112,16] = zext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = zext(TMPD3[0,8]);
TMPQ4[16,16] = zext(TMPD3[8,8]);
TMPQ4[32,16] = zext(TMPD3[16,8]);
TMPQ4[48,16] = zext(TMPD3[24,8]);
TMPQ4[64,16] = zext(TMPD3[32,8]);
TMPQ4[80,16] = zext(TMPD3[40,8]);
TMPQ4[96,16] = zext(TMPD3[48,8]);
TMPQ4[112,16] = zext(TMPD3[56,8]);
# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2
TMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16];
TMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16];
TMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16];
TMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16];
TMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16];
TMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16];
TMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16];
TMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16];
# simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 2
TMPQ6[0,16] = MP_INT_ABS(TMPQ5[0,16]);
TMPQ6[16,16] = MP_INT_ABS(TMPQ5[16,16]);
TMPQ6[32,16] = MP_INT_ABS(TMPQ5[32,16]);
TMPQ6[48,16] = MP_INT_ABS(TMPQ5[48,16]);
TMPQ6[64,16] = MP_INT_ABS(TMPQ5[64,16]);
TMPQ6[80,16] = MP_INT_ABS(TMPQ5[80,16]);
TMPQ6[96,16] = MP_INT_ABS(TMPQ5[96,16]);
TMPQ6[112,16] = MP_INT_ABS(TMPQ5[112,16]);
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ6 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ6[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ6[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ6[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ6[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ6[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ6[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ6[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ6[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.344 UABAL, UABAL2 page C7-2179 line 122590 MATCH x2e205000/mask=xbf20fc00
# CONSTRUCT x2ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $-@8 $abs@8 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal/3@4
# AUNIT --inst x2ea05000/mask=xffe0fc00 --status pass --comment "ext abd"
:uabal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x5 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);
# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8
TMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64];
TMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64];
# simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 8
TMPQ4[0,64] = MP_INT_ABS(TMPQ3[0,64]);
TMPQ4[64,64] = MP_INT_ABS(TMPQ3[64,64]);
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.344 UABAL, UABAL2 page C7-2179 line 122590 MATCH x2e205000/mask=xbf20fc00
# CONSTRUCT x2e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $-@4 $abs@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal/3@2
# AUNIT --inst x2e605000/mask=xffe0fc00 --status pass --comment "ext abd"
:uabal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x5 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);
# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4
TMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32];
TMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32];
TMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32];
TMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32];
# simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 4
TMPQ4[0,32] = MP_INT_ABS(TMPQ3[0,32]);
TMPQ4[32,32] = MP_INT_ABS(TMPQ3[32,32]);
TMPQ4[64,32] = MP_INT_ABS(TMPQ3[64,32]);
TMPQ4[96,32] = MP_INT_ABS(TMPQ3[96,32]);
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.344 UABAL, UABAL2 page C7-2179 line 122590 MATCH x2e205000/mask=xbf20fc00
# CONSTRUCT x2e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $-@2 $abs@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal/3@1
# AUNIT --inst x2e205000/mask=xffe0fc00 --status pass --comment "ext abd"
:uabal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x5 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);
# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2
TMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16];
TMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16];
TMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16];
TMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16];
TMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16];
TMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16];
TMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16];
TMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16];
# simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 2
TMPQ4[0,16] = MP_INT_ABS(TMPQ3[0,16]);
TMPQ4[16,16] = MP_INT_ABS(TMPQ3[16,16]);
TMPQ4[32,16] = MP_INT_ABS(TMPQ3[32,16]);
TMPQ4[48,16] = MP_INT_ABS(TMPQ3[48,16]);
TMPQ4[64,16] = MP_INT_ABS(TMPQ3[64,16]);
TMPQ4[80,16] = MP_INT_ABS(TMPQ3[80,16]);
TMPQ4[96,16] = MP_INT_ABS(TMPQ3[96,16]);
TMPQ4[112,16] = MP_INT_ABS(TMPQ3[112,16]);
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ4 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ4[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ4[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ4[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ4[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ4[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ4[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ4[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ4[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.345 UABD page C7-2181 line 122708 MATCH x2e207400/mask=xbf20fc00
# CONSTRUCT x6e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@1
# AUNIT --inst x6e207400/mask=xffe0fc00 --status nopcodeop --comment "abd"
:uabd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_uabd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.345 UABD page C7-2181 line 122708 MATCH x2e207400/mask=xbf20fc00
# CONSTRUCT x2ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $-@4 ARG3 ARG2 $-@4 2:4 &=$* ARG2 ARG3 $less@4 &=$*@4 =$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@4
# AUNIT --inst x2ea07400/mask=xffe0fc00 --status pass --comment "abd"
# This abd instruction is implemented correctly to document a correct
# way to implement the unsigned absolute difference semantic.
:uabd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
# simd infix TMPD1 = Rn_VPR64.2S - Rm_VPR64.2S on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] - Rm_VPR64.2S[0,32];
TMPD1[32,32] = Rn_VPR64.2S[32,32] - Rm_VPR64.2S[32,32];
# simd infix TMPD2 = Rm_VPR64.2S - Rn_VPR64.2S on lane size 4
TMPD2[0,32] = Rm_VPR64.2S[0,32] - Rn_VPR64.2S[0,32];
TMPD2[32,32] = Rm_VPR64.2S[32,32] - Rn_VPR64.2S[32,32];
# simd infix TMPD2 = TMPD2 * 2:4 on lane size 4
TMPD2[0,32] = TMPD2[0,32] * 2:4;
TMPD2[32,32] = TMPD2[32,32] * 2:4;
# simd infix TMPD3 = Rn_VPR64.2S < Rm_VPR64.2S on lane size 4
TMPD3[0,32] = zext(Rn_VPR64.2S[0,32] < Rm_VPR64.2S[0,32]);
TMPD3[32,32] = zext(Rn_VPR64.2S[32,32] < Rm_VPR64.2S[32,32]);
# simd infix TMPD2 = TMPD2 * TMPD3 on lane size 4
TMPD2[0,32] = TMPD2[0,32] * TMPD3[0,32];
TMPD2[32,32] = TMPD2[32,32] * TMPD3[32,32];
# simd infix Rd_VPR64.2S = TMPD1 + TMPD2 on lane size 4
Rd_VPR64.2S[0,32] = TMPD1[0,32] + TMPD2[0,32];
Rd_VPR64.2S[32,32] = TMPD1[32,32] + TMPD2[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.345 UABD page C7-2181 line 122708 MATCH x2e207400/mask=xbf20fc00
# CONSTRUCT x2e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@2
# AUNIT --inst x2e607400/mask=xffe0fc00 --status nopcodeop --comment "abd"
:uabd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_uabd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.345 UABD page C7-2181 line 122708 MATCH x2e207400/mask=xbf20fc00
# CONSTRUCT x6ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@4
# AUNIT --inst x6ea07400/mask=xffe0fc00 --status nopcodeop --comment "abd"
:uabd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_uabd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.345 UABD page C7-2181 line 122708 MATCH x2e207400/mask=xbf20fc00
# CONSTRUCT x2e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@1
# AUNIT --inst x2e207400/mask=xffe0fc00 --status nopcodeop --comment "abd"
:uabd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_uabd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.345 UABD page C7-2181 line 122708 MATCH x2e207400/mask=xbf20fc00
# CONSTRUCT x6e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@2
# AUNIT --inst x6e607400/mask=xffe0fc00 --status nopcodeop --comment "abd"
:uabd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_uabd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.346 UABDL, UABDL2 page C7-2183 line 122808 MATCH x2e207000/mask=xbf20fc00
# CONSTRUCT x6ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $-@8 =$abs@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl2/2@4
# AUNIT --inst x6ea07000/mask=xffe0fc00 --status pass --comment "ext abd"
:uabdl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x7 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = zext(TMPD3[0,32]);
TMPQ4[64,64] = zext(TMPD3[32,32]);
# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8
TMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64];
TMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64];
# simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ5) on lane size 8
Rd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ5[0,64]);
Rd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ5[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.346 UABDL, UABDL2 page C7-2183 line 122808 MATCH x2e207000/mask=xbf20fc00
# CONSTRUCT x6e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $-@4 =$abs@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl2/2@2
# AUNIT --inst x6e607000/mask=xffe0fc00 --status pass --comment "ext abd"
:uabdl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x7 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = zext(TMPD3[0,16]);
TMPQ4[32,32] = zext(TMPD3[16,16]);
TMPQ4[64,32] = zext(TMPD3[32,16]);
TMPQ4[96,32] = zext(TMPD3[48,16]);
# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4
TMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32];
TMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32];
TMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32];
TMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32];
# simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ5) on lane size 4
Rd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ5[0,32]);
Rd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ5[32,32]);
Rd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ5[64,32]);
Rd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ5[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.346 UABDL, UABDL2 page C7-2183 line 122808 MATCH x2e207000/mask=xbf20fc00
# CONSTRUCT x6e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $-@2 =$abs@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl2/2@1
# AUNIT --inst x6e207000/mask=xffe0fc00 --status pass --comment "ext abd"
:uabdl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x7 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = zext(TMPD1[0,8]);
TMPQ2[16,16] = zext(TMPD1[8,8]);
TMPQ2[32,16] = zext(TMPD1[16,8]);
TMPQ2[48,16] = zext(TMPD1[24,8]);
TMPQ2[64,16] = zext(TMPD1[32,8]);
TMPQ2[80,16] = zext(TMPD1[40,8]);
TMPQ2[96,16] = zext(TMPD1[48,8]);
TMPQ2[112,16] = zext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = zext(TMPD3[0,8]);
TMPQ4[16,16] = zext(TMPD3[8,8]);
TMPQ4[32,16] = zext(TMPD3[16,8]);
TMPQ4[48,16] = zext(TMPD3[24,8]);
TMPQ4[64,16] = zext(TMPD3[32,8]);
TMPQ4[80,16] = zext(TMPD3[40,8]);
TMPQ4[96,16] = zext(TMPD3[48,8]);
TMPQ4[112,16] = zext(TMPD3[56,8]);
# simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2
TMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16];
TMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16];
TMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16];
TMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16];
TMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16];
TMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16];
TMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16];
TMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16];
# simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ5) on lane size 2
Rd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ5[0,16]);
Rd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ5[16,16]);
Rd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ5[32,16]);
Rd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ5[48,16]);
Rd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ5[64,16]);
Rd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ5[80,16]);
Rd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ5[96,16]);
Rd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ5[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.346 UABDL, UABDL2 page C7-2183 line 122808 MATCH x2e207000/mask=xbf20fc00
# CONSTRUCT x2ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $-@8 =$abs@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl/2@4
# AUNIT --inst x2ea07000/mask=xffe0fc00 --status pass --comment "ext abd"
:uabdl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x7 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);
# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8
TMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64];
TMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64];
# simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ3) on lane size 8
Rd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ3[0,64]);
Rd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ3[64,64]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.346 UABDL, UABDL2 page C7-2183 line 122808 MATCH x2e207000/mask=xbf20fc00
# CONSTRUCT x2e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $-@4 =$abs@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl/2@2
# AUNIT --inst x2e607000/mask=xffe0fc00 --status pass --comment "ext abd"
:uabdl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x7 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Rn_VPR128 & Rm_VPR128 & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);
# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4
TMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32];
TMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32];
TMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32];
TMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32];
# simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ3) on lane size 4
Rd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ3[0,32]);
Rd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ3[32,32]);
Rd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ3[64,32]);
Rd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ3[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.346 UABDL, UABDL2 page C7-2183 line 122808 MATCH x2e207000/mask=xbf20fc00
# CONSTRUCT x2e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $-@2 =$abs@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl/2@1
# AUNIT --inst x2e207000/mask=xffe0fc00 --status pass --comment "ext abd"
:uabdl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x7 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Rn_VPR128 & Rm_VPR128 & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);
# simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2
TMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16];
TMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16];
TMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16];
TMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16];
TMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16];
TMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16];
TMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16];
TMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16];
# simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ3) on lane size 2
Rd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ3[0,16]);
Rd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ3[16,16]);
Rd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ3[32,16]);
Rd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ3[48,16]);
Rd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ3[64,16]);
Rd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ3[80,16]);
Rd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ3[96,16]);
Rd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ3[112,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.347 UADALP page C7-2185 line 122926 MATCH x2e206800/mask=xbf3ffc00
# CONSTRUCT x6e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 =#u+ &=$+@2
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@1
# AUNIT --inst x6e206800/mask=xfffffc00 --status pass --comment "ext"
:uadalp Rd_VPR128.8H, Rn_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = +(Rn_VPR128.16B) on pairs lane size (1 to 2)
tmp2 = Rn_VPR128.16B[0,8];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.16B[8,8];
tmp5 = zext(tmp3);
TMPQ1[0,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[16,8];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.16B[24,8];
tmp5 = zext(tmp3);
TMPQ1[16,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[32,8];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.16B[40,8];
tmp5 = zext(tmp3);
TMPQ1[32,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[48,8];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.16B[56,8];
tmp5 = zext(tmp3);
TMPQ1[48,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[64,8];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.16B[72,8];
tmp5 = zext(tmp3);
TMPQ1[64,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[80,8];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.16B[88,8];
tmp5 = zext(tmp3);
TMPQ1[80,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[96,8];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.16B[104,8];
tmp5 = zext(tmp3);
TMPQ1[96,16] = tmp4 + tmp5;
tmp2 = Rn_VPR128.16B[112,8];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.16B[120,8];
tmp5 = zext(tmp3);
TMPQ1[112,16] = tmp4 + tmp5;
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.347 UADALP page C7-2185 line 122926 MATCH x2e206800/mask=xbf3ffc00
# CONSTRUCT x2ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:8 ARG2 =#u+ &=$+@8
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@4
# AUNIT --inst x2ea06800/mask=xfffffc00 --status pass --comment "ext"
:uadalp Rd_VPR64.1D, Rn_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.1D & Zd
{
# sipd infix TMPD1 = +(Rn_VPR64.2S) on pairs lane size (4 to 8)
tmp2 = Rn_VPR64.2S[0,32];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR64.2S[32,32];
tmp5 = zext(tmp3);
tmpd1 = tmp4 + tmp5;
# simd infix Rd_VPR64.1D = Rd_VPR64.1D + TMPD1 on lane size 8
Rd_VPR64.1D[0,64] = Rd_VPR64.1D[0,64] + tmpd1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.347 UADALP page C7-2185 line 122926 MATCH x2e206800/mask=xbf3ffc00
# CONSTRUCT x2e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:8 ARG2 =#u+ &=$+@4
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@2
# AUNIT --inst x2e606800/mask=xfffffc00 --status pass --comment "ext"
:uadalp Rd_VPR64.2S, Rn_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.2S & Zd
{
TMPD1 = 0;
# sipd infix TMPD1 = +(Rn_VPR64.4H) on pairs lane size (2 to 4)
tmp2 = Rn_VPR64.4H[0,16];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR64.4H[16,16];
tmp5 = zext(tmp3);
TMPD1[0,32] = tmp4 + tmp5;
tmp2 = Rn_VPR64.4H[32,16];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR64.4H[48,16];
tmp5 = zext(tmp3);
TMPD1[32,32] = tmp4 + tmp5;
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.347 UADALP page C7-2185 line 122926 MATCH x2e206800/mask=xbf3ffc00
# CONSTRUCT x6ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 =#u+ &=$+@8
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@4
# AUNIT --inst x6ea06800/mask=xfffffc00 --status pass --comment "ext"
:uadalp Rd_VPR128.2D, Rn_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = +(Rn_VPR128.4S) on pairs lane size (4 to 8)
tmp2 = Rn_VPR128.4S[0,32];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.4S[32,32];
tmp5 = zext(tmp3);
TMPQ1[0,64] = tmp4 + tmp5;
tmp2 = Rn_VPR128.4S[64,32];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.4S[96,32];
tmp5 = zext(tmp3);
TMPQ1[64,64] = tmp4 + tmp5;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.347 UADALP page C7-2185 line 122926 MATCH x2e206800/mask=xbf3ffc00
# CONSTRUCT x2e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:8 ARG2 =#u+ &=$+@2
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@1
# AUNIT --inst x2e206800/mask=xfffffc00 --status pass --comment "ext"
:uadalp Rd_VPR64.4H, Rn_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.4H & Zd
{
TMPD1 = 0;
# sipd infix TMPD1 = +(Rn_VPR64.8B) on pairs lane size (1 to 2)
tmp2 = Rn_VPR64.8B[0,8];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR64.8B[8,8];
tmp5 = zext(tmp3);
TMPD1[0,16] = tmp4 + tmp5;
tmp2 = Rn_VPR64.8B[16,8];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR64.8B[24,8];
tmp5 = zext(tmp3);
TMPD1[16,16] = tmp4 + tmp5;
tmp2 = Rn_VPR64.8B[32,8];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR64.8B[40,8];
tmp5 = zext(tmp3);
TMPD1[32,16] = tmp4 + tmp5;
tmp2 = Rn_VPR64.8B[48,8];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR64.8B[56,8];
tmp5 = zext(tmp3);
TMPD1[48,16] = tmp4 + tmp5;
# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.347 UADALP page C7-2185 line 122926 MATCH x2e206800/mask=xbf3ffc00
# CONSTRUCT x6e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 var:16 ARG2 =#u+ &=$+@4
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@2
# AUNIT --inst x6e606800/mask=xfffffc00 --status pass --comment "ext"
:uadalp Rd_VPR128.4S, Rn_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPQ1 = 0;
# sipd infix TMPQ1 = +(Rn_VPR128.8H) on pairs lane size (2 to 4)
tmp2 = Rn_VPR128.8H[0,16];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.8H[16,16];
tmp5 = zext(tmp3);
TMPQ1[0,32] = tmp4 + tmp5;
tmp2 = Rn_VPR128.8H[32,16];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.8H[48,16];
tmp5 = zext(tmp3);
TMPQ1[32,32] = tmp4 + tmp5;
tmp2 = Rn_VPR128.8H[64,16];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.8H[80,16];
tmp5 = zext(tmp3);
TMPQ1[64,32] = tmp4 + tmp5;
tmp2 = Rn_VPR128.8H[96,16];
tmp4 = zext(tmp2);
tmp3 = Rn_VPR128.8H[112,16];
tmp5 = zext(tmp3);
TMPQ1[96,32] = tmp4 + tmp5;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.348 UADDL, UADDL2 page C7-2187 line 123035 MATCH x2e200000/mask=xbf20fc00
# CONSTRUCT x6ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 =$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl2/2@4
# AUNIT --inst x6ea00000/mask=xffe0fc00 --status pass --comment "ext"
:uaddl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x0 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = zext(TMPD3[0,32]);
TMPQ4[64,64] = zext(TMPD3[32,32]);
# simd infix Rd_VPR128.2D = TMPQ2 + TMPQ4 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ2[0,64] + TMPQ4[0,64];
Rd_VPR128.2D[64,64] = TMPQ2[64,64] + TMPQ4[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.348 UADDL, UADDL2 page C7-2187 line 123035 MATCH x2e200000/mask=xbf20fc00
# CONSTRUCT x6e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 =$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl2/2@2
# AUNIT --inst x6e600000/mask=xffe0fc00 --status pass --comment "ext"
:uaddl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x0 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = zext(TMPD3[0,16]);
TMPQ4[32,32] = zext(TMPD3[16,16]);
TMPQ4[64,32] = zext(TMPD3[32,16]);
TMPQ4[96,32] = zext(TMPD3[48,16]);
# simd infix Rd_VPR128.4S = TMPQ2 + TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ2[0,32] + TMPQ4[0,32];
Rd_VPR128.4S[32,32] = TMPQ2[32,32] + TMPQ4[32,32];
Rd_VPR128.4S[64,32] = TMPQ2[64,32] + TMPQ4[64,32];
Rd_VPR128.4S[96,32] = TMPQ2[96,32] + TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.348 UADDL, UADDL2 page C7-2187 line 123035 MATCH x2e200000/mask=xbf20fc00
# CONSTRUCT x6e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 =$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl2/2@1
# AUNIT --inst x6e200000/mask=xffe0fc00 --status pass --comment "ext"
:uaddl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x0 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = zext(TMPD1[0,8]);
TMPQ2[16,16] = zext(TMPD1[8,8]);
TMPQ2[32,16] = zext(TMPD1[16,8]);
TMPQ2[48,16] = zext(TMPD1[24,8]);
TMPQ2[64,16] = zext(TMPD1[32,8]);
TMPQ2[80,16] = zext(TMPD1[40,8]);
TMPQ2[96,16] = zext(TMPD1[48,8]);
TMPQ2[112,16] = zext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = zext(TMPD3[0,8]);
TMPQ4[16,16] = zext(TMPD3[8,8]);
TMPQ4[32,16] = zext(TMPD3[16,8]);
TMPQ4[48,16] = zext(TMPD3[24,8]);
TMPQ4[64,16] = zext(TMPD3[32,8]);
TMPQ4[80,16] = zext(TMPD3[40,8]);
TMPQ4[96,16] = zext(TMPD3[48,8]);
TMPQ4[112,16] = zext(TMPD3[56,8]);
# simd infix Rd_VPR128.8H = TMPQ2 + TMPQ4 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ2[0,16] + TMPQ4[0,16];
Rd_VPR128.8H[16,16] = TMPQ2[16,16] + TMPQ4[16,16];
Rd_VPR128.8H[32,16] = TMPQ2[32,16] + TMPQ4[32,16];
Rd_VPR128.8H[48,16] = TMPQ2[48,16] + TMPQ4[48,16];
Rd_VPR128.8H[64,16] = TMPQ2[64,16] + TMPQ4[64,16];
Rd_VPR128.8H[80,16] = TMPQ2[80,16] + TMPQ4[80,16];
Rd_VPR128.8H[96,16] = TMPQ2[96,16] + TMPQ4[96,16];
Rd_VPR128.8H[112,16] = TMPQ2[112,16] + TMPQ4[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.348 UADDL, UADDL2 page C7-2187 line 123035 MATCH x2e200000/mask=xbf20fc00
# CONSTRUCT x2ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 =$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl/2@4
# AUNIT --inst x2ea00000/mask=xffe0fc00 --status pass --comment "ext"
:uaddl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x0 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);
# simd infix Rd_VPR128.2D = TMPQ1 + TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64] + TMPQ2[0,64];
Rd_VPR128.2D[64,64] = TMPQ1[64,64] + TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.348 UADDL, UADDL2 page C7-2187 line 123035 MATCH x2e200000/mask=xbf20fc00
# CONSTRUCT x2e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 =$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl/2@2
# AUNIT --inst x2e600000/mask=xffe0fc00 --status pass --comment "ext"
:uaddl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x0 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);
# simd infix Rd_VPR128.4S = TMPQ1 + TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32] + TMPQ2[0,32];
Rd_VPR128.4S[32,32] = TMPQ1[32,32] + TMPQ2[32,32];
Rd_VPR128.4S[64,32] = TMPQ1[64,32] + TMPQ2[64,32];
Rd_VPR128.4S[96,32] = TMPQ1[96,32] + TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.348 UADDL, UADDL2 page C7-2187 line 123035 MATCH x2e200000/mask=xbf20fc00
# CONSTRUCT x2e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 =$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl/2@1
# AUNIT --inst x2e200000/mask=xffe0fc00 --status pass --comment "ext"
:uaddl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x0 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);
# simd infix Rd_VPR128.8H = TMPQ1 + TMPQ2 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[0,16] + TMPQ2[0,16];
Rd_VPR128.8H[16,16] = TMPQ1[16,16] + TMPQ2[16,16];
Rd_VPR128.8H[32,16] = TMPQ1[32,16] + TMPQ2[32,16];
Rd_VPR128.8H[48,16] = TMPQ1[48,16] + TMPQ2[48,16];
Rd_VPR128.8H[64,16] = TMPQ1[64,16] + TMPQ2[64,16];
Rd_VPR128.8H[80,16] = TMPQ1[80,16] + TMPQ2[80,16];
Rd_VPR128.8H[96,16] = TMPQ1[96,16] + TMPQ2[96,16];
Rd_VPR128.8H[112,16] = TMPQ1[112,16] + TMPQ2[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.349 UADDLP page C7-2189 line 123155 MATCH x2e202800/mask=xbf3ffc00
# CONSTRUCT x2e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =#u+@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@1
# AUNIT --inst x2e202800/mask=xfffffc00 --status pass --comment "ext"
# Vector variant when size = 00 , Q = 0 s=16 e1=1 e2=2 Ta=VPR64.4H Tb=VPR64.8B
:uaddlp Rd_VPR64.4H, Rn_VPR64.8B
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001010 & Rd_VPR64.4H & Rn_VPR64.8B & Zd
{
TMPD1 = Rn_VPR64.8B;
# sipd infix Rd_VPR64.4H = +(TMPD1) on pairs lane size (1 to 2)
tmp2 = TMPD1[0,8];
tmp4 = zext(tmp2);
tmp3 = TMPD1[8,8];
tmp5 = zext(tmp3);
Rd_VPR64.4H[0,16] = tmp4 + tmp5;
tmp2 = TMPD1[16,8];
tmp4 = zext(tmp2);
tmp3 = TMPD1[24,8];
tmp5 = zext(tmp3);
Rd_VPR64.4H[16,16] = tmp4 + tmp5;
tmp2 = TMPD1[32,8];
tmp4 = zext(tmp2);
tmp3 = TMPD1[40,8];
tmp5 = zext(tmp3);
Rd_VPR64.4H[32,16] = tmp4 + tmp5;
tmp2 = TMPD1[48,8];
tmp4 = zext(tmp2);
tmp3 = TMPD1[56,8];
tmp5 = zext(tmp3);
Rd_VPR64.4H[48,16] = tmp4 + tmp5;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.349 UADDLP page C7-2189 line 123155 MATCH x2e202800/mask=xbf3ffc00
# CONSTRUCT x6e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =#u+@1
# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@1
# AUNIT --inst x6e202800/mask=xfffffc00 --status pass --comment "ext"
# Vector variant when size = 00 , Q = 1 s=32 e1=1 e2=2 Ta=VPR128.8H Tb=VPR128.16B
:uaddlp Rd_VPR128.8H, Rn_VPR128.16B
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001010 & Rd_VPR128.8H & Rn_VPR128.16B & Zd
{
TMPQ1 = Rn_VPR128.16B;
# sipd infix Rd_VPR128.8H = +(TMPQ1) on pairs lane size (1 to 2)
tmp2 = TMPQ1[0,8];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[8,8];
tmp5 = zext(tmp3);
Rd_VPR128.8H[0,16] = tmp4 + tmp5;
tmp2 = TMPQ1[16,8];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[24,8];
tmp5 = zext(tmp3);
Rd_VPR128.8H[16,16] = tmp4 + tmp5;
tmp2 = TMPQ1[32,8];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[40,8];
tmp5 = zext(tmp3);
Rd_VPR128.8H[32,16] = tmp4 + tmp5;
tmp2 = TMPQ1[48,8];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[56,8];
tmp5 = zext(tmp3);
Rd_VPR128.8H[48,16] = tmp4 + tmp5;
tmp2 = TMPQ1[64,8];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[72,8];
tmp5 = zext(tmp3);
Rd_VPR128.8H[64,16] = tmp4 + tmp5;
tmp2 = TMPQ1[80,8];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[88,8];
tmp5 = zext(tmp3);
Rd_VPR128.8H[80,16] = tmp4 + tmp5;
tmp2 = TMPQ1[96,8];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[104,8];
tmp5 = zext(tmp3);
Rd_VPR128.8H[96,16] = tmp4 + tmp5;
tmp2 = TMPQ1[112,8];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[120,8];
tmp5 = zext(tmp3);
Rd_VPR128.8H[112,16] = tmp4 + tmp5;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.349 UADDLP page C7-2189 line 123155 MATCH x2e202800/mask=xbf3ffc00
# CONSTRUCT x2e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =#u+@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@2
# AUNIT --inst x2e602800/mask=xfffffc00 --status pass --comment "ext"
# Vector variant when size = 01 , Q = 0 s=16 e1=2 e2=4 Ta=VPR64.2S Tb=VPR64.4H
:uaddlp Rd_VPR64.2S, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001010 & Rd_VPR64.2S & Rn_VPR64.4H & Zd
{
TMPD1 = Rn_VPR64.4H;
# sipd infix Rd_VPR64.2S = +(TMPD1) on pairs lane size (2 to 4)
tmp2 = TMPD1[0,16];
tmp4 = zext(tmp2);
tmp3 = TMPD1[16,16];
tmp5 = zext(tmp3);
Rd_VPR64.2S[0,32] = tmp4 + tmp5;
tmp2 = TMPD1[32,16];
tmp4 = zext(tmp2);
tmp3 = TMPD1[48,16];
tmp5 = zext(tmp3);
Rd_VPR64.2S[32,32] = tmp4 + tmp5;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.349 UADDLP page C7-2189 line 123155 MATCH x2e202800/mask=xbf3ffc00
# CONSTRUCT x6e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =#u+@2
# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@2
# AUNIT --inst x6e602800/mask=xfffffc00 --status pass --comment "ext"
# Vector variant when size = 01 , Q = 1 s=32 e1=2 e2=4 Ta=VPR128.4S Tb=VPR128.8H
:uaddlp Rd_VPR128.4S, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001010 & Rd_VPR128.4S & Rn_VPR128.8H & Zd
{
TMPQ1 = Rn_VPR128.8H;
# sipd infix Rd_VPR128.4S = +(TMPQ1) on pairs lane size (2 to 4)
tmp2 = TMPQ1[0,16];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[16,16];
tmp5 = zext(tmp3);
Rd_VPR128.4S[0,32] = tmp4 + tmp5;
tmp2 = TMPQ1[32,16];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[48,16];
tmp5 = zext(tmp3);
Rd_VPR128.4S[32,32] = tmp4 + tmp5;
tmp2 = TMPQ1[64,16];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[80,16];
tmp5 = zext(tmp3);
Rd_VPR128.4S[64,32] = tmp4 + tmp5;
tmp2 = TMPQ1[96,16];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[112,16];
tmp5 = zext(tmp3);
Rd_VPR128.4S[96,32] = tmp4 + tmp5;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.349 UADDLP page C7-2189 line 123155 MATCH x2e202800/mask=xbf3ffc00
# CONSTRUCT x2ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =#u+@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@4
# AUNIT --inst x2ea02800/mask=xfffffc00 --status pass --comment "ext"
# Vector variant when size = 10 , Q = 0 s=16 e1=4 e2=8 Ta=VPR64.1D Tb=VPR64.2S
:uaddlp Rd_VPR64.1D, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001010 & Rd_VPR64.1D & Rn_VPR64.2S & Zd
{
TMPD1 = Rn_VPR64.2S;
# sipd infix Rd_VPR64.1D = +(TMPD1) on pairs lane size (4 to 8)
tmp2 = TMPD1[0,32];
tmp4 = zext(tmp2);
tmp3 = TMPD1[32,32];
tmp5 = zext(tmp3);
Rd_VPR64.1D[0,64] = tmp4 + tmp5;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.349 UADDLP page C7-2189 line 123155 MATCH x2e202800/mask=xbf3ffc00
# CONSTRUCT x6ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =#u+@4
# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@4
# AUNIT --inst x6ea02800/mask=xfffffc00 --status pass --comment "ext"
# Vector variant when size = 10 , Q = 1 s=32 e1=4 e2=8 Ta=VPR128.2D Tb=VPR128.4S
:uaddlp Rd_VPR128.2D, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001010 & Rd_VPR128.2D & Rn_VPR128.4S & Zd
{
TMPQ1 = Rn_VPR128.4S;
# sipd infix Rd_VPR128.2D = +(TMPQ1) on pairs lane size (4 to 8)
tmp2 = TMPQ1[0,32];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[32,32];
tmp5 = zext(tmp3);
Rd_VPR128.2D[0,64] = tmp4 + tmp5;
tmp2 = TMPQ1[64,32];
tmp4 = zext(tmp2);
tmp3 = TMPQ1[96,32];
tmp5 = zext(tmp3);
Rd_VPR128.2D[64,64] = tmp4 + tmp5;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.350 UADDLV page C7-2191 line 123264 MATCH x2e303800/mask=xbf3ffc00
# CONSTRUCT x6eb03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@4
# AUNIT --inst x6eb03800/mask=xfffffc00 --status nopcodeop --comment "ext"
:uaddlv Rd_FPR64, Rn_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.4S & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_uaddlv(Rn_VPR128.4S, 4:1);
}
# C7.2.350 UADDLV page C7-2191 line 123264 MATCH x2e303800/mask=xbf3ffc00
# CONSTRUCT x6e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@1
# AUNIT --inst x6e303800/mask=xfffffc00 --status nopcodeop --comment "ext"
:uaddlv Rd_FPR16, Rn_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.16B & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_uaddlv(Rn_VPR128.16B, 1:1);
}
# C7.2.350 UADDLV page C7-2191 line 123264 MATCH x2e303800/mask=xbf3ffc00
# CONSTRUCT x2e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@1
# AUNIT --inst x2e303800/mask=xfffffc00 --status nopcodeop --comment "ext"
:uaddlv Rd_FPR16, Rn_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.8B & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_uaddlv(Rn_VPR64.8B, 1:1);
}
# C7.2.350 UADDLV page C7-2191 line 123264 MATCH x2e303800/mask=xbf3ffc00
# CONSTRUCT x2e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@2
# AUNIT --inst x2e703800/mask=xfffffc00 --status nopcodeop --comment "ext"
:uaddlv Rd_FPR32, Rn_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.4H & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_uaddlv(Rn_VPR64.4H, 2:1);
}
# C7.2.350 UADDLV page C7-2191 line 123264 MATCH x2e303800/mask=xbf3ffc00
# CONSTRUCT x6e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@2
# AUNIT --inst x6e703800/mask=xfffffc00 --status nopcodeop --comment "ext"
:uaddlv Rd_FPR32, Rn_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.8H & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_uaddlv(Rn_VPR128.8H, 2:1);
}
# C7.2.351 UADDW, UADDW2 page C7-2193 line 123362 MATCH x2e201000/mask=xbf20fc00
# CONSTRUCT x6ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@4:16 =$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw2/2@4
# AUNIT --inst x6ea01000/mask=xffe0fc00 --status pass --comment "ext"
:uaddw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
TMPD1 = Rm_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
# simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ2[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.351 UADDW, UADDW2 page C7-2193 line 123362 MATCH x2e201000/mask=xbf20fc00
# CONSTRUCT x6e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@2:16 =$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw2/2@2
# AUNIT --inst x6e601000/mask=xffe0fc00 --status pass --comment "ext"
:uaddw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
TMPD1 = Rm_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
# simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ2[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ2[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ2[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.351 UADDW, UADDW2 page C7-2193 line 123362 MATCH x2e201000/mask=xbf20fc00
# CONSTRUCT x6e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@1:16 =$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw2/2@1
# AUNIT --inst x6e201000/mask=xffe0fc00 --status pass --comment "ext"
:uaddw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
TMPD1 = Rm_VPR128.16B[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = zext(TMPD1[0,8]);
TMPQ2[16,16] = zext(TMPD1[8,8]);
TMPQ2[32,16] = zext(TMPD1[16,8]);
TMPQ2[48,16] = zext(TMPD1[24,8]);
TMPQ2[64,16] = zext(TMPD1[32,8]);
TMPQ2[80,16] = zext(TMPD1[40,8]);
TMPQ2[96,16] = zext(TMPD1[48,8]);
TMPQ2[112,16] = zext(TMPD1[56,8]);
# simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ2 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ2[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ2[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ2[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ2[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ2[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ2[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ2[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ2[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.351 UADDW, UADDW2 page C7-2193 line 123362 MATCH x2e201000/mask=xbf20fc00
# CONSTRUCT x2ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $zext@4:16 =$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw/2@4
# AUNIT --inst x2ea01000/mask=xffe0fc00 --status pass --comment "ext"
:uaddw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = zext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = zext(Rm_VPR64.2S[0,32]);
TMPQ1[64,64] = zext(Rm_VPR64.2S[32,32]);
# simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.351 UADDW, UADDW2 page C7-2193 line 123362 MATCH x2e201000/mask=xbf20fc00
# CONSTRUCT x2e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $zext@2:16 =$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw/2@2
# AUNIT --inst x2e601000/mask=xffe0fc00 --status pass --comment "ext"
:uaddw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = zext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = zext(Rm_VPR64.4H[0,16]);
TMPQ1[32,32] = zext(Rm_VPR64.4H[16,16]);
TMPQ1[64,32] = zext(Rm_VPR64.4H[32,16]);
TMPQ1[96,32] = zext(Rm_VPR64.4H[48,16]);
# simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.351 UADDW, UADDW2 page C7-2193 line 123362 MATCH x2e201000/mask=xbf20fc00
# CONSTRUCT x2e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $zext@1:16 =$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw/2@1
# AUNIT --inst x2e201000/mask=xffe0fc00 --status pass --comment "ext"
:uaddw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = zext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = zext(Rm_VPR64.8B[0,8]);
TMPQ1[16,16] = zext(Rm_VPR64.8B[8,8]);
TMPQ1[32,16] = zext(Rm_VPR64.8B[16,8]);
TMPQ1[48,16] = zext(Rm_VPR64.8B[24,8]);
TMPQ1[64,16] = zext(Rm_VPR64.8B[32,8]);
TMPQ1[80,16] = zext(Rm_VPR64.8B[40,8]);
TMPQ1[96,16] = zext(Rm_VPR64.8B[48,8]);
TMPQ1[112,16] = zext(Rm_VPR64.8B[56,8]);
# simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.352 UCVTF (vector, fixed-point) page C7-2195 line 123484 MATCH x7f00e400/mask=xff80fc00
# CONSTRUCT x7f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2
# AUNIT --inst x7f40e400/mask=xffc0fc00 --status nopcodeop --comment "nofpround"
:ucvtf Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_3031=1 & u=1 & b_2428=0x1f & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_ucvtf(Rn_FPR64, Imm_shr_imm64:1);
}
# C7.2.352 UCVTF (vector, fixed-point) page C7-2195 line 123484 MATCH x7f00e400/mask=xff80fc00
# CONSTRUCT x7f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2
# AUNIT --inst x7f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround"
:ucvtf Rd_FPR32, Rn_FPR32, Imm_shr_imm32
is b_3031=1 & u=1 & b_2428=0x1f & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_ucvtf(Rn_FPR32, Imm_shr_imm32:1);
}
# C7.2.352 UCVTF (vector, fixed-point) page C7-2195 line 123484 MATCH x7f00e400/mask=xff80fc00
# CONSTRUCT x7f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2
# AUNIT --inst x7f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround"
:ucvtf Rd_FPR16, Rn_FPR16, Imm_shr_imm16
is b_3031=1 & u=1 & b_2428=0x1f & b_2023=1 & Imm_shr_imm16 & b_1115=0x1c & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_ucvtf(Rn_FPR16, Imm_shr_imm16:1);
}
# C7.2.352 UCVTF (vector, fixed-point) page C7-2195 line 123484 MATCH x2f00e400/mask=xbf80fc00
# CONSTRUCT x6f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@8
# AUNIT --inst x6f40e400/mask=xffc0fc00 --status nopcodeop --comment "nofpround"
:ucvtf Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_ucvtf(Rn_VPR128.2D, Imm_shr_imm64:1, 8:1);
}
# C7.2.352 UCVTF (vector, fixed-point) page C7-2195 line 123484 MATCH x2f00e400/mask=xbf80fc00
# CONSTRUCT x2f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@4
# AUNIT --inst x2f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround"
:ucvtf Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_ucvtf(Rn_VPR64.2S, Imm_shr_imm32:1, 4:1);
}
# C7.2.352 UCVTF (vector, fixed-point) page C7-2195 line 123484 MATCH x2f00e400/mask=xbf80fc00
# CONSTRUCT x6f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@4
# AUNIT --inst x6f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround"
:ucvtf Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_ucvtf(Rn_VPR128.4S, Imm_shr_imm32:1, 4:1);
}
# C7.2.352 UCVTF (vector, fixed-point) page C7-2195 line 123484 MATCH x2f00e400/mask=xbf80fc00
# CONSTRUCT x2f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@2
# AUNIT --inst x2f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround"
:ucvtf Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm32
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_ucvtf(Rn_VPR64.4H, Imm_shr_imm32:1, 2:1);
}
# C7.2.352 UCVTF (vector, fixed-point) page C7-2195 line 123484 MATCH x2f00e400/mask=xbf80fc00
# CONSTRUCT x6f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@2
# AUNIT --inst x6f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround"
:ucvtf Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm32
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_ucvtf(Rn_VPR128.8H, Imm_shr_imm32:1, 2:1);
}
# C7.2.353 UCVTF (vector, integer) page C7-2198 line 123634 MATCH x7e21d800/mask=xffbffc00
# CONSTRUCT x7e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
# AUNIT --inst x7e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
:ucvtf Rd_FPR32, Rn_FPR32
is b_3031=1 & u=1 & b_2428=0x1e & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_ucvtf(Rn_FPR32);
}
# C7.2.353 UCVTF (vector, integer) page C7-2198 line 123634 MATCH x7e21d800/mask=xffbffc00
# CONSTRUCT x7e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
# AUNIT --inst x7e61d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
:ucvtf Rd_FPR64, Rn_FPR64
is b_3031=1 & u=1 & b_2428=0x1e & size_high=0 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_ucvtf(Rn_FPR64);
}
# C7.2.353 UCVTF (vector, integer) page C7-2198 line 123634 MATCH x2e21d800/mask=xbfbffc00
# CONSTRUCT x2e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@4
# AUNIT --inst x2e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
:ucvtf Rd_VPR64.2S, Rn_VPR64.2S
is sf=0 & q=0 & b_2929=1 & b_2428=0x0e & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1d & b_1011=2 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_ucvtf(Rn_VPR64.2S, 4:1);
}
# C7.2.353 UCVTF (vector, integer) page C7-2198 line 123634 MATCH x2e21d800/mask=xbfbffc00
# CONSTRUCT x6e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@4
# AUNIT --inst x6e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
:ucvtf Rd_VPR128.4S, Rn_VPR128.4S
is sf=0 & q=1 & b_2929=1 & b_2428=0x0e & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1d & b_1011=2 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_ucvtf(Rn_VPR128.4S, 4:1);
}
# C7.2.353 UCVTF (vector, integer) page C7-2198 line 123634 MATCH x2e21d800/mask=xbfbffc00
# CONSTRUCT x6e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@8
# AUNIT --inst x6e61d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
:ucvtf Rd_VPR128.2D, Rn_VPR128.2D
is sf=0 & q=1 & b_2929=1 & b_2428=0x0e & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x1d & b_1011=2 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_ucvtf(Rn_VPR128.2D, 8:1);
}
# C7.2.353 UCVTF (vector, integer) page C7-2198 line 123634 MATCH x7e79d800/mask=xfffffc00
# CONSTRUCT x7e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
# AUNIT --inst x7e79d800/mask=xfffffc00 --status noqemu --comment "nofpround"
# Scalar half precision variant
:ucvtf Rd_FPR16, Rn_FPR16
is b_1031=0b0111111001111001110110 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = NEON_ucvtf(Rn_FPR16);
}
# C7.2.353 UCVTF (vector, integer) page C7-2198 line 123634 MATCH x2e79d800/mask=xbffffc00
# CONSTRUCT x2e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@2
# AUNIT --inst x2e79d800/mask=xfffffc00 --status noqemu --comment "nofpround"
# Vector half precision variant when Q=0 T=VPR64.4H
:ucvtf Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_1029=0b10111001111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_ucvtf(Rn_VPR64.4H, 2:1);
}
# C7.2.353 UCVTF (vector, integer) page C7-2198 line 123634 MATCH x2e79d800/mask=xbffffc00
# CONSTRUCT x6e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@2
# AUNIT --inst x6e79d800/mask=xfffffc00 --status noqemu --comment "nofpround"
# Vector half precision variant when Q=1 T=VPR128.8H
:ucvtf Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_1029=0b10111001111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_ucvtf(Rn_VPR128.8H, 2:1);
}
# C7.2.354 UCVTF (scalar, fixed-point) page C7-2201 line 123812 MATCH x1e030000/mask=x7f3f0000
# CONSTRUCT x1ec38000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 zext:8 int2float:2 FBits16 =f/
# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_ucvtf/2
# AUNIT --inst x1ec38000/mask=xffff8000 --status noqemu --comment "nofpround"
# if sf == '0' && scale<5> == '0' then UnallocatedEncoding();
:ucvtf Rd_FPR16, Rn_GPR32, FBitsOp
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=3 & b_15=1 & FBitsOp & FBits16 & Rn_GPR32 & Rd_FPR16 & Zd
{
local tmp1:8 = zext(Rn_GPR32);
local tmp2:2 = int2float(tmp1);
Rd_FPR16 = tmp2 f/ FBits16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.354 UCVTF (scalar, fixed-point) page C7-2201 line 123812 MATCH x1e030000/mask=x7f3f0000
# CONSTRUCT x9ec30000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 zext:9 int2float:2 FBits16 =f/
# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_ucvtf/2
# AUNIT --inst x9ec30000/mask=xffff0000 --status noqemu --comment "nofpround"
:ucvtf Rd_FPR16, Rn_GPR64, FBitsOp
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=3 & FBitsOp & FBits16 & Rn_GPR64 & Rd_FPR16 & Zd
{
local tmp1:9 = zext(Rn_GPR64);
local tmp2:2 = int2float(tmp1);
Rd_FPR16 = tmp2 f/ FBits16;
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.354 UCVTF (scalar, fixed-point) page C7-2201 line 123812 MATCH x1e030000/mask=x7f3f0000
# CONSTRUCT x1e438000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 zext:8 int2float:8 FBits64 =f/
# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_ucvtf/2
# AUNIT --inst x1e438000/mask=xffff8000 --status pass --comment "nofpround"
# if sf == '0' && scale<5> == '0' then UnallocatedEncoding();
:ucvtf Rd_FPR64, Rn_GPR32, FBitsOp
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=3 & b_15=1 & FBitsOp & FBits64 & Rn_GPR32 & Rd_FPR64 & Zd
{
local tmp1:8 = zext(Rn_GPR32);
local tmp2:8 = int2float(tmp1);
Rd_FPR64 = tmp2 f/ FBits64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.354 UCVTF (scalar, fixed-point) page C7-2201 line 123812 MATCH x1e030000/mask=x7f3f0000
# CONSTRUCT x9e430000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 zext:9 int2float:8 FBits64 =f/
# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_ucvtf/2
# AUNIT --inst x9e430000/mask=xffff0000 --status fail --comment "nofpround"
# The zext:9 naively force unsigned int before conversion
:ucvtf Rd_FPR64, Rn_GPR64, FBitsOp
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=3 & FBitsOp & FBits64 & Rn_GPR64 & Rd_FPR64 & Zd
{
local tmp1:9 = zext(Rn_GPR64);
local tmp2:8 = int2float(tmp1);
Rd_FPR64 = tmp2 f/ FBits64;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.354 UCVTF (scalar, fixed-point) page C7-2201 line 123812 MATCH x1e030000/mask=x7f3f0000
# CONSTRUCT x1e038000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 zext:8 int2float:4 FBits32 =f/
# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_ucvtf/2
# AUNIT --inst x1e038000/mask=xffff8000 --status fail --comment "nofpround"
# if sf == '0' && scale<5> == '0' then UnallocatedEncoding();
:ucvtf Rd_FPR32, Rn_GPR32, FBitsOp
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=3 & b_15=1 & FBitsOp & FBits32 & Rn_GPR32 & Rd_FPR32 & Zd
{
local tmp1:8 = zext(Rn_GPR32);
local tmp2:4 = int2float(tmp1);
Rd_FPR32 = tmp2 f/ FBits32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.354 UCVTF (scalar, fixed-point) page C7-2201 line 123812 MATCH x1e030000/mask=x7f3f0000
# CONSTRUCT x9e030000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 zext:9 int2float:4 FBits32 =f/
# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_ucvtf/2
# AUNIT --inst x9e030000/mask=xffff0000 --status fail --comment "nofpround"
:ucvtf Rd_FPR32, Rn_GPR64, FBitsOp
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=3 & FBitsOp & FBits32 & Rn_GPR64 & Rd_FPR32 & Zd
{
local tmp1:9 = zext(Rn_GPR64);
local tmp2:4 = int2float(tmp1);
Rd_FPR32 = tmp2 f/ FBits32;
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.355 UCVTF (scalar, integer) page C7-2203 line 123942 MATCH x1e230000/mask=x7f3ffc00
# CONSTRUCT x1ee30000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 zext:8 =int2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
# AUNIT --inst x1ee30000/mask=xfffffc00 --status noqemu --comment "nofpround"
:ucvtf Rd_FPR16, Rn_GPR32
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR32 & Rd_FPR16 & Zd
{
local tmp1:8 = zext(Rn_GPR32);
Rd_FPR16 = int2float(tmp1);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.355 UCVTF (scalar, integer) page C7-2203 line 123942 MATCH x1e230000/mask=x7f3ffc00
# CONSTRUCT x9ee30000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 zext:9 =int2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
# AUNIT --inst x9ee30000/mask=xfffffc00 --status noqemu --comment "nofpround"
:ucvtf Rd_FPR16, Rn_GPR64
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR64 & Rd_FPR16 & Zd
{
local tmp1:9 = zext(Rn_GPR64);
Rd_FPR16 = int2float(tmp1);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.355 UCVTF (scalar, integer) page C7-2203 line 123942 MATCH x1e230000/mask=x7f3ffc00
# CONSTRUCT x1e630000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 zext:8 =int2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
# AUNIT --inst x1e630000/mask=xfffffc00 --status pass --comment "nofpround"
:ucvtf Rd_FPR64, Rn_GPR32
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR32 & Rd_FPR64 & Zd
{
local tmp1:8 = zext(Rn_GPR32);
Rd_FPR64 = int2float(tmp1);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.355 UCVTF (scalar, integer) page C7-2203 line 123942 MATCH x1e230000/mask=x7f3ffc00
# CONSTRUCT x9e630000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 zext:9 =int2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
# AUNIT --inst x9e630000/mask=xfffffc00 --status fail --comment "nofpround"
:ucvtf Rd_FPR64, Rn_GPR64
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR64 & Rd_FPR64 & Zd
{
local tmp1:9 = zext(Rn_GPR64);
Rd_FPR64 = int2float(tmp1);
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.355 UCVTF (scalar, integer) page C7-2203 line 123942 MATCH x1e230000/mask=x7f3ffc00
# CONSTRUCT x1e230000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 zext:8 =int2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
# AUNIT --inst x1e230000/mask=xfffffc00 --status fail --comment "nofpround"
:ucvtf Rd_FPR32, Rn_GPR32
is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR32 & Rd_FPR32 & Zd
{
local tmp1:8 = zext(Rn_GPR32);
Rd_FPR32 = int2float(tmp1);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.355 UCVTF (scalar, integer) page C7-2203 line 123942 MATCH x1e230000/mask=x7f3ffc00
# CONSTRUCT x9e230000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 zext:9 =int2float
# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
# AUNIT --inst x9e230000/mask=xfffffc00 --status fail --comment "nofpround"
:ucvtf Rd_FPR32, Rn_GPR64
is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR64 & Rd_FPR32 & Zd
{
local tmp1:9 = zext(Rn_GPR64);
Rd_FPR32 = int2float(tmp1);
zext_zs(Zd); # zero upper 28 bytes of Zd
}
# C7.2.356 UDOT (by element) page C7-2205 line 124065 MATCH x2f00e000/mask=xbf00f400
# CONSTRUCT x2f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_udot/2@1
# AUNIT --inst x2f80e000/mask=xffc0f400 --status noqemu
# Vector variant when Q=0 Ta=VPR64.2S Tb=VPR64.8B
:udot Rd_VPR64.2S, Rn_VPR64.8B, Re_VPR128.B.vIndex
is b_31=0 & b_30=0 & b_2429=0b101111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR64.2S & Rn_VPR64.8B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd
{
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
Rd_VPR64.2S = NEON_udot(Rn_VPR64.8B, tmp1, 1:1);
}
# C7.2.356 UDOT (by element) page C7-2205 line 124065 MATCH x2f00e000/mask=xbf00f400
# CONSTRUCT x6f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_udot/2@1
# AUNIT --inst x6f80e000/mask=xffc0f400 --status noqemu
# Vector variant when Q=1 Ta=VPR128.4S Tb=VPR128.16B
:udot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.B.vIndex
is b_31=0 & b_30=1 & b_2429=0b101111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR128.4S & Rn_VPR128.16B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd
{
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
Rd_VPR128.4S = NEON_udot(Rn_VPR128.16B, tmp1, 1:1);
}
# C7.2.357 UDOT (vector) page C7-2207 line 124164 MATCH x2e009400/mask=xbf20fc00
# CONSTRUCT x2e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_udot/2@1
# AUNIT --inst x2e809400/mask=xffe0fc00 --status noqemu
# Three registers of the same type variant when Q=0 Ta=VPR64.2S Tb=VPR64.8B
:udot Rd_VPR64.2S, Rn_VPR64.8B, Rm_VPR64.8B
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR64.2S & Rn_VPR64.8B & Rm_VPR64.8B & Zd
{
Rd_VPR64.2S = NEON_udot(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.357 UDOT (vector) page C7-2207 line 124164 MATCH x2e009400/mask=xbf20fc00
# CONSTRUCT x6e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_udot/2@1
# AUNIT --inst x6e809400/mask=xffe0fc00 --status noqemu
# Three registers of the same type variant when Q=1 Ta=VPR128.4S Tb=VPR128.16B
:udot Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR128.4S & Rn_VPR128.16B & Rm_VPR128.16B & Zd
{
Rd_VPR128.4S = NEON_udot(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.358 UHADD page C7-2209 line 124262 MATCH x2e200400/mask=xbf20fc00
# CONSTRUCT x6e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@1
# AUNIT --inst x6e200400/mask=xffe0fc00 --status nopcodeop
:uhadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_uhadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.358 UHADD page C7-2209 line 124262 MATCH x2e200400/mask=xbf20fc00
# CONSTRUCT x2ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@4
# AUNIT --inst x2ea00400/mask=xffe0fc00 --status nopcodeop
:uhadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_uhadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.358 UHADD page C7-2209 line 124262 MATCH x2e200400/mask=xbf20fc00
# CONSTRUCT x2e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@2
# AUNIT --inst x2e600400/mask=xffe0fc00 --status nopcodeop
:uhadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_uhadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.358 UHADD page C7-2209 line 124262 MATCH x2e200400/mask=xbf20fc00
# CONSTRUCT x6ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@4
# AUNIT --inst x6ea00400/mask=xffe0fc00 --status nopcodeop
:uhadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_uhadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.358 UHADD page C7-2209 line 124262 MATCH x2e200400/mask=xbf20fc00
# CONSTRUCT x2e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@1
# AUNIT --inst x2e200400/mask=xffe0fc00 --status nopcodeop
:uhadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_uhadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.358 UHADD page C7-2209 line 124262 MATCH x2e200400/mask=xbf20fc00
# CONSTRUCT x6e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@2
# AUNIT --inst x6e600400/mask=xffe0fc00 --status nopcodeop
:uhadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_uhadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.359 UHSUB page C7-2211 line 124362 MATCH x2e202400/mask=xbf20fc00
# CONSTRUCT x6e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@1
# AUNIT --inst x6e202400/mask=xffe0fc00 --status nopcodeop
:uhsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_uhsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.359 UHSUB page C7-2211 line 124362 MATCH x2e202400/mask=xbf20fc00
# CONSTRUCT x2ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@4
# AUNIT --inst x2ea02400/mask=xffe0fc00 --status nopcodeop
:uhsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_uhsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.359 UHSUB page C7-2211 line 124362 MATCH x2e202400/mask=xbf20fc00
# CONSTRUCT x2e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@2
# AUNIT --inst x2e602400/mask=xffe0fc00 --status nopcodeop
:uhsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_uhsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.359 UHSUB page C7-2211 line 124362 MATCH x2e202400/mask=xbf20fc00
# CONSTRUCT x6ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@4
# AUNIT --inst x6ea02400/mask=xffe0fc00 --status nopcodeop
:uhsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_uhsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.359 UHSUB page C7-2211 line 124362 MATCH x2e202400/mask=xbf20fc00
# CONSTRUCT x2e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@1
# AUNIT --inst x2e202400/mask=xffe0fc00 --status nopcodeop
:uhsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_uhsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.359 UHSUB page C7-2211 line 124362 MATCH x2e202400/mask=xbf20fc00
# CONSTRUCT x6e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@2
# AUNIT --inst x6e602400/mask=xffe0fc00 --status nopcodeop
:uhsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_uhsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.360 UMAX page C7-2213 line 124460 MATCH x2e206400/mask=xbf20fc00
# CONSTRUCT x6e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@1
# AUNIT --inst x6e206400/mask=xffe0fc00 --status nopcodeop
:umax Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xc & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_umax(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.360 UMAX page C7-2213 line 124460 MATCH x2e206400/mask=xbf20fc00
# CONSTRUCT x2ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@4
# AUNIT --inst x2ea06400/mask=xffe0fc00 --status nopcodeop
:umax Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xc & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_umax(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.360 UMAX page C7-2213 line 124460 MATCH x2e206400/mask=xbf20fc00
# CONSTRUCT x2e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@2
# AUNIT --inst x2e606400/mask=xffe0fc00 --status nopcodeop
:umax Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xc & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_umax(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.360 UMAX page C7-2213 line 124460 MATCH x2e206400/mask=xbf20fc00
# CONSTRUCT x6ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@4
# AUNIT --inst x6ea06400/mask=xffe0fc00 --status nopcodeop
:umax Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xc & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_umax(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.360 UMAX page C7-2213 line 124460 MATCH x2e206400/mask=xbf20fc00
# CONSTRUCT x2e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@1
# AUNIT --inst x2e206400/mask=xffe0fc00 --status nopcodeop
:umax Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xc & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_umax(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.360 UMAX page C7-2213 line 124460 MATCH x2e206400/mask=xbf20fc00
# CONSTRUCT x6e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@2
# AUNIT --inst x6e606400/mask=xffe0fc00 --status nopcodeop
:umax Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xc & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_umax(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.361 UMAXP page C7-2215 line 124560 MATCH x2e20a400/mask=xbf20fc00
# CONSTRUCT x6e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@1
# AUNIT --inst x6e20a400/mask=xffe0fc00 --status nopcodeop
:umaxp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_umaxp(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.361 UMAXP page C7-2215 line 124560 MATCH x2e20a400/mask=xbf20fc00
# CONSTRUCT x2ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@4
# AUNIT --inst x2ea0a400/mask=xffe0fc00 --status nopcodeop
:umaxp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_umaxp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.361 UMAXP page C7-2215 line 124560 MATCH x2e20a400/mask=xbf20fc00
# CONSTRUCT x2e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@2
# AUNIT --inst x2e60a400/mask=xffe0fc00 --status nopcodeop
:umaxp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_umaxp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.361 UMAXP page C7-2215 line 124560 MATCH x2e20a400/mask=xbf20fc00
# CONSTRUCT x6ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@4
# AUNIT --inst x6ea0a400/mask=xffe0fc00 --status nopcodeop
:umaxp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_umaxp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.361 UMAXP page C7-2215 line 124560 MATCH x2e20a400/mask=xbf20fc00
# CONSTRUCT x2e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@1
# AUNIT --inst x2e20a400/mask=xffe0fc00 --status nopcodeop
:umaxp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_umaxp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.361 UMAXP page C7-2215 line 124560 MATCH x2e20a400/mask=xbf20fc00
# CONSTRUCT x6e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@2
# AUNIT --inst x6e60a400/mask=xffe0fc00 --status nopcodeop
:umaxp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_umaxp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.362 UMAXV page C7-2217 line 124662 MATCH x2e30a800/mask=xbf3ffc00
# CONSTRUCT x6e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@1
# AUNIT --inst x6e30a800/mask=xfffffc00 --status nopcodeop
:umaxv Rd_FPR8, Rn_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_umaxv(Rn_VPR128.16B, 1:1);
}
# C7.2.362 UMAXV page C7-2217 line 124662 MATCH x2e30a800/mask=xbf3ffc00
# CONSTRUCT x2e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@1
# AUNIT --inst x2e30a800/mask=xfffffc00 --status nopcodeop
:umaxv Rd_FPR8, Rn_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_umaxv(Rn_VPR64.8B, 1:1);
}
# C7.2.362 UMAXV page C7-2217 line 124662 MATCH x2e30a800/mask=xbf3ffc00
# CONSTRUCT x2e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@2
# AUNIT --inst x2e70a800/mask=xfffffc00 --status nopcodeop
:umaxv Rd_FPR16, Rn_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_umaxv(Rn_VPR64.4H, 2:1);
}
# C7.2.362 UMAXV page C7-2217 line 124662 MATCH x2e30a800/mask=xbf3ffc00
# CONSTRUCT x6e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@2
# AUNIT --inst x6e70a800/mask=xfffffc00 --status nopcodeop
:umaxv Rd_FPR16, Rn_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_umaxv(Rn_VPR128.8H, 2:1);
}
# C7.2.362 UMAXV page C7-2217 line 124662 MATCH x2e30a800/mask=xbf3ffc00
# CONSTRUCT x6eb0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@4
# AUNIT --inst x6eb0a800/mask=xfffffc00 --status nopcodeop
:umaxv Rd_FPR32, Rn_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_umaxv(Rn_VPR128.4S, 4:1);
}
# C7.2.363 UMIN page C7-2219 line 124763 MATCH x2e206c00/mask=xbf20fc00
# CONSTRUCT x6e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@1
# AUNIT --inst x6e206c00/mask=xffe0fc00 --status nopcodeop
:umin Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xd & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_umin(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.363 UMIN page C7-2219 line 124763 MATCH x2e206c00/mask=xbf20fc00
# CONSTRUCT x2ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@4
# AUNIT --inst x2ea06c00/mask=xffe0fc00 --status nopcodeop
:umin Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xd & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_umin(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.363 UMIN page C7-2219 line 124763 MATCH x2e206c00/mask=xbf20fc00
# CONSTRUCT x2e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@2
# AUNIT --inst x2e606c00/mask=xffe0fc00 --status nopcodeop
:umin Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xd & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_umin(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.363 UMIN page C7-2219 line 124763 MATCH x2e206c00/mask=xbf20fc00
# CONSTRUCT x6ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@4
# AUNIT --inst x6ea06c00/mask=xffe0fc00 --status nopcodeop
:umin Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xd & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_umin(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.363 UMIN page C7-2219 line 124763 MATCH x2e206c00/mask=xbf20fc00
# CONSTRUCT x2e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@1
# AUNIT --inst x2e206c00/mask=xffe0fc00 --status nopcodeop
:umin Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xd & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_umin(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.363 UMIN page C7-2219 line 124763 MATCH x2e206c00/mask=xbf20fc00
# CONSTRUCT x6e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@2
# AUNIT --inst x6e606c00/mask=xffe0fc00 --status nopcodeop
:umin Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xd & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_umin(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.364 UMINP page C7-2221 line 124863 MATCH x2e20ac00/mask=xbf20fc00
# CONSTRUCT x6e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@1
# AUNIT --inst x6e20ac00/mask=xffe0fc00 --status nopcodeop
:uminp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x15 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_uminp(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.364 UMINP page C7-2221 line 124863 MATCH x2e20ac00/mask=xbf20fc00
# CONSTRUCT x2ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@4
# AUNIT --inst x2ea0ac00/mask=xffe0fc00 --status nopcodeop
:uminp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x15 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_uminp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.364 UMINP page C7-2221 line 124863 MATCH x2e20ac00/mask=xbf20fc00
# CONSTRUCT x2e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@2
# AUNIT --inst x2e60ac00/mask=xffe0fc00 --status nopcodeop
:uminp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x15 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_uminp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.364 UMINP page C7-2221 line 124863 MATCH x2e20ac00/mask=xbf20fc00
# CONSTRUCT x6ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@4
# AUNIT --inst x6ea0ac00/mask=xffe0fc00 --status nopcodeop
:uminp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x15 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_uminp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.364 UMINP page C7-2221 line 124863 MATCH x2e20ac00/mask=xbf20fc00
# CONSTRUCT x2e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@1
# AUNIT --inst x2e20ac00/mask=xffe0fc00 --status nopcodeop
:uminp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x15 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_uminp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.364 UMINP page C7-2221 line 124863 MATCH x2e20ac00/mask=xbf20fc00
# CONSTRUCT x6e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@2
# AUNIT --inst x6e60ac00/mask=xffe0fc00 --status nopcodeop
:uminp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x15 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_uminp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.365 UMINV page C7-2223 line 124965 MATCH x2e31a800/mask=xbf3ffc00
# CONSTRUCT x6e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@1
# AUNIT --inst x6e31a800/mask=xfffffc00 --status nopcodeop
:uminv Rd_FPR8, Rn_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_uminv(Rn_VPR128.16B, 1:1);
}
# C7.2.365 UMINV page C7-2223 line 124965 MATCH x2e31a800/mask=xbf3ffc00
# CONSTRUCT x2e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@1
# AUNIT --inst x2e31a800/mask=xfffffc00 --status nopcodeop
:uminv Rd_FPR8, Rn_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_uminv(Rn_VPR64.8B, 1:1);
}
# C7.2.365 UMINV page C7-2223 line 124965 MATCH x2e31a800/mask=xbf3ffc00
# CONSTRUCT x2e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@2
# AUNIT --inst x2e71a800/mask=xfffffc00 --status nopcodeop
:uminv Rd_FPR16, Rn_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_uminv(Rn_VPR64.4H, 2:1);
}
# C7.2.365 UMINV page C7-2223 line 124965 MATCH x2e31a800/mask=xbf3ffc00
# CONSTRUCT x6e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@2
# AUNIT --inst x6e71a800/mask=xfffffc00 --status nopcodeop
:uminv Rd_FPR16, Rn_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_uminv(Rn_VPR128.8H, 2:1);
}
# C7.2.365 UMINV page C7-2223 line 124965 MATCH x2e31a800/mask=xbf3ffc00
# CONSTRUCT x6eb1a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@4
# AUNIT --inst x6eb1a800/mask=xfffffc00 --status nopcodeop
:uminv Rd_FPR32, Rn_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_uminv(Rn_VPR128.4S, 4:1);
}
# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2225 line 125066 MATCH x2f002000/mask=xbf00f400
# CONSTRUCT x2f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@4:16 ARG3 zext:8 $* &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@4
# AUNIT --inst x2f802000/mask=xffc0f400 --status pass --comment "ext"
:umlal Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = zext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ2[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2225 line 125066 MATCH x2f002000/mask=xbf00f400
# CONSTRUCT x6f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 zext:8 $* &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@4
# AUNIT --inst x6f802000/mask=xffc0f400 --status pass --comment "ext"
:umlal2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp3:4 = Re_VPR128.S.vIndex;
local tmp4:8 = zext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2225 line 125066 MATCH x2f002000/mask=xbf00f400
# CONSTRUCT x2f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@2:16 ARG3 zext:4 $* &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@2
# AUNIT --inst x2f402000/mask=xffc0f400 --status pass --comment "ext"
:umlal Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = zext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ2[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ2[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ2[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2225 line 125066 MATCH x2f002000/mask=xbf00f400
# CONSTRUCT x6f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 zext:4 $* &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@2
# AUNIT --inst x6f402000/mask=xffc0f400 --status pass --comment "ext"
:umlal2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp4:4 = zext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2228 line 125227 MATCH x2e208000/mask=xbf20fc00
# CONSTRUCT x6ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $*@8 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@4
# AUNIT --inst x6ea08000/mask=xffe0fc00 --status pass --comment "ext"
:umlal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x8 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = zext(TMPD3[0,32]);
TMPQ4[64,64] = zext(TMPD3[32,32]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ5 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ5[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ5[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2228 line 125227 MATCH x2e208000/mask=xbf20fc00
# CONSTRUCT x6e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $*@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@2
# AUNIT --inst x6e608000/mask=xffe0fc00 --status pass --comment "ext"
:umlal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x8 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = zext(TMPD3[0,16]);
TMPQ4[32,32] = zext(TMPD3[16,16]);
TMPQ4[64,32] = zext(TMPD3[32,16]);
TMPQ4[96,32] = zext(TMPD3[48,16]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ5 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ5[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ5[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ5[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ5[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2228 line 125227 MATCH x2e208000/mask=xbf20fc00
# CONSTRUCT x6e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $*@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@1
# AUNIT --inst x6e208000/mask=xffe0fc00 --status pass --comment "ext"
:umlal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x8 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = zext(TMPD1[0,8]);
TMPQ2[16,16] = zext(TMPD1[8,8]);
TMPQ2[32,16] = zext(TMPD1[16,8]);
TMPQ2[48,16] = zext(TMPD1[24,8]);
TMPQ2[64,16] = zext(TMPD1[32,8]);
TMPQ2[80,16] = zext(TMPD1[40,8]);
TMPQ2[96,16] = zext(TMPD1[48,8]);
TMPQ2[112,16] = zext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = zext(TMPD3[0,8]);
TMPQ4[16,16] = zext(TMPD3[8,8]);
TMPQ4[32,16] = zext(TMPD3[16,8]);
TMPQ4[48,16] = zext(TMPD3[24,8]);
TMPQ4[64,16] = zext(TMPD3[32,8]);
TMPQ4[80,16] = zext(TMPD3[40,8]);
TMPQ4[96,16] = zext(TMPD3[48,8]);
TMPQ4[112,16] = zext(TMPD3[56,8]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2
TMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16];
TMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16];
TMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16];
TMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16];
TMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16];
TMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16];
TMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16];
TMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16];
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ5 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ5[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ5[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ5[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ5[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ5[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ5[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ5[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ5[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2228 line 125227 MATCH x2e208000/mask=xbf20fc00
# CONSTRUCT x2ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $*@8 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@4
# AUNIT --inst x2ea08000/mask=xffe0fc00 --status pass --comment "ext"
:umlal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x8 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8
TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2228 line 125227 MATCH x2e208000/mask=xbf20fc00
# CONSTRUCT x2e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $*@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@2
# AUNIT --inst x2e608000/mask=xffe0fc00 --status pass --comment "ext"
:umlal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x8 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4
TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2228 line 125227 MATCH x2e208000/mask=xbf20fc00
# CONSTRUCT x2e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $*@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@1
# AUNIT --inst x2e208000/mask=xffe0fc00 --status pass --comment "ext"
:umlal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x8 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2
TMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16];
TMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16];
TMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16];
TMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16];
TMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16];
TMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16];
TMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16];
TMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16];
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ3 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ3[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ3[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ3[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ3[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ3[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ3[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ3[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ3[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2230 line 125350 MATCH x2f006000/mask=xbf00f400
# CONSTRUCT x2f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@4:16 ARG3 zext:8 $*@8 &=$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@4
# AUNIT --inst x2f806000/mask=xffc0f400 --status pass --comment "ext"
:umlsl Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = zext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ2[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2230 line 125350 MATCH x2f006000/mask=xbf00f400
# CONSTRUCT x6f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 zext:8 $*@8 &=$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@4
# AUNIT --inst x6f806000/mask=xffc0f400 --status pass --comment "ext"
:umlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp3:4 = Re_VPR128.S.vIndex;
local tmp4:8 = zext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2230 line 125350 MATCH x2f006000/mask=xbf00f400
# CONSTRUCT x2f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@2:16 ARG3 zext:4 $*@4 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@2
# AUNIT --inst x2f406000/mask=xffc0f400 --status pass --comment "ext"
:umlsl Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = zext(tmp2);
# simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ2[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ2[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ2[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2230 line 125350 MATCH x2f006000/mask=xbf00f400
# CONSTRUCT x6f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 zext:4 $*@4 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@2
# AUNIT --inst x6f406000/mask=xffc0f400 --status pass --comment "ext"
:umlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp4:4 = zext(tmp3);
# simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2233 line 125511 MATCH x2e20a000/mask=xbf20fc00
# CONSTRUCT x6ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $*@8 &=$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@4
# AUNIT --inst x6ea0a000/mask=xffe0fc00 --status pass --comment "ext"
:umlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xa & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = zext(TMPD3[0,32]);
TMPQ4[64,64] = zext(TMPD3[32,32]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ5 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ5[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ5[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2233 line 125511 MATCH x2e20a000/mask=xbf20fc00
# CONSTRUCT x6e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $*@4 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@2
# AUNIT --inst x6e60a000/mask=xffe0fc00 --status pass --comment "ext"
:umlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xa & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = zext(TMPD3[0,16]);
TMPQ4[32,32] = zext(TMPD3[16,16]);
TMPQ4[64,32] = zext(TMPD3[32,16]);
TMPQ4[96,32] = zext(TMPD3[48,16]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ5 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ5[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ5[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ5[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ5[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2233 line 125511 MATCH x2e20a000/mask=xbf20fc00
# CONSTRUCT x6e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $*@2 &=$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@1
# AUNIT --inst x6e20a000/mask=xffe0fc00 --status pass --comment "ext"
:umlsl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xa & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = zext(TMPD1[0,8]);
TMPQ2[16,16] = zext(TMPD1[8,8]);
TMPQ2[32,16] = zext(TMPD1[16,8]);
TMPQ2[48,16] = zext(TMPD1[24,8]);
TMPQ2[64,16] = zext(TMPD1[32,8]);
TMPQ2[80,16] = zext(TMPD1[40,8]);
TMPQ2[96,16] = zext(TMPD1[48,8]);
TMPQ2[112,16] = zext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = zext(TMPD3[0,8]);
TMPQ4[16,16] = zext(TMPD3[8,8]);
TMPQ4[32,16] = zext(TMPD3[16,8]);
TMPQ4[48,16] = zext(TMPD3[24,8]);
TMPQ4[64,16] = zext(TMPD3[32,8]);
TMPQ4[80,16] = zext(TMPD3[40,8]);
TMPQ4[96,16] = zext(TMPD3[48,8]);
TMPQ4[112,16] = zext(TMPD3[56,8]);
# simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2
TMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16];
TMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16];
TMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16];
TMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16];
TMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16];
TMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16];
TMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16];
TMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16];
# simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ5 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ5[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ5[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ5[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ5[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ5[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ5[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ5[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ5[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2233 line 125511 MATCH x2e20a000/mask=xbf20fc00
# CONSTRUCT x2ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $*@8 &=$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@4
# AUNIT --inst x2ea0a000/mask=xffe0fc00 --status pass --comment "ext"
:umlsl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xa & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8
TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
# simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2233 line 125511 MATCH x2e20a000/mask=xbf20fc00
# CONSTRUCT x2e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $*@4 &=$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@2
# AUNIT --inst x2e60a000/mask=xffe0fc00 --status pass --comment "ext"
:umlsl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xa & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Rd_VPR128 & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4
TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
# simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2233 line 125511 MATCH x2e20a000/mask=xbf20fc00
# CONSTRUCT x2e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $*@2 &=$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@1
# AUNIT --inst x2e20a000/mask=xffe0fc00 --status pass --comment "ext"
:umlsl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xa & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Rd_VPR128 & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);
# simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2
TMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16];
TMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16];
TMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16];
TMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16];
TMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16];
TMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16];
TMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16];
TMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16];
# simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ3 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ3[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ3[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ3[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ3[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ3[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ3[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ3[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ3[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.371 UMOV page C7-2236 line 125692 MATCH x0e003c00/mask=xbfe0fc00
# CONSTRUCT x0e013c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =zext:4
# SMACRO(pseudo) ARG1 ARG2 =NEON_umov/1
# AUNIT --inst x0e013c00/mask=xffe1fc00 --status pass
:umov Rd_GPR32, Rn_VPR128.B.imm_neon_uimm4
is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64
{
# simd element Rn_VPR128[imm_neon_uimm4] lane size 1
local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;
Rd_GPR32 = zext(tmp1);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.371 UMOV page C7-2236 line 125692 MATCH x0e003c00/mask=xbfe0fc00
# CONSTRUCT x0e023c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =zext:4
# SMACRO(pseudo) ARG1 ARG2 =NEON_umov/1
# AUNIT --inst x0e023c00/mask=xffe3fc00 --status pass
:umov Rd_GPR32, Rn_VPR128.H.imm_neon_uimm3
is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64 & Rd_VPR128
{
# simd element Rn_VPR128[imm_neon_uimm3] lane size 2
local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;
Rd_GPR32 = zext(tmp1);
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
}
# C7.2.372 UMULL, UMULL2 (by element) page C7-2238 line 125820 MATCH x2f00a000/mask=xbf00f400
# CONSTRUCT x6f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 zext:8 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@4
# AUNIT --inst x6f80a000/mask=xffc0f400 --status pass --comment "ext"
:umull2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp3:4 = Re_VPR128.S.vIndex;
local tmp4:8 = zext(tmp3);
# simd infix Rd_VPR128.2D = TMPQ2 * tmp4 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ2[0,64] * tmp4;
Rd_VPR128.2D[64,64] = TMPQ2[64,64] * tmp4;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.372 UMULL, UMULL2 (by element) page C7-2238 line 125820 MATCH x2f00a000/mask=xbf00f400
# CONSTRUCT x6f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 zext:4 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@2
# AUNIT --inst x6f40a000/mask=xffc0f400 --status pass --comment "ext"
:umull2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp4:4 = zext(tmp3);
# simd infix Rd_VPR128.4S = TMPQ2 * tmp4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ2[0,32] * tmp4;
Rd_VPR128.4S[32,32] = TMPQ2[32,32] * tmp4;
Rd_VPR128.4S[64,32] = TMPQ2[64,32] * tmp4;
Rd_VPR128.4S[96,32] = TMPQ2[96,32] * tmp4;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.372 UMULL, UMULL2 (by element) page C7-2238 line 125820 MATCH x2f00a000/mask=xbf00f400
# CONSTRUCT x2f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@4:16 ARG3 zext:8 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@4
# AUNIT --inst x2f80a000/mask=xffc0f400 --status pass --comment "ext"
:umull Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
# simd element Re_VPR128.S[vIndex] lane size 4
local tmp2:4 = Re_VPR128.S.vIndex;
local tmp3:8 = zext(tmp2);
# simd infix Rd_VPR128.2D = TMPQ1 * tmp3 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64] * tmp3;
Rd_VPR128.2D[64,64] = TMPQ1[64,64] * tmp3;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.372 UMULL, UMULL2 (by element) page C7-2238 line 125820 MATCH x2f00a000/mask=xbf00f400
# CONSTRUCT x2f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@2:16 ARG3 zext:4 =$*
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@2
# AUNIT --inst x2f40a000/mask=xffc0f400 --status pass --comment "ext"
:umull Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
# simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
local tmp3:4 = zext(tmp2);
# simd infix Rd_VPR128.4S = TMPQ1 * tmp3 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32] * tmp3;
Rd_VPR128.4S[32,32] = TMPQ1[32,32] * tmp3;
Rd_VPR128.4S[64,32] = TMPQ1[64,32] * tmp3;
Rd_VPR128.4S[96,32] = TMPQ1[96,32] * tmp3;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.373 UMULL, UMULL2 (vector) page C7-2241 line 125973 MATCH x2e20c000/mask=xbf20fc00
# CONSTRUCT x6ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 =$*@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@4
# AUNIT --inst x6ea0c000/mask=xffe0fc00 --status pass --comment "ext"
:umull2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xc & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = zext(TMPD3[0,32]);
TMPQ4[64,64] = zext(TMPD3[32,32]);
# simd infix Rd_VPR128.2D = TMPQ2 * TMPQ4 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
Rd_VPR128.2D[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.373 UMULL, UMULL2 (vector) page C7-2241 line 125973 MATCH x2e20c000/mask=xbf20fc00
# CONSTRUCT x6e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 =$*@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@2
# AUNIT --inst x6e60c000/mask=xffe0fc00 --status pass --comment "ext"
:umull2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xc & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = zext(TMPD3[0,16]);
TMPQ4[32,32] = zext(TMPD3[16,16]);
TMPQ4[64,32] = zext(TMPD3[32,16]);
TMPQ4[96,32] = zext(TMPD3[48,16]);
# simd infix Rd_VPR128.4S = TMPQ2 * TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
Rd_VPR128.4S[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
Rd_VPR128.4S[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
Rd_VPR128.4S[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.373 UMULL, UMULL2 (vector) page C7-2241 line 125973 MATCH x2e20c000/mask=xbf20fc00
# CONSTRUCT x6e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 =$*@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@1
# AUNIT --inst x6e20c000/mask=xffe0fc00 --status pass --comment "ext"
:umull2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xc & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = zext(TMPD1[0,8]);
TMPQ2[16,16] = zext(TMPD1[8,8]);
TMPQ2[32,16] = zext(TMPD1[16,8]);
TMPQ2[48,16] = zext(TMPD1[24,8]);
TMPQ2[64,16] = zext(TMPD1[32,8]);
TMPQ2[80,16] = zext(TMPD1[40,8]);
TMPQ2[96,16] = zext(TMPD1[48,8]);
TMPQ2[112,16] = zext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = zext(TMPD3[0,8]);
TMPQ4[16,16] = zext(TMPD3[8,8]);
TMPQ4[32,16] = zext(TMPD3[16,8]);
TMPQ4[48,16] = zext(TMPD3[24,8]);
TMPQ4[64,16] = zext(TMPD3[32,8]);
TMPQ4[80,16] = zext(TMPD3[40,8]);
TMPQ4[96,16] = zext(TMPD3[48,8]);
TMPQ4[112,16] = zext(TMPD3[56,8]);
# simd infix Rd_VPR128.8H = TMPQ2 * TMPQ4 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ2[0,16] * TMPQ4[0,16];
Rd_VPR128.8H[16,16] = TMPQ2[16,16] * TMPQ4[16,16];
Rd_VPR128.8H[32,16] = TMPQ2[32,16] * TMPQ4[32,16];
Rd_VPR128.8H[48,16] = TMPQ2[48,16] * TMPQ4[48,16];
Rd_VPR128.8H[64,16] = TMPQ2[64,16] * TMPQ4[64,16];
Rd_VPR128.8H[80,16] = TMPQ2[80,16] * TMPQ4[80,16];
Rd_VPR128.8H[96,16] = TMPQ2[96,16] * TMPQ4[96,16];
Rd_VPR128.8H[112,16] = TMPQ2[112,16] * TMPQ4[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.373 UMULL, UMULL2 (vector) page C7-2241 line 125973 MATCH x2e20c000/mask=xbf20fc00
# CONSTRUCT x2ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@4
# AUNIT --inst x2ea0c000/mask=xffe0fc00 --status nopcodeop --comment "ext"
:umull Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xc & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_umull(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.373 UMULL, UMULL2 (vector) page C7-2241 line 125973 MATCH x2e20c000/mask=xbf20fc00
# CONSTRUCT x2e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@2
# AUNIT --inst x2e60c000/mask=xffe0fc00 --status nopcodeop --comment "ext"
:umull Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xc & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_umull(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.373 UMULL, UMULL2 (vector) page C7-2241 line 125973 MATCH x2e20c000/mask=xbf20fc00
# CONSTRUCT x2e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@1
# AUNIT --inst x2e20c000/mask=xffe0fc00 --status nopcodeop --comment "ext"
:umull Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xc & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_umull(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.374 UQADD page C7-2243 line 126088 MATCH x7e200c00/mask=xff20fc00
# CONSTRUCT x7e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2
# AUNIT --inst x7e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqadd Rd_FPR8, Rn_FPR8, Rm_FPR8
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x1 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_uqadd(Rn_FPR8, Rm_FPR8);
}
# C7.2.374 UQADD page C7-2243 line 126088 MATCH x7e200c00/mask=xff20fc00
# CONSTRUCT x7ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2
# AUNIT --inst x7ee00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqadd Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x1 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_uqadd(Rn_FPR64, Rm_FPR64);
}
# C7.2.374 UQADD page C7-2243 line 126088 MATCH x7e200c00/mask=xff20fc00
# CONSTRUCT x7e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2
# AUNIT --inst x7e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqadd Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x1 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_uqadd(Rn_FPR16, Rm_FPR16);
}
# C7.2.374 UQADD page C7-2243 line 126088 MATCH x7e200c00/mask=xff20fc00
# CONSTRUCT x7ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2
# AUNIT --inst x7ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqadd Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x1 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_uqadd(Rn_FPR32, Rm_FPR32);
}
# C7.2.374 UQADD page C7-2243 line 126088 MATCH x2e200c00/mask=xbf20fc00
# CONSTRUCT x6e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@1
# AUNIT --inst x6e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x1 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_uqadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.374 UQADD page C7-2243 line 126088 MATCH x2e200c00/mask=xbf20fc00
# CONSTRUCT x6ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@8
# AUNIT --inst x6ee00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x1 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_uqadd(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.374 UQADD page C7-2243 line 126088 MATCH x2e200c00/mask=xbf20fc00
# CONSTRUCT x2ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@4
# AUNIT --inst x2ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x1 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_uqadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.374 UQADD page C7-2243 line 126088 MATCH x2e200c00/mask=xbf20fc00
# CONSTRUCT x2e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@2
# AUNIT --inst x2e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x1 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_uqadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.374 UQADD page C7-2243 line 126088 MATCH x2e200c00/mask=xbf20fc00
# CONSTRUCT x6ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@4
# AUNIT --inst x6ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x1 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_uqadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.374 UQADD page C7-2243 line 126088 MATCH x2e200c00/mask=xbf20fc00
# CONSTRUCT x2e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@1
# AUNIT --inst x2e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x1 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_uqadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.374 UQADD page C7-2243 line 126088 MATCH x2e200c00/mask=xbf20fc00
# CONSTRUCT x6e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@2
# AUNIT --inst x6e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x1 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_uqadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.375 UQRSHL page C7-2245 line 126213 MATCH x7e205c00/mask=xff20fc00
# CONSTRUCT x7e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2
# AUNIT --inst x7e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqrshl Rd_FPR8, Rn_FPR8, Rm_FPR8
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0xb & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_uqrshl(Rn_FPR8, Rm_FPR8);
}
# C7.2.375 UQRSHL page C7-2245 line 126213 MATCH x7e205c00/mask=xff20fc00
# CONSTRUCT x7ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2
# AUNIT --inst x7ee05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqrshl Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xb & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_uqrshl(Rn_FPR64, Rm_FPR64);
}
# C7.2.375 UQRSHL page C7-2245 line 126213 MATCH x7e205c00/mask=xff20fc00
# CONSTRUCT x7e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2
# AUNIT --inst x7e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqrshl Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0xb & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_uqrshl(Rn_FPR16, Rm_FPR16);
}
# C7.2.375 UQRSHL page C7-2245 line 126213 MATCH x7e205c00/mask=xff20fc00
# CONSTRUCT x7ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2
# AUNIT --inst x7ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqrshl Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0xb & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_uqrshl(Rn_FPR32, Rm_FPR32);
}
# C7.2.375 UQRSHL page C7-2245 line 126213 MATCH x2e205c00/mask=xbf20fc00
# CONSTRUCT x6e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@1
# AUNIT --inst x6e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqrshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xb & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_uqrshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.375 UQRSHL page C7-2245 line 126213 MATCH x2e205c00/mask=xbf20fc00
# CONSTRUCT x6ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@8
# AUNIT --inst x6ee05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqrshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xb & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_uqrshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.375 UQRSHL page C7-2245 line 126213 MATCH x2e205c00/mask=xbf20fc00
# CONSTRUCT x2ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@4
# AUNIT --inst x2ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqrshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xb & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_uqrshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.375 UQRSHL page C7-2245 line 126213 MATCH x2e205c00/mask=xbf20fc00
# CONSTRUCT x2e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@2
# AUNIT --inst x2e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqrshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xb & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_uqrshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.375 UQRSHL page C7-2245 line 126213 MATCH x2e205c00/mask=xbf20fc00
# CONSTRUCT x6ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@4
# AUNIT --inst x6ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqrshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xb & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_uqrshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.375 UQRSHL page C7-2245 line 126213 MATCH x2e205c00/mask=xbf20fc00
# CONSTRUCT x2e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@1
# AUNIT --inst x2e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqrshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xb & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_uqrshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.375 UQRSHL page C7-2245 line 126213 MATCH x2e205c00/mask=xbf20fc00
# CONSTRUCT x6e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@2
# AUNIT --inst x6e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqrshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xb & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_uqrshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2247 line 126351 MATCH x2f009c00/mask=xbf80fc00
# CONSTRUCT x6f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn2/2@2
# AUNIT --inst x6f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
:uqrshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_uqrshrn2(Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2247 line 126351 MATCH x2f009c00/mask=xbf80fc00
# CONSTRUCT x2f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@8
# AUNIT --inst x2f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqrshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_uqrshrn(Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2247 line 126351 MATCH x2f009c00/mask=xbf80fc00
# CONSTRUCT x2f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@4
# AUNIT --inst x2f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
:uqrshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_uqrshrn(Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2247 line 126351 MATCH x2f009c00/mask=xbf80fc00
# CONSTRUCT x6f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@8
# AUNIT --inst x6f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
:uqrshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_uqrshrn(Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2247 line 126351 MATCH x2f009c00/mask=xbf80fc00
# CONSTRUCT x2f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@2
# AUNIT --inst x2f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
:uqrshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_uqrshrn(Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2247 line 126351 MATCH x2f009c00/mask=xbf80fc00
# CONSTRUCT x6f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn2/2@4
# AUNIT --inst x6f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
:uqrshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_uqrshrn2(Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2247 line 126351 MATCH x7f009c00/mask=xff80fc00
# CONSTRUCT x7f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2
# AUNIT --inst x7f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
:uqrshrn Rd_FPR8, Rn_FPR16, Imm_shr_imm8
is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100111 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd
{
Rd_FPR8 = NEON_uqrshrn(Rn_FPR16, Imm_shr_imm8:1);
}
# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2247 line 126351 MATCH x7f009c00/mask=xff80fc00
# CONSTRUCT x7f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2
# AUNIT --inst x7f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
:uqrshrn Rd_FPR16, Rn_FPR32, Imm_shr_imm16
is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100111 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd
{
Rd_FPR16 = NEON_uqrshrn(Rn_FPR32, Imm_shr_imm16:1);
}
# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2247 line 126351 MATCH x7f009c00/mask=xff80fc00
# CONSTRUCT x7f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2
# AUNIT --inst x7f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
:uqrshrn Rd_FPR32, Rn_FPR64, Imm_shr_imm32
is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100111 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd
{
Rd_FPR32 = NEON_uqrshrn(Rn_FPR64, Imm_shr_imm32:1);
}
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x2f007400/mask=xbf80fc00
# CONSTRUCT x6f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@1
# AUNIT --inst x6f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_uqshl(Rn_VPR128.16B, Imm_uimm3:1, 1:1);
}
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x2f007400/mask=xbf80fc00
# CONSTRUCT x6f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@8
# AUNIT --inst x6f407400/mask=xffc0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xe & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_uqshl(Rn_VPR128.2D, Imm_imm0_63:1, 8:1);
}
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x2f007400/mask=xbf80fc00
# CONSTRUCT x2f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@4
# AUNIT --inst x2f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_uqshl(Rn_VPR64.2S, Imm_uimm5:1, 4:1);
}
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x2f007400/mask=xbf80fc00
# CONSTRUCT x2f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@2
# AUNIT --inst x2f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_uqshl(Rn_VPR64.4H, Imm_uimm4:1, 2:1);
}
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x2f007400/mask=xbf80fc00
# CONSTRUCT x6f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@4
# AUNIT --inst x6f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_uqshl(Rn_VPR128.4S, Imm_uimm5:1, 4:1);
}
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x2f007400/mask=xbf80fc00
# CONSTRUCT x2f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@1
# AUNIT --inst x2f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_uqshl(Rn_VPR64.8B, Imm_uimm3:1, 1:1);
}
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x2f007400/mask=xbf80fc00
# CONSTRUCT x6f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@2
# AUNIT --inst x6f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_uqshl(Rn_VPR128.8H, Imm_uimm4:1, 2:1);
}
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x7f007400/mask=xff80fc00
# CONSTRUCT x7f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2
# AUNIT --inst x7f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=0001 V=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
:uqshl Rd_FPR8, Rn_FPR8, Imm_shr_imm8
is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b011101 & Rd_FPR8 & Rn_FPR8 & Imm_shr_imm8 & Zd
{
Rd_FPR8 = NEON_uqshl(Rn_FPR8, Imm_shr_imm8:1);
}
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x7f007400/mask=xff80fc00
# CONSTRUCT x7f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2
# AUNIT --inst x7f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=001x V=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
:uqshl Rd_FPR16, Rn_FPR16, Imm_shr_imm16
is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b011101 & Rd_FPR16 & Rn_FPR16 & Imm_shr_imm16 & Zd
{
Rd_FPR16 = NEON_uqshl(Rn_FPR16, Imm_shr_imm16:1);
}
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x7f007400/mask=xff80fc00
# CONSTRUCT x7f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2
# AUNIT --inst x7f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=01xx V=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
:uqshl Rd_FPR32, Rn_FPR32, Imm_shr_imm32
is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b011101 & Rd_FPR32 & Rn_FPR32 & Imm_shr_imm32 & Zd
{
Rd_FPR32 = NEON_uqshl(Rn_FPR32, Imm_shr_imm32:1);
}
# C7.2.377 UQSHL (immediate) page C7-2250 line 126535 MATCH x7f007400/mask=xff80fc00
# CONSTRUCT x7f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2
# AUNIT --inst x7f407400/mask=xffc0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=1xxx V=FPR64 imm=Imm_shr_imm64 bb=b_22 aa=1
:uqshl Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_2331=0b011111110 & b_22=1 & b_1015=0b011101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
{
Rd_FPR64 = NEON_uqshl(Rn_FPR64, Imm_shr_imm64:1);
}
# C7.2.378 UQSHL (register) page C7-2253 line 126700 MATCH x7e204c00/mask=xff20fc00
# CONSTRUCT x7e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2
# AUNIT --inst x7e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_FPR8, Rn_FPR8, Rm_FPR8
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x9 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_uqshl(Rn_FPR8, Rm_FPR8);
}
# C7.2.378 UQSHL (register) page C7-2253 line 126700 MATCH x7e204c00/mask=xff20fc00
# CONSTRUCT x7ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2
# AUNIT --inst x7ee04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x9 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_uqshl(Rn_FPR64, Rm_FPR64);
}
# C7.2.378 UQSHL (register) page C7-2253 line 126700 MATCH x7e204c00/mask=xff20fc00
# CONSTRUCT x7e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2
# AUNIT --inst x7e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x9 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_uqshl(Rn_FPR16, Rm_FPR16);
}
# C7.2.378 UQSHL (register) page C7-2253 line 126700 MATCH x7e204c00/mask=xff20fc00
# CONSTRUCT x7ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2
# AUNIT --inst x7ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x9 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_uqshl(Rn_FPR32, Rm_FPR32);
}
# C7.2.378 UQSHL (register) page C7-2253 line 126700 MATCH x2e204c00/mask=xbf20fc00
# CONSTRUCT x6e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@1
# AUNIT --inst x6e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x9 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_uqshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.378 UQSHL (register) page C7-2253 line 126700 MATCH x2e204c00/mask=xbf20fc00
# CONSTRUCT x6ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@8
# AUNIT --inst x6ee04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x9 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_uqshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.378 UQSHL (register) page C7-2253 line 126700 MATCH x2e204c00/mask=xbf20fc00
# CONSTRUCT x2ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@4
# AUNIT --inst x2ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x9 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_uqshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.378 UQSHL (register) page C7-2253 line 126700 MATCH x2e204c00/mask=xbf20fc00
# CONSTRUCT x2e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@2
# AUNIT --inst x2e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x9 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_uqshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.378 UQSHL (register) page C7-2253 line 126700 MATCH x2e204c00/mask=xbf20fc00
# CONSTRUCT x6ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@4
# AUNIT --inst x6ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x9 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_uqshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.378 UQSHL (register) page C7-2253 line 126700 MATCH x2e204c00/mask=xbf20fc00
# CONSTRUCT x2e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@1
# AUNIT --inst x2e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x9 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_uqshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.378 UQSHL (register) page C7-2253 line 126700 MATCH x2e204c00/mask=xbf20fc00
# CONSTRUCT x6e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@2
# AUNIT --inst x6e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x9 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_uqshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.379 UQSHRN, UQSHRN2 page C7-2255 line 126838 MATCH x2f009400/mask=xbf80fc00
# CONSTRUCT x6f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn2/3@2
# AUNIT --inst x6f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
:uqshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_uqshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.379 UQSHRN, UQSHRN2 page C7-2255 line 126838 MATCH x2f009400/mask=xbf80fc00
# CONSTRUCT x2f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3@8
# AUNIT --inst x2f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_uqshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.379 UQSHRN, UQSHRN2 page C7-2255 line 126838 MATCH x2f009400/mask=xbf80fc00
# CONSTRUCT x2f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3@4
# AUNIT --inst x2f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
:uqshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_uqshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.379 UQSHRN, UQSHRN2 page C7-2255 line 126838 MATCH x2f009400/mask=xbf80fc00
# CONSTRUCT x6f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn2/3@8
# AUNIT --inst x6f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_uqshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
}
# C7.2.379 UQSHRN, UQSHRN2 page C7-2255 line 126838 MATCH x2f009400/mask=xbf80fc00
# CONSTRUCT x2f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3@2
# AUNIT --inst x2f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
:uqshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_uqshrn(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
}
# C7.2.379 UQSHRN, UQSHRN2 page C7-2255 line 126838 MATCH x2f009400/mask=xbf80fc00
# CONSTRUCT x6f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn2/3@4
# AUNIT --inst x6f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
:uqshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_uqshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
}
# C7.2.379 UQSHRN, UQSHRN2 page C7-2255 line 126838 MATCH x7f009400/mask=xff80fc00
# CONSTRUCT x7f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3
# AUNIT --inst x7f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
:uqshrn Rd_FPR8, Rn_FPR16, Imm_shr_imm8
is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100101 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd
{
Rd_FPR8 = NEON_uqshrn(Rd_FPR8, Rn_FPR16, Imm_shr_imm8:1);
}
# C7.2.379 UQSHRN, UQSHRN2 page C7-2255 line 126838 MATCH x7f009400/mask=xff80fc00
# CONSTRUCT x7f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3
# AUNIT --inst x7f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
:uqshrn Rd_FPR16, Rn_FPR32, Imm_shr_imm16
is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100101 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd
{
Rd_FPR16 = NEON_uqshrn(Rd_FPR16, Rn_FPR32, Imm_shr_imm16:1);
}
# C7.2.379 UQSHRN, UQSHRN2 page C7-2255 line 126838 MATCH x7f009400/mask=xff80fc00
# CONSTRUCT x7f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3
# AUNIT --inst x7f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
:uqshrn Rd_FPR32, Rn_FPR64, Imm_shr_imm32
is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100101 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd
{
Rd_FPR32 = NEON_uqshrn(Rd_FPR32, Rn_FPR64, Imm_shr_imm32:1);
}
# C7.2.380 UQSUB page C7-2258 line 127023 MATCH x7e202c00/mask=xff20fc00
# CONSTRUCT x7e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2
# AUNIT --inst x7e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqsub Rd_FPR8, Rn_FPR8, Rm_FPR8
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x5 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
{
Rd_FPR8 = NEON_uqsub(Rn_FPR8, Rm_FPR8);
}
# C7.2.380 UQSUB page C7-2258 line 127023 MATCH x7e202c00/mask=xff20fc00
# CONSTRUCT x7ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2
# AUNIT --inst x7ee02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqsub Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x5 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_uqsub(Rn_FPR64, Rm_FPR64);
}
# C7.2.380 UQSUB page C7-2258 line 127023 MATCH x7e202c00/mask=xff20fc00
# CONSTRUCT x7e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2
# AUNIT --inst x7e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqsub Rd_FPR16, Rn_FPR16, Rm_FPR16
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x5 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
{
Rd_FPR16 = NEON_uqsub(Rn_FPR16, Rm_FPR16);
}
# C7.2.380 UQSUB page C7-2258 line 127023 MATCH x7e202c00/mask=xff20fc00
# CONSTRUCT x7ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2
# AUNIT --inst x7ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqsub Rd_FPR32, Rn_FPR32, Rm_FPR32
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x5 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
{
Rd_FPR32 = NEON_uqsub(Rn_FPR32, Rm_FPR32);
}
# C7.2.380 UQSUB page C7-2258 line 127023 MATCH x2e202c00/mask=xbf20fc00
# CONSTRUCT x6e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@1
# AUNIT --inst x6e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x5 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_uqsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.380 UQSUB page C7-2258 line 127023 MATCH x2e202c00/mask=xbf20fc00
# CONSTRUCT x6ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@8
# AUNIT --inst x6ee02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqsub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x5 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_uqsub(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.380 UQSUB page C7-2258 line 127023 MATCH x2e202c00/mask=xbf20fc00
# CONSTRUCT x2ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@4
# AUNIT --inst x2ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x5 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_uqsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.380 UQSUB page C7-2258 line 127023 MATCH x2e202c00/mask=xbf20fc00
# CONSTRUCT x2e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@2
# AUNIT --inst x2e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x5 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_uqsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.380 UQSUB page C7-2258 line 127023 MATCH x2e202c00/mask=xbf20fc00
# CONSTRUCT x6ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@4
# AUNIT --inst x6ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x5 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_uqsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.380 UQSUB page C7-2258 line 127023 MATCH x2e202c00/mask=xbf20fc00
# CONSTRUCT x2e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@1
# AUNIT --inst x2e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x5 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_uqsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.380 UQSUB page C7-2258 line 127023 MATCH x2e202c00/mask=xbf20fc00
# CONSTRUCT x6e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@2
# AUNIT --inst x6e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
:uqsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x5 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_uqsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.381 UQXTN, UQXTN2 page C7-2260 line 127148 MATCH x7e214800/mask=xff3ffc00
# CONSTRUCT x7e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2
# AUNIT --inst x7e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Scalar variant when size=00 Q=1 bb=1 mnemonic=uqxtn Ta=FPR16 Tb=FPR8
:uqxtn Rd_FPR8, Rn_FPR16
is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100001010010 & Rd_FPR8 & Rn_FPR16 & Zd
{
Rd_FPR8 = NEON_uqxtn(Rd_FPR8, Rn_FPR16);
}
# C7.2.381 UQXTN, UQXTN2 page C7-2260 line 127148 MATCH x7e214800/mask=xff3ffc00
# CONSTRUCT x7e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2
# AUNIT --inst x7e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Scalar variant when size=01 Q=1 bb=1 mnemonic=uqxtn Ta=FPR32 Tb=FPR16
:uqxtn Rd_FPR16, Rn_FPR32
is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100001010010 & Rd_FPR16 & Rn_FPR32 & Zd
{
Rd_FPR16 = NEON_uqxtn(Rd_FPR16, Rn_FPR32);
}
# C7.2.381 UQXTN, UQXTN2 page C7-2260 line 127148 MATCH x7e214800/mask=xff3ffc00
# CONSTRUCT x7ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2
# AUNIT --inst x7ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Scalar variant when size=10 Q=1 bb=1 mnemonic=uqxtn Ta=FPR64 Tb=FPR32
:uqxtn Rd_FPR32, Rn_FPR64
is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100001010010 & Rd_FPR32 & Rn_FPR64 & Zd
{
Rd_FPR32 = NEON_uqxtn(Rd_FPR32, Rn_FPR64);
}
# C7.2.381 UQXTN, UQXTN2 page C7-2260 line 127148 MATCH x2e214800/mask=xbf3ffc00
# CONSTRUCT x2e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2@2
# AUNIT --inst x2e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=00 Q=0 bb=0 mnemonic=uqxtn e=2 Ta=VPR128.8H Tb=VPR64.8B
:uqxtn Rd_VPR64.8B, Rn_VPR128.8H
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001010010 & Rd_VPR64.8B & Rn_VPR128.8H & Zd
{
Rd_VPR64.8B = NEON_uqxtn(Rd_VPR64.8B, Rn_VPR128.8H, 2:1);
}
# C7.2.381 UQXTN, UQXTN2 page C7-2260 line 127148 MATCH x2e214800/mask=xbf3ffc00
# CONSTRUCT x6e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn2/2@2
# AUNIT --inst x6e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=00 Q=1 bb=0 mnemonic=uqxtn2 e=2 Ta=VPR128.8H Tb=VPR128.16B
:uqxtn2 Rd_VPR128.16B, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001010010 & Rd_VPR128.16B & Rn_VPR128.8H & Zd
{
Rd_VPR128.16B = NEON_uqxtn2(Rd_VPR128.16B, Rn_VPR128.8H, 2:1);
}
# C7.2.381 UQXTN, UQXTN2 page C7-2260 line 127148 MATCH x2e214800/mask=xbf3ffc00
# CONSTRUCT x2e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2@4
# AUNIT --inst x2e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=01 Q=0 bb=0 mnemonic=uqxtn e=4 Ta=VPR128.4S Tb=VPR64.4H
:uqxtn Rd_VPR64.4H, Rn_VPR128.4S
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001010010 & Rd_VPR64.4H & Rn_VPR128.4S & Zd
{
Rd_VPR64.4H = NEON_uqxtn(Rd_VPR64.4H, Rn_VPR128.4S, 4:1);
}
# C7.2.381 UQXTN, UQXTN2 page C7-2260 line 127148 MATCH x2e214800/mask=xbf3ffc00
# CONSTRUCT x6e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn2/2@4
# AUNIT --inst x6e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=01 Q=1 bb=0 mnemonic=uqxtn2 e=4 Ta=VPR128.4S Tb=VPR128.8H
:uqxtn2 Rd_VPR128.8H, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001010010 & Rd_VPR128.8H & Rn_VPR128.4S & Zd
{
Rd_VPR128.8H = NEON_uqxtn2(Rd_VPR128.8H, Rn_VPR128.4S, 4:1);
}
# C7.2.381 UQXTN, UQXTN2 page C7-2260 line 127148 MATCH x2e214800/mask=xbf3ffc00
# CONSTRUCT x2ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2@8
# AUNIT --inst x2ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=10 Q=0 bb=0 mnemonic=uqxtn e=8 Ta=VPR128.2D Tb=VPR64.2S
:uqxtn Rd_VPR64.2S, Rn_VPR128.2D
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001010010 & Rd_VPR64.2S & Rn_VPR128.2D & Zd
{
Rd_VPR64.2S = NEON_uqxtn(Rd_VPR64.2S, Rn_VPR128.2D, 8:1);
}
# C7.2.381 UQXTN, UQXTN2 page C7-2260 line 127148 MATCH x2e214800/mask=xbf3ffc00
# CONSTRUCT x6ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn2/2@8
# AUNIT --inst x6ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=10 Q=1 bb=0 mnemonic=uqxtn2 e=8 Ta=VPR128.2D Tb=VPR128.4S
:uqxtn2 Rd_VPR128.4S, Rn_VPR128.2D
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001010010 & Rd_VPR128.4S & Rn_VPR128.2D & Zd
{
Rd_VPR128.4S = NEON_uqxtn2(Rd_VPR128.4S, Rn_VPR128.2D, 8:1);
}
# C7.2.382 URECPE page C7-2263 line 127300 MATCH x0ea1c800/mask=xbfbffc00
# CONSTRUCT x0ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_urecpe/1@4
# AUNIT --inst x0ea1c800/mask=xfffffc00 --status nopcodeop
# Vector variant when Q=0 T=VPR64.2S
:urecpe Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_urecpe(Rn_VPR64.2S, 4:1);
}
# C7.2.382 URECPE page C7-2263 line 127300 MATCH x0ea1c800/mask=xbfbffc00
# CONSTRUCT x4ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_urecpe/1@4
# AUNIT --inst x4ea1c800/mask=xfffffc00 --status nopcodeop
# Vector variant when Q=1 T=VPR128.4S
:urecpe Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_urecpe(Rn_VPR128.4S, 4:1);
}
# C7.2.383 URHADD page C7-2264 line 127365 MATCH x2e201400/mask=xbf20fc00
# CONSTRUCT x6e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@1
# AUNIT --inst x6e201400/mask=xffe0fc00 --status nopcodeop
:urhadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_urhadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.383 URHADD page C7-2264 line 127365 MATCH x2e201400/mask=xbf20fc00
# CONSTRUCT x2ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@2
# AUNIT --inst x2ea01400/mask=xffe0fc00 --status nopcodeop
:urhadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_urhadd(Rn_VPR64.2S, Rm_VPR64.2S, 2:1);
}
# C7.2.383 URHADD page C7-2264 line 127365 MATCH x2e201400/mask=xbf20fc00
# CONSTRUCT x2e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@2
# AUNIT --inst x2e601400/mask=xffe0fc00 --status nopcodeop
:urhadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_urhadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.383 URHADD page C7-2264 line 127365 MATCH x2e201400/mask=xbf20fc00
# CONSTRUCT x6ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@4
# AUNIT --inst x6ea01400/mask=xffe0fc00 --status nopcodeop
:urhadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_urhadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.383 URHADD page C7-2264 line 127365 MATCH x2e201400/mask=xbf20fc00
# CONSTRUCT x2e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@1
# AUNIT --inst x2e201400/mask=xffe0fc00 --status nopcodeop
:urhadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_urhadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.383 URHADD page C7-2264 line 127365 MATCH x2e201400/mask=xbf20fc00
# CONSTRUCT x6e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@2
# AUNIT --inst x6e601400/mask=xffe0fc00 --status nopcodeop
:urhadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_urhadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.384 URSHL page C7-2266 line 127452 MATCH x7e205400/mask=xff20fc00
# CONSTRUCT x7ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2
# AUNIT --inst x7ee05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:urshl Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xa & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_urshl(Rn_FPR64, Rm_FPR64);
}
# C7.2.384 URSHL page C7-2266 line 127452 MATCH x2e205400/mask=xbf20fc00
# CONSTRUCT x6e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@1
# AUNIT --inst x6e205400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:urshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_urshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.384 URSHL page C7-2266 line 127452 MATCH x2e205400/mask=xbf20fc00
# CONSTRUCT x6ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@8
# AUNIT --inst x6ee05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:urshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_urshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.384 URSHL page C7-2266 line 127452 MATCH x2e205400/mask=xbf20fc00
# CONSTRUCT x2ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@4
# AUNIT --inst x2ea05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:urshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_urshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.384 URSHL page C7-2266 line 127452 MATCH x2e205400/mask=xbf20fc00
# CONSTRUCT x2e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@2
# AUNIT --inst x2e605400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:urshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_urshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.384 URSHL page C7-2266 line 127452 MATCH x2e205400/mask=xbf20fc00
# CONSTRUCT x6ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@4
# AUNIT --inst x6ea05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:urshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_urshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.384 URSHL page C7-2266 line 127452 MATCH x2e205400/mask=xbf20fc00
# CONSTRUCT x2e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@1
# AUNIT --inst x2e205400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:urshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_urshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.384 URSHL page C7-2266 line 127452 MATCH x2e205400/mask=xbf20fc00
# CONSTRUCT x6e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@2
# AUNIT --inst x6e605400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:urshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_urshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.385 URSHR page C7-2268 line 127587 MATCH x2f002400/mask=xbf80fc00
# CONSTRUCT x6f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@1
# AUNIT --inst x6f082400/mask=xfff8fc00 --status nopcodeop --comment "nointround"
:urshr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_urshr(Rn_VPR128.16B, Imm_shr_imm8:1, 1:1);
}
# C7.2.385 URSHR page C7-2268 line 127587 MATCH x2f002400/mask=xbf80fc00
# CONSTRUCT x6f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@8
# AUNIT --inst x6f402400/mask=xffc0fc00 --status nopcodeop --comment "nointround"
:urshr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x4 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_urshr(Rn_VPR128.2D, Imm_shr_imm64:1, 8:1);
}
# C7.2.385 URSHR page C7-2268 line 127587 MATCH x2f002400/mask=xbf80fc00
# CONSTRUCT x2f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@4
# AUNIT --inst x2f202400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:urshr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_urshr(Rn_VPR64.2S, Imm_shr_imm32:1, 4:1);
}
# C7.2.385 URSHR page C7-2268 line 127587 MATCH x2f002400/mask=xbf80fc00
# CONSTRUCT x2f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@2
# AUNIT --inst x2f102400/mask=xfff0fc00 --status nopcodeop --comment "nointround"
:urshr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_urshr(Rn_VPR64.4H, Imm_shr_imm16:1, 2:1);
}
# C7.2.385 URSHR page C7-2268 line 127587 MATCH x2f002400/mask=xbf80fc00
# CONSTRUCT x6f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@4
# AUNIT --inst x6f202400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
:urshr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_urshr(Rn_VPR128.4S, Imm_shr_imm32:1, 4:1);
}
# C7.2.385 URSHR page C7-2268 line 127587 MATCH x2f002400/mask=xbf80fc00
# CONSTRUCT x2f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@1
# AUNIT --inst x2f082400/mask=xfff8fc00 --status nopcodeop --comment "nointround"
:urshr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_urshr(Rn_VPR64.8B, Imm_shr_imm8:1, 1:1);
}
# C7.2.385 URSHR page C7-2268 line 127587 MATCH x2f002400/mask=xbf80fc00
# CONSTRUCT x6f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@2
# AUNIT --inst x6f102400/mask=xfff0fc00 --status nopcodeop --comment "nointround"
:urshr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_urshr(Rn_VPR128.8H, Imm_shr_imm16:1, 2:1);
}
# C7.2.385 URSHR page C7-2268 line 127587 MATCH x7f002400/mask=xff80fc00
# CONSTRUCT x7f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2
# AUNIT --inst x7f402400/mask=xffc0fc00 --status nopcodeop --comment "nointround"
# Scalar variant
:urshr Rd_FPR64, Rn_FPR64, Imm_shr_imm32
is b_2331=0b011111110 & b_22=1 & b_1015=0b001001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm32 & Zd
{
Rd_FPR64 = NEON_urshr(Rn_FPR64, Imm_shr_imm32:1);
}
# C7.2.386 URSQRTE page C7-2270 line 127723 MATCH x2ea1c800/mask=xbfbffc00
# CONSTRUCT x2ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_ursqrte/1@4
# AUNIT --inst x2ea1c800/mask=xfffffc00 --status nopcodeop
# Vector variant when Q=0 T=VPR64.2S
:ursqrte Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_ursqrte(Rn_VPR64.2S, 4:1);
}
# C7.2.386 URSQRTE page C7-2270 line 127723 MATCH x2ea1c800/mask=xbfbffc00
# CONSTRUCT x6ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 =NEON_ursqrte/1@4
# AUNIT --inst x6ea1c800/mask=xfffffc00 --status nopcodeop
# Vector variant when Q=0 T=VPR128.4S
:ursqrte Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_ursqrte(Rn_VPR128.4S, 4:1);
}
# C7.2.387 URSRA page C7-2271 line 127788 MATCH x2f003400/mask=xbf80fc00
# CONSTRUCT x6f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@1
# AUNIT --inst x6f083400/mask=xfff8fc00 --status fail --comment "nointround"
:ursra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix TMPQ1 = Rn_VPR128.16B >> Imm_shr_imm8:1 on lane size 1
TMPQ1[0,8] = Rn_VPR128.16B[0,8] >> Imm_shr_imm8:1;
TMPQ1[8,8] = Rn_VPR128.16B[8,8] >> Imm_shr_imm8:1;
TMPQ1[16,8] = Rn_VPR128.16B[16,8] >> Imm_shr_imm8:1;
TMPQ1[24,8] = Rn_VPR128.16B[24,8] >> Imm_shr_imm8:1;
TMPQ1[32,8] = Rn_VPR128.16B[32,8] >> Imm_shr_imm8:1;
TMPQ1[40,8] = Rn_VPR128.16B[40,8] >> Imm_shr_imm8:1;
TMPQ1[48,8] = Rn_VPR128.16B[48,8] >> Imm_shr_imm8:1;
TMPQ1[56,8] = Rn_VPR128.16B[56,8] >> Imm_shr_imm8:1;
TMPQ1[64,8] = Rn_VPR128.16B[64,8] >> Imm_shr_imm8:1;
TMPQ1[72,8] = Rn_VPR128.16B[72,8] >> Imm_shr_imm8:1;
TMPQ1[80,8] = Rn_VPR128.16B[80,8] >> Imm_shr_imm8:1;
TMPQ1[88,8] = Rn_VPR128.16B[88,8] >> Imm_shr_imm8:1;
TMPQ1[96,8] = Rn_VPR128.16B[96,8] >> Imm_shr_imm8:1;
TMPQ1[104,8] = Rn_VPR128.16B[104,8] >> Imm_shr_imm8:1;
TMPQ1[112,8] = Rn_VPR128.16B[112,8] >> Imm_shr_imm8:1;
TMPQ1[120,8] = Rn_VPR128.16B[120,8] >> Imm_shr_imm8:1;
# simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1
Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];
Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];
Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];
Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];
Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];
Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];
Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];
Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];
Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];
Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];
Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];
Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];
Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];
Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];
Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];
Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.387 URSRA page C7-2271 line 127788 MATCH x2f003400/mask=xbf80fc00
# CONSTRUCT x6f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@8
# AUNIT --inst x6f403400/mask=xffc0fc00 --status fail --comment "nointround"
:ursra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
# simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1;
TMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.387 URSRA page C7-2271 line 127788 MATCH x2f003400/mask=xbf80fc00
# CONSTRUCT x2f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@4
# AUNIT --inst x2f203400/mask=xffe0fc00 --status fail --comment "nointround"
:ursra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
local tmp1:4 = Imm_shr_imm32;
# simd infix TMPD1 = Rn_VPR64.2S >> tmp1 on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] >> tmp1;
TMPD1[32,32] = Rn_VPR64.2S[32,32] >> tmp1;
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.387 URSRA page C7-2271 line 127788 MATCH x2f003400/mask=xbf80fc00
# CONSTRUCT x2f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@2
# AUNIT --inst x2f103400/mask=xfff0fc00 --status fail --comment "nointround"
:ursra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd infix TMPD1 = Rn_VPR64.4H >> Imm_shr_imm16:2 on lane size 2
TMPD1[0,16] = Rn_VPR64.4H[0,16] >> Imm_shr_imm16:2;
TMPD1[16,16] = Rn_VPR64.4H[16,16] >> Imm_shr_imm16:2;
TMPD1[32,16] = Rn_VPR64.4H[32,16] >> Imm_shr_imm16:2;
TMPD1[48,16] = Rn_VPR64.4H[48,16] >> Imm_shr_imm16:2;
# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 4
Rd_VPR64.4H[0,32] = Rd_VPR64.4H[0,32] + TMPD1[0,32];
Rd_VPR64.4H[32,32] = Rd_VPR64.4H[32,32] + TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.387 URSRA page C7-2271 line 127788 MATCH x2f003400/mask=xbf80fc00
# CONSTRUCT x6f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@4
# AUNIT --inst x6f203400/mask=xffe0fc00 --status fail --comment "nointround"
:ursra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
local tmp1:4 = Imm_shr_imm32;
# simd infix TMPQ1 = Rn_VPR128.4S >> tmp1 on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] >> tmp1;
TMPQ1[32,32] = Rn_VPR128.4S[32,32] >> tmp1;
TMPQ1[64,32] = Rn_VPR128.4S[64,32] >> tmp1;
TMPQ1[96,32] = Rn_VPR128.4S[96,32] >> tmp1;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.387 URSRA page C7-2271 line 127788 MATCH x2f003400/mask=xbf80fc00
# CONSTRUCT x2f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@1
# AUNIT --inst x2f083400/mask=xfff8fc00 --status fail --comment "nointround"
:ursra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix TMPD1 = Rn_VPR64.8B >> Imm_shr_imm8:1 on lane size 1
TMPD1[0,8] = Rn_VPR64.8B[0,8] >> Imm_shr_imm8:1;
TMPD1[8,8] = Rn_VPR64.8B[8,8] >> Imm_shr_imm8:1;
TMPD1[16,8] = Rn_VPR64.8B[16,8] >> Imm_shr_imm8:1;
TMPD1[24,8] = Rn_VPR64.8B[24,8] >> Imm_shr_imm8:1;
TMPD1[32,8] = Rn_VPR64.8B[32,8] >> Imm_shr_imm8:1;
TMPD1[40,8] = Rn_VPR64.8B[40,8] >> Imm_shr_imm8:1;
TMPD1[48,8] = Rn_VPR64.8B[48,8] >> Imm_shr_imm8:1;
TMPD1[56,8] = Rn_VPR64.8B[56,8] >> Imm_shr_imm8:1;
# simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1
Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];
Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];
Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];
Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];
Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];
Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];
Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];
Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.387 URSRA page C7-2271 line 127788 MATCH x2f003400/mask=xbf80fc00
# CONSTRUCT x6f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@2
# AUNIT --inst x6f103400/mask=xfff0fc00 --status fail --comment "nointround"
:ursra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm16:2 on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm16:2;
TMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm16:2;
TMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm16:2;
TMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm16:2;
TMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm16:2;
TMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm16:2;
TMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm16:2;
TMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm16:2;
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.387 URSRA page C7-2271 line 127788 MATCH x7f003400/mask=xff80fc00
# CONSTRUCT x7f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 >> &=+
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3
# AUNIT --inst x7f403400/mask=xffc0fc00 --status fail --comment "nointround"
# Scalar variant when immh=1xxx
:ursra Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_2331=0b011111110 & b_22=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
local tmp2:8 = Rn_FPR64 >> tmp1;
Rd_FPR64 = Rd_FPR64 + tmp2;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.390 USHL page C7-2277 line 128100 MATCH x7e204400/mask=xff20fc00
# CONSTRUCT x7ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2
# AUNIT --inst x7ee04400/mask=xffe0fc00 --status nopcodeop
:ushl Rd_FPR64, Rn_FPR64, Rm_FPR64
is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x8 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
{
Rd_FPR64 = NEON_ushl(Rn_FPR64, Rm_FPR64);
}
# C7.2.390 USHL page C7-2277 line 128100 MATCH x2e204400/mask=xbf20fc00
# CONSTRUCT x6e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@1
# AUNIT --inst x6e204400/mask=xffe0fc00 --status nopcodeop
:ushl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x8 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_ushl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.390 USHL page C7-2277 line 128100 MATCH x2e204400/mask=xbf20fc00
# CONSTRUCT x6ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@8
# AUNIT --inst x6ee04400/mask=xffe0fc00 --status nopcodeop
:ushl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x8 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_ushl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
}
# C7.2.390 USHL page C7-2277 line 128100 MATCH x2e204400/mask=xbf20fc00
# CONSTRUCT x2ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@4
# AUNIT --inst x2ea04400/mask=xffe0fc00 --status nopcodeop
:ushl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x8 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_ushl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
}
# C7.2.390 USHL page C7-2277 line 128100 MATCH x2e204400/mask=xbf20fc00
# CONSTRUCT x2e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@2
# AUNIT --inst x2e604400/mask=xffe0fc00 --status nopcodeop
:ushl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x8 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_ushl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
}
# C7.2.390 USHL page C7-2277 line 128100 MATCH x2e204400/mask=xbf20fc00
# CONSTRUCT x6ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@4
# AUNIT --inst x6ea04400/mask=xffe0fc00 --status nopcodeop
:ushl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x8 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_ushl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
}
# C7.2.390 USHL page C7-2277 line 128100 MATCH x2e204400/mask=xbf20fc00
# CONSTRUCT x2e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@1
# AUNIT --inst x2e204400/mask=xffe0fc00 --status nopcodeop
:ushl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x8 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_ushl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
}
# C7.2.390 USHL page C7-2277 line 128100 MATCH x2e204400/mask=xbf20fc00
# CONSTRUCT x6e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@2
# AUNIT --inst x6e604400/mask=xffe0fc00 --status nopcodeop
:ushl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x8 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_ushl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
}
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# CONSTRUCT x6f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3 =var:2 =$<<@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll2/2@1
# AUNIT --inst x6f08a400/mask=xfff8fc00 --status pass --comment "ext"
:ushll2 Rd_VPR128.8H, Rn_VPR128.16B, Imm_uimm3
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = zext(TMPD1[0,8]);
TMPQ2[16,16] = zext(TMPD1[8,8]);
TMPQ2[32,16] = zext(TMPD1[16,8]);
TMPQ2[48,16] = zext(TMPD1[24,8]);
TMPQ2[64,16] = zext(TMPD1[32,8]);
TMPQ2[80,16] = zext(TMPD1[40,8]);
TMPQ2[96,16] = zext(TMPD1[48,8]);
TMPQ2[112,16] = zext(TMPD1[56,8]);
local tmp3:2 = Imm_uimm3;
# simd infix Rd_VPR128.8H = TMPQ2 << tmp3 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ2[0,16] << tmp3;
Rd_VPR128.8H[16,16] = TMPQ2[16,16] << tmp3;
Rd_VPR128.8H[32,16] = TMPQ2[32,16] << tmp3;
Rd_VPR128.8H[48,16] = TMPQ2[48,16] << tmp3;
Rd_VPR128.8H[64,16] = TMPQ2[64,16] << tmp3;
Rd_VPR128.8H[80,16] = TMPQ2[80,16] << tmp3;
Rd_VPR128.8H[96,16] = TMPQ2[96,16] << tmp3;
Rd_VPR128.8H[112,16] = TMPQ2[112,16] << tmp3;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# CONSTRUCT x2f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@4:16 ARG3 =var:8 =$<<@8
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll/2@4
# AUNIT --inst x2f20a400/mask=xffe0fc00 --status pass --comment "ext"
:ushll Rd_VPR128.2D, Rn_VPR64.2S, Imm_uimm5
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
local tmp2:8 = Imm_uimm5;
# simd infix Rd_VPR128.2D = TMPQ1 << tmp2 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64] << tmp2;
Rd_VPR128.2D[64,64] = TMPQ1[64,64] << tmp2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# CONSTRUCT x2f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@2:16 ARG3 =var:4 =$<<@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll/2@2
# AUNIT --inst x2f10a400/mask=xfff0fc00 --status pass --comment "ext"
:ushll Rd_VPR128.4S, Rn_VPR64.4H, Imm_uimm4
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
local tmp2:4 = Imm_uimm4;
# simd infix Rd_VPR128.4S = TMPQ1 << tmp2 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32] << tmp2;
Rd_VPR128.4S[32,32] = TMPQ1[32,32] << tmp2;
Rd_VPR128.4S[64,32] = TMPQ1[64,32] << tmp2;
Rd_VPR128.4S[96,32] = TMPQ1[96,32] << tmp2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# CONSTRUCT x6f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 =var:8 =$<<@8
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll2/2@4
# AUNIT --inst x6f20a400/mask=xffe0fc00 --status pass --comment "ext"
:ushll2 Rd_VPR128.2D, Rn_VPR128.4S, Imm_uimm5
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
local tmp3:8 = Imm_uimm5;
# simd infix Rd_VPR128.2D = TMPQ2 << tmp3 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ2[0,64] << tmp3;
Rd_VPR128.2D[64,64] = TMPQ2[64,64] << tmp3;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# CONSTRUCT x2f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@1:16 ARG3 =var:2 =$<<@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll/2@1
# AUNIT --inst x2f08a400/mask=xfff8fc00 --status pass --comment "ext"
:ushll Rd_VPR128.8H, Rn_VPR64.8B, Imm_uimm3
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
local tmp2:2 = Imm_uimm3;
# simd infix Rd_VPR128.8H = TMPQ1 << tmp2 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[0,16] << tmp2;
Rd_VPR128.8H[16,16] = TMPQ1[16,16] << tmp2;
Rd_VPR128.8H[32,16] = TMPQ1[32,16] << tmp2;
Rd_VPR128.8H[48,16] = TMPQ1[48,16] << tmp2;
Rd_VPR128.8H[64,16] = TMPQ1[64,16] << tmp2;
Rd_VPR128.8H[80,16] = TMPQ1[80,16] << tmp2;
Rd_VPR128.8H[96,16] = TMPQ1[96,16] << tmp2;
Rd_VPR128.8H[112,16] = TMPQ1[112,16] << tmp2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# CONSTRUCT x6f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 =var:4 =$<<@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll2/2@2
# AUNIT --inst x6f10a400/mask=xfff0fc00 --status pass --comment "ext"
:ushll2 Rd_VPR128.4S, Rn_VPR128.8H, Imm_uimm4
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
local tmp3:4 = Imm_uimm4;
# simd infix Rd_VPR128.4S = TMPQ2 << tmp3 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ2[0,32] << tmp3;
Rd_VPR128.4S[32,32] = TMPQ2[32,32] << tmp3;
Rd_VPR128.4S[64,32] = TMPQ2[64,32] << tmp3;
Rd_VPR128.4S[96,32] = TMPQ2[96,32] << tmp3;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.392 USHR page C7-2282 line 128386 MATCH x2f000400/mask=xbf80fc00
# CONSTRUCT x6f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:1 =$>>@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@1
# AUNIT --inst x6f080400/mask=xfff8fc00 --status pass
:ushr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix Rd_VPR128.16B = Rn_VPR128.16B >> Imm_shr_imm8:1 on lane size 1
Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] >> Imm_shr_imm8:1;
Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] >> Imm_shr_imm8:1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.392 USHR page C7-2282 line 128386 MATCH x2f000400/mask=xbf80fc00
# CONSTRUCT x6f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 =$>>@8
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@8
# AUNIT --inst x6f400400/mask=xffc0fc00 --status pass
:ushr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x0 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
# simd infix Rd_VPR128.2D = Rn_VPR128.2D >> tmp1 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] >> tmp1;
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] >> tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.392 USHR page C7-2282 line 128386 MATCH x2f000400/mask=xbf80fc00
# CONSTRUCT x2f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:4 =$>>@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@4
# AUNIT --inst x2f200400/mask=xffe0fc00 --status pass
:ushr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
local tmp1:4 = Imm_shr_imm32;
# simd infix Rd_VPR64.2S = Rn_VPR64.2S >> tmp1 on lane size 4
Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] >> tmp1;
Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] >> tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.392 USHR page C7-2282 line 128386 MATCH x2f000400/mask=xbf80fc00
# CONSTRUCT x2f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 =$>>@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@2
# AUNIT --inst x2f100400/mask=xfff0fc00 --status pass
:ushr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd infix Rd_VPR64.4H = Rn_VPR64.4H >> Imm_shr_imm16:2 on lane size 2
Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] >> Imm_shr_imm16:2;
Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] >> Imm_shr_imm16:2;
Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] >> Imm_shr_imm16:2;
Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] >> Imm_shr_imm16:2;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.392 USHR page C7-2282 line 128386 MATCH x2f000400/mask=xbf80fc00
# CONSTRUCT x6f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:4 =$>>@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@4
# AUNIT --inst x6f200400/mask=xffe0fc00 --status pass
:ushr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
local tmp1:4 = Imm_shr_imm32;
# simd infix Rd_VPR128.4S = Rn_VPR128.4S >> tmp1 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] >> tmp1;
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] >> tmp1;
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] >> tmp1;
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] >> tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.392 USHR page C7-2282 line 128386 MATCH x2f000400/mask=xbf80fc00
# CONSTRUCT x2f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:1 =$>>@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@1
# AUNIT --inst x2f080400/mask=xfff8fc00 --status pass
:ushr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix Rd_VPR64.8B = Rn_VPR64.8B >> Imm_shr_imm8:1 on lane size 1
Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] >> Imm_shr_imm8:1;
Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] >> Imm_shr_imm8:1;
Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] >> Imm_shr_imm8:1;
Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] >> Imm_shr_imm8:1;
Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] >> Imm_shr_imm8:1;
Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] >> Imm_shr_imm8:1;
Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] >> Imm_shr_imm8:1;
Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] >> Imm_shr_imm8:1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.392 USHR page C7-2282 line 128386 MATCH x2f000400/mask=xbf80fc00
# CONSTRUCT x6f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 =$>>@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@2
# AUNIT --inst x6f100400/mask=xfff0fc00 --status pass
:ushr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd infix Rd_VPR128.8H = Rn_VPR128.8H >> Imm_shr_imm16:2 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm16:2;
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm16:2;
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm16:2;
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm16:2;
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm16:2;
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm16:2;
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm16:2;
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm16:2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.392 USHR page C7-2282 line 128386 MATCH x7f000400/mask=xff80fc00
# CONSTRUCT x7f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 =>>
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2
# AUNIT --inst x7f400400/mask=xffc0fc00 --status pass
# Scalar variant when immh=1xxx
:ushr Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_2331=0b011111110 & b_22=1 & b_1015=0b000001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
Rd_FPR64 = Rn_FPR64 >> tmp1;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.394 USQADD page C7-2286 line 128601 MATCH x7e203800/mask=xff3ffc00
# CONSTRUCT x7e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2
# AUNIT --inst x7e203800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Scalar variant when size=00 Q=1 bb=1 T=FPR8
:usqadd Rd_FPR8, Rn_FPR8
is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_FPR8 & Rn_FPR8 & Zd
{
Rd_FPR8 = NEON_usqadd(Rd_FPR8, Rn_FPR8);
}
# C7.2.394 USQADD page C7-2286 line 128601 MATCH x7e203800/mask=xff3ffc00
# CONSTRUCT x7e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2
# AUNIT --inst x7e603800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Scalar variant when size=01 Q=1 bb=1 T=FPR16
:usqadd Rd_FPR16, Rn_FPR16
is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_FPR16 & Rn_FPR16 & Zd
{
Rd_FPR16 = NEON_usqadd(Rd_FPR16, Rn_FPR16);
}
# C7.2.394 USQADD page C7-2286 line 128601 MATCH x7e203800/mask=xff3ffc00
# CONSTRUCT x7ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2
# AUNIT --inst x7ea03800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Scalar variant when size=10 Q=1 bb=1 T=FPR32
:usqadd Rd_FPR32, Rn_FPR32
is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_FPR32 & Rn_FPR32 & Zd
{
Rd_FPR32 = NEON_usqadd(Rd_FPR32, Rn_FPR32);
}
# C7.2.394 USQADD page C7-2286 line 128601 MATCH x7e203800/mask=xff3ffc00
# CONSTRUCT x7ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2
# AUNIT --inst x7ee03800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Scalar variant when size=11 Q=1 bb=1 T=FPR64
:usqadd Rd_FPR64, Rn_FPR64
is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_FPR64 & Rn_FPR64 & Zd
{
Rd_FPR64 = NEON_usqadd(Rd_FPR64, Rn_FPR64);
}
# C7.2.394 USQADD page C7-2286 line 128601 MATCH x2e203800/mask=xbf3ffc00
# CONSTRUCT x2e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@1
# AUNIT --inst x2e203800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=00 Q=0 bb=0 e=1 T=VPR64.8B
:usqadd Rd_VPR64.8B, Rn_VPR64.8B
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
{
Rd_VPR64.8B = NEON_usqadd(Rd_VPR64.8B, Rn_VPR64.8B, 1:1);
}
# C7.2.394 USQADD page C7-2286 line 128601 MATCH x2e203800/mask=xbf3ffc00
# CONSTRUCT x6e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@1
# AUNIT --inst x6e203800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=00 Q=1 bb=0 e=1 T=VPR128.16B
:usqadd Rd_VPR128.16B, Rn_VPR128.16B
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
{
Rd_VPR128.16B = NEON_usqadd(Rd_VPR128.16B, Rn_VPR128.16B, 1:1);
}
# C7.2.394 USQADD page C7-2286 line 128601 MATCH x2e203800/mask=xbf3ffc00
# CONSTRUCT x2e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@2
# AUNIT --inst x2e603800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=01 Q=0 bb=0 e=2 T=VPR64.4H
:usqadd Rd_VPR64.4H, Rn_VPR64.4H
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
{
Rd_VPR64.4H = NEON_usqadd(Rd_VPR64.4H, Rn_VPR64.4H, 2:1);
}
# C7.2.394 USQADD page C7-2286 line 128601 MATCH x2e203800/mask=xbf3ffc00
# CONSTRUCT x6e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@2
# AUNIT --inst x6e603800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=01 Q=1 bb=0 e=2 T=VPR128.8H
:usqadd Rd_VPR128.8H, Rn_VPR128.8H
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
{
Rd_VPR128.8H = NEON_usqadd(Rd_VPR128.8H, Rn_VPR128.8H, 2:1);
}
# C7.2.394 USQADD page C7-2286 line 128601 MATCH x2e203800/mask=xbf3ffc00
# CONSTRUCT x2ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@4
# AUNIT --inst x2ea03800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=10 Q=0 bb=0 e=4 T=VPR64.2S
:usqadd Rd_VPR64.2S, Rn_VPR64.2S
is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
{
Rd_VPR64.2S = NEON_usqadd(Rd_VPR64.2S, Rn_VPR64.2S, 4:1);
}
# C7.2.394 USQADD page C7-2286 line 128601 MATCH x2e203800/mask=xbf3ffc00
# CONSTRUCT x6ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@4
# AUNIT --inst x6ea03800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=10 Q=1 bb=0 e=4 T=VPR128.4S
:usqadd Rd_VPR128.4S, Rn_VPR128.4S
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
{
Rd_VPR128.4S = NEON_usqadd(Rd_VPR128.4S, Rn_VPR128.4S, 4:1);
}
# C7.2.394 USQADD page C7-2286 line 128601 MATCH x2e203800/mask=xbf3ffc00
# CONSTRUCT x6ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@8
# AUNIT --inst x6ee03800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
# Vector variant when size=11 Q=1 bb=0 e=8 T=VPR128.2D
:usqadd Rd_VPR128.2D, Rn_VPR128.2D
is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
{
Rd_VPR128.2D = NEON_usqadd(Rd_VPR128.2D, Rn_VPR128.2D, 8:1);
}
# C7.2.395 USRA page C7-2288 line 128723 MATCH x2f001400/mask=xbf80fc00
# CONSTRUCT x6f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@1
# AUNIT --inst x6f081400/mask=xfff8fc00 --status pass
:usra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
# simd infix TMPQ1 = Rn_VPR128.16B >> Imm_shr_imm8:1 on lane size 1
TMPQ1[0,8] = Rn_VPR128.16B[0,8] >> Imm_shr_imm8:1;
TMPQ1[8,8] = Rn_VPR128.16B[8,8] >> Imm_shr_imm8:1;
TMPQ1[16,8] = Rn_VPR128.16B[16,8] >> Imm_shr_imm8:1;
TMPQ1[24,8] = Rn_VPR128.16B[24,8] >> Imm_shr_imm8:1;
TMPQ1[32,8] = Rn_VPR128.16B[32,8] >> Imm_shr_imm8:1;
TMPQ1[40,8] = Rn_VPR128.16B[40,8] >> Imm_shr_imm8:1;
TMPQ1[48,8] = Rn_VPR128.16B[48,8] >> Imm_shr_imm8:1;
TMPQ1[56,8] = Rn_VPR128.16B[56,8] >> Imm_shr_imm8:1;
TMPQ1[64,8] = Rn_VPR128.16B[64,8] >> Imm_shr_imm8:1;
TMPQ1[72,8] = Rn_VPR128.16B[72,8] >> Imm_shr_imm8:1;
TMPQ1[80,8] = Rn_VPR128.16B[80,8] >> Imm_shr_imm8:1;
TMPQ1[88,8] = Rn_VPR128.16B[88,8] >> Imm_shr_imm8:1;
TMPQ1[96,8] = Rn_VPR128.16B[96,8] >> Imm_shr_imm8:1;
TMPQ1[104,8] = Rn_VPR128.16B[104,8] >> Imm_shr_imm8:1;
TMPQ1[112,8] = Rn_VPR128.16B[112,8] >> Imm_shr_imm8:1;
TMPQ1[120,8] = Rn_VPR128.16B[120,8] >> Imm_shr_imm8:1;
# simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1
Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];
Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];
Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];
Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];
Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];
Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];
Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];
Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];
Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];
Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];
Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];
Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];
Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];
Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];
Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];
Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.395 USRA page C7-2288 line 128723 MATCH x2f001400/mask=xbf80fc00
# CONSTRUCT x6f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 &=$+@8
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@8
# AUNIT --inst x6f401400/mask=xffc0fc00 --status pass
:usra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x2 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
# simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1;
TMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1;
# simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.395 USRA page C7-2288 line 128723 MATCH x2f001400/mask=xbf80fc00
# CONSTRUCT x2f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@4
# AUNIT --inst x2f201400/mask=xffe0fc00 --status pass
:usra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
local tmp1:4 = Imm_shr_imm32;
# simd infix TMPD1 = Rn_VPR64.2S >> tmp1 on lane size 4
TMPD1[0,32] = Rn_VPR64.2S[0,32] >> tmp1;
TMPD1[32,32] = Rn_VPR64.2S[32,32] >> tmp1;
# simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.395 USRA page C7-2288 line 128723 MATCH x2f001400/mask=xbf80fc00
# CONSTRUCT x2f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@2
# AUNIT --inst x2f101400/mask=xfff0fc00 --status pass
:usra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
# simd infix TMPD1 = Rn_VPR64.4H >> Imm_shr_imm16:2 on lane size 2
TMPD1[0,16] = Rn_VPR64.4H[0,16] >> Imm_shr_imm16:2;
TMPD1[16,16] = Rn_VPR64.4H[16,16] >> Imm_shr_imm16:2;
TMPD1[32,16] = Rn_VPR64.4H[32,16] >> Imm_shr_imm16:2;
TMPD1[48,16] = Rn_VPR64.4H[48,16] >> Imm_shr_imm16:2;
# simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.395 USRA page C7-2288 line 128723 MATCH x2f001400/mask=xbf80fc00
# CONSTRUCT x6f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@4
# AUNIT --inst x6f201400/mask=xffe0fc00 --status pass
:usra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
local tmp1:4 = Imm_shr_imm32;
# simd infix TMPQ1 = Rn_VPR128.4S >> tmp1 on lane size 4
TMPQ1[0,32] = Rn_VPR128.4S[0,32] >> tmp1;
TMPQ1[32,32] = Rn_VPR128.4S[32,32] >> tmp1;
TMPQ1[64,32] = Rn_VPR128.4S[64,32] >> tmp1;
TMPQ1[96,32] = Rn_VPR128.4S[96,32] >> tmp1;
# simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.395 USRA page C7-2288 line 128723 MATCH x2f001400/mask=xbf80fc00
# CONSTRUCT x2f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@1
# AUNIT --inst x2f081400/mask=xfff8fc00 --status pass
:usra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
# simd infix TMPD1 = Rn_VPR64.8B >> Imm_shr_imm8:1 on lane size 1
TMPD1[0,8] = Rn_VPR64.8B[0,8] >> Imm_shr_imm8:1;
TMPD1[8,8] = Rn_VPR64.8B[8,8] >> Imm_shr_imm8:1;
TMPD1[16,8] = Rn_VPR64.8B[16,8] >> Imm_shr_imm8:1;
TMPD1[24,8] = Rn_VPR64.8B[24,8] >> Imm_shr_imm8:1;
TMPD1[32,8] = Rn_VPR64.8B[32,8] >> Imm_shr_imm8:1;
TMPD1[40,8] = Rn_VPR64.8B[40,8] >> Imm_shr_imm8:1;
TMPD1[48,8] = Rn_VPR64.8B[48,8] >> Imm_shr_imm8:1;
TMPD1[56,8] = Rn_VPR64.8B[56,8] >> Imm_shr_imm8:1;
# simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1
Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];
Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];
Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];
Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];
Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];
Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];
Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];
Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.395 USRA page C7-2288 line 128723 MATCH x2f001400/mask=xbf80fc00
# CONSTRUCT x6f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@2
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@2
# AUNIT --inst x6f101400/mask=xfff0fc00 --status pass
:usra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm16:2 on lane size 2
TMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm16:2;
TMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm16:2;
TMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm16:2;
TMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm16:2;
TMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm16:2;
TMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm16:2;
TMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm16:2;
TMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm16:2;
# simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.395 USRA page C7-2288 line 128723 MATCH x7f001400/mask=xff80fc00
# CONSTRUCT x7f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 zext:8 >> &=+
# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3
# AUNIT --inst x7f401400/mask=xffc0fc00 --status pass
# Scalar variant when immh=1xxx
:usra Rd_FPR64, Rn_FPR64, Imm_shr_imm64
is b_2331=0b011111110 & b_22=1 & b_1015=0b000101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
{
local tmp1:8 = zext(Imm_shr_imm64);
local tmp2:8 = Rn_FPR64 >> tmp1;
Rd_FPR64 = Rd_FPR64 + tmp2;
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.396 USUBL, USUBL2 page C7-2291 line 128880 MATCH x2e202000/mask=xbf20fc00
# CONSTRUCT x6ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 =$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl2/2@4
# AUNIT --inst x6ea02000/mask=xffe0fc00 --status pass --comment "ext"
:usubl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x2 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
TMPD3 = Rm_VPR128.4S[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
TMPQ4[0,64] = zext(TMPD3[0,32]);
TMPQ4[64,64] = zext(TMPD3[32,32]);
# simd infix Rd_VPR128.2D = TMPQ2 - TMPQ4 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ2[0,64] - TMPQ4[0,64];
Rd_VPR128.2D[64,64] = TMPQ2[64,64] - TMPQ4[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.396 USUBL, USUBL2 page C7-2291 line 128880 MATCH x2e202000/mask=xbf20fc00
# CONSTRUCT x6e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 =$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl2/2@2
# AUNIT --inst x6e602000/mask=xffe0fc00 --status pass --comment "ext"
:usubl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x2 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
TMPD3 = Rm_VPR128.8H[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
TMPQ4[0,32] = zext(TMPD3[0,16]);
TMPQ4[32,32] = zext(TMPD3[16,16]);
TMPQ4[64,32] = zext(TMPD3[32,16]);
TMPQ4[96,32] = zext(TMPD3[48,16]);
# simd infix Rd_VPR128.4S = TMPQ2 - TMPQ4 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ2[0,32] - TMPQ4[0,32];
Rd_VPR128.4S[32,32] = TMPQ2[32,32] - TMPQ4[32,32];
Rd_VPR128.4S[64,32] = TMPQ2[64,32] - TMPQ4[64,32];
Rd_VPR128.4S[96,32] = TMPQ2[96,32] - TMPQ4[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.396 USUBL, USUBL2 page C7-2291 line 128880 MATCH x2e202000/mask=xbf20fc00
# CONSTRUCT x6e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 =$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl2/2@1
# AUNIT --inst x6e202000/mask=xffe0fc00 --status pass --comment "ext"
:usubl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x2 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = zext(TMPD1[0,8]);
TMPQ2[16,16] = zext(TMPD1[8,8]);
TMPQ2[32,16] = zext(TMPD1[16,8]);
TMPQ2[48,16] = zext(TMPD1[24,8]);
TMPQ2[64,16] = zext(TMPD1[32,8]);
TMPQ2[80,16] = zext(TMPD1[40,8]);
TMPQ2[96,16] = zext(TMPD1[48,8]);
TMPQ2[112,16] = zext(TMPD1[56,8]);
TMPD3 = Rm_VPR128.16B[64,64];
# simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
TMPQ4[0,16] = zext(TMPD3[0,8]);
TMPQ4[16,16] = zext(TMPD3[8,8]);
TMPQ4[32,16] = zext(TMPD3[16,8]);
TMPQ4[48,16] = zext(TMPD3[24,8]);
TMPQ4[64,16] = zext(TMPD3[32,8]);
TMPQ4[80,16] = zext(TMPD3[40,8]);
TMPQ4[96,16] = zext(TMPD3[48,8]);
TMPQ4[112,16] = zext(TMPD3[56,8]);
# simd infix Rd_VPR128.8H = TMPQ2 - TMPQ4 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ2[0,16] - TMPQ4[0,16];
Rd_VPR128.8H[16,16] = TMPQ2[16,16] - TMPQ4[16,16];
Rd_VPR128.8H[32,16] = TMPQ2[32,16] - TMPQ4[32,16];
Rd_VPR128.8H[48,16] = TMPQ2[48,16] - TMPQ4[48,16];
Rd_VPR128.8H[64,16] = TMPQ2[64,16] - TMPQ4[64,16];
Rd_VPR128.8H[80,16] = TMPQ2[80,16] - TMPQ4[80,16];
Rd_VPR128.8H[96,16] = TMPQ2[96,16] - TMPQ4[96,16];
Rd_VPR128.8H[112,16] = TMPQ2[112,16] - TMPQ4[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.396 USUBL, USUBL2 page C7-2291 line 128880 MATCH x2e202000/mask=xbf20fc00
# CONSTRUCT x2ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 =$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl/2@4
# AUNIT --inst x2ea02000/mask=xffe0fc00 --status pass --comment "ext"
:usubl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x2 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
# simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);
TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);
# simd infix Rd_VPR128.2D = TMPQ1 - TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64] - TMPQ2[0,64];
Rd_VPR128.2D[64,64] = TMPQ1[64,64] - TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.396 USUBL, USUBL2 page C7-2291 line 128880 MATCH x2e202000/mask=xbf20fc00
# CONSTRUCT x2e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 =$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl/2@2
# AUNIT --inst x2e602000/mask=xffe0fc00 --status pass --comment "ext"
:usubl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x2 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
# simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);
TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);
TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);
TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);
# simd infix Rd_VPR128.4S = TMPQ1 - TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32] - TMPQ2[0,32];
Rd_VPR128.4S[32,32] = TMPQ1[32,32] - TMPQ2[32,32];
Rd_VPR128.4S[64,32] = TMPQ1[64,32] - TMPQ2[64,32];
Rd_VPR128.4S[96,32] = TMPQ1[96,32] - TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.396 USUBL, USUBL2 page C7-2291 line 128880 MATCH x2e202000/mask=xbf20fc00
# CONSTRUCT x2e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 =$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl/2@1
# AUNIT --inst x2e202000/mask=xffe0fc00 --status pass --comment "ext"
:usubl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x2 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
# simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);
TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);
TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);
TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);
TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);
TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);
TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);
TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);
# simd infix Rd_VPR128.8H = TMPQ1 - TMPQ2 on lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[0,16] - TMPQ2[0,16];
Rd_VPR128.8H[16,16] = TMPQ1[16,16] - TMPQ2[16,16];
Rd_VPR128.8H[32,16] = TMPQ1[32,16] - TMPQ2[32,16];
Rd_VPR128.8H[48,16] = TMPQ1[48,16] - TMPQ2[48,16];
Rd_VPR128.8H[64,16] = TMPQ1[64,16] - TMPQ2[64,16];
Rd_VPR128.8H[80,16] = TMPQ1[80,16] - TMPQ2[80,16];
Rd_VPR128.8H[96,16] = TMPQ1[96,16] - TMPQ2[96,16];
Rd_VPR128.8H[112,16] = TMPQ1[112,16] - TMPQ2[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.397 USUBW, USUBW2 page C7-2293 line 129000 MATCH x2e203000/mask=xbf20fc00
# CONSTRUCT x6ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@4:16 =$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw2/2@4
# AUNIT --inst x6ea03000/mask=xffe0fc00 --status pass --comment "ext"
:usubw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
TMPD1 = Rm_VPR128.4S[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
TMPQ2[0,64] = zext(TMPD1[0,32]);
TMPQ2[64,64] = zext(TMPD1[32,32]);
# simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ2 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ2[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.397 USUBW, USUBW2 page C7-2293 line 129000 MATCH x2e203000/mask=xbf20fc00
# CONSTRUCT x6e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@2:16 =$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw2/2@2
# AUNIT --inst x6e603000/mask=xffe0fc00 --status pass --comment "ext"
:usubw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
TMPD1 = Rm_VPR128.8H[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
TMPQ2[0,32] = zext(TMPD1[0,16]);
TMPQ2[32,32] = zext(TMPD1[16,16]);
TMPQ2[64,32] = zext(TMPD1[32,16]);
TMPQ2[96,32] = zext(TMPD1[48,16]);
# simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ2 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ2[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ2[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ2[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.397 USUBW, USUBW2 page C7-2293 line 129000 MATCH x2e203000/mask=xbf20fc00
# CONSTRUCT x6e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@1:16 =$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw2/2@1
# AUNIT --inst x6e203000/mask=xffe0fc00 --status pass --comment "ext"
:usubw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
TMPD1 = Rm_VPR128.16B[64,64];
# simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
TMPQ2[0,16] = zext(TMPD1[0,8]);
TMPQ2[16,16] = zext(TMPD1[8,8]);
TMPQ2[32,16] = zext(TMPD1[16,8]);
TMPQ2[48,16] = zext(TMPD1[24,8]);
TMPQ2[64,16] = zext(TMPD1[32,8]);
TMPQ2[80,16] = zext(TMPD1[40,8]);
TMPQ2[96,16] = zext(TMPD1[48,8]);
TMPQ2[112,16] = zext(TMPD1[56,8]);
# simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ2 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ2[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ2[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ2[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ2[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ2[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ2[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ2[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ2[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.397 USUBW, USUBW2 page C7-2293 line 129000 MATCH x2e203000/mask=xbf20fc00
# CONSTRUCT x2ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $zext@4:16 =$-@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw/2@4
# AUNIT --inst x2ea03000/mask=xffe0fc00 --status pass --comment "ext"
:usubw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
# simd resize TMPQ1 = zext(Rm_VPR64.2S) (lane size 4 to 8)
TMPQ1[0,64] = zext(Rm_VPR64.2S[0,32]);
TMPQ1[64,64] = zext(Rm_VPR64.2S[32,32]);
# simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ1 on lane size 8
Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ1[0,64];
Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ1[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.397 USUBW, USUBW2 page C7-2293 line 129000 MATCH x2e203000/mask=xbf20fc00
# CONSTRUCT x2e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $zext@2:16 =$-@4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw/2@2
# AUNIT --inst x2e603000/mask=xffe0fc00 --status pass --comment "ext"
:usubw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
# simd resize TMPQ1 = zext(Rm_VPR64.4H) (lane size 2 to 4)
TMPQ1[0,32] = zext(Rm_VPR64.4H[0,16]);
TMPQ1[32,32] = zext(Rm_VPR64.4H[16,16]);
TMPQ1[64,32] = zext(Rm_VPR64.4H[32,16]);
TMPQ1[96,32] = zext(Rm_VPR64.4H[48,16]);
# simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ1 on lane size 4
Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ1[0,32];
Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ1[32,32];
Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ1[64,32];
Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ1[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.397 USUBW, USUBW2 page C7-2293 line 129000 MATCH x2e203000/mask=xbf20fc00
# CONSTRUCT x2e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $zext@1:16 =$-@2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw/2@1
# AUNIT --inst x2e203000/mask=xffe0fc00 --status pass --comment "ext"
:usubw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
# simd resize TMPQ1 = zext(Rm_VPR64.8B) (lane size 1 to 2)
TMPQ1[0,16] = zext(Rm_VPR64.8B[0,8]);
TMPQ1[16,16] = zext(Rm_VPR64.8B[8,8]);
TMPQ1[32,16] = zext(Rm_VPR64.8B[16,8]);
TMPQ1[48,16] = zext(Rm_VPR64.8B[24,8]);
TMPQ1[64,16] = zext(Rm_VPR64.8B[32,8]);
TMPQ1[80,16] = zext(Rm_VPR64.8B[40,8]);
TMPQ1[96,16] = zext(Rm_VPR64.8B[48,8]);
TMPQ1[112,16] = zext(Rm_VPR64.8B[56,8]);
# simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ1 on lane size 2
Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ1[0,16];
Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ1[16,16];
Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ1[32,16];
Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ1[48,16];
Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ1[64,16];
Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ1[80,16];
Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ1[96,16];
Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ1[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# CONSTRUCT x6f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 =$zext@1:16
# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl2/1@1
# AUNIT --inst x6f08a400/mask=xfffffc00 --status pass --comment "ext"
:uxtl2 Rd_VPR128.8H, Rn_VPR128.16B
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR128.16B[64,64];
# simd resize Rd_VPR128.8H = zext(TMPD1) (lane size 1 to 2)
Rd_VPR128.8H[0,16] = zext(TMPD1[0,8]);
Rd_VPR128.8H[16,16] = zext(TMPD1[8,8]);
Rd_VPR128.8H[32,16] = zext(TMPD1[16,8]);
Rd_VPR128.8H[48,16] = zext(TMPD1[24,8]);
Rd_VPR128.8H[64,16] = zext(TMPD1[32,8]);
Rd_VPR128.8H[80,16] = zext(TMPD1[40,8]);
Rd_VPR128.8H[96,16] = zext(TMPD1[48,8]);
Rd_VPR128.8H[112,16] = zext(TMPD1[56,8]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# CONSTRUCT x2f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =$zext@4:16
# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl/1@4
# AUNIT --inst x2f20a400/mask=xfffffc00 --status pass --comment "ext"
:uxtl Rd_VPR128.2D, Rn_VPR64.2S
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR64.2S;
# simd resize Rd_VPR128.2D = zext(TMPD1) (lane size 4 to 8)
Rd_VPR128.2D[0,64] = zext(TMPD1[0,32]);
Rd_VPR128.2D[64,64] = zext(TMPD1[32,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# CONSTRUCT x2f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =$zext@2:16
# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl/1@2
# AUNIT --inst x2f10a400/mask=xfffffc00 --status pass --comment "ext"
:uxtl Rd_VPR128.4S, Rn_VPR64.4H
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR64.4H;
# simd resize Rd_VPR128.4S = zext(TMPD1) (lane size 2 to 4)
Rd_VPR128.4S[0,32] = zext(TMPD1[0,16]);
Rd_VPR128.4S[32,32] = zext(TMPD1[16,16]);
Rd_VPR128.4S[64,32] = zext(TMPD1[32,16]);
Rd_VPR128.4S[96,32] = zext(TMPD1[48,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# CONSTRUCT x6f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 =$zext@4:16
# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl2/1@4
# AUNIT --inst x6f20a400/mask=xfffffc00 --status pass --comment "ext"
:uxtl2 Rd_VPR128.2D, Rn_VPR128.4S
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
{
TMPD1 = Rn_VPR128.4S[64,64];
# simd resize Rd_VPR128.2D = zext(TMPD1) (lane size 4 to 8)
Rd_VPR128.2D[0,64] = zext(TMPD1[0,32]);
Rd_VPR128.2D[64,64] = zext(TMPD1[32,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# CONSTRUCT x2f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 =var =$zext@1:16
# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl/1@1
# AUNIT --inst x2f08a400/mask=xfffffc00 --status pass --comment "ext"
:uxtl Rd_VPR128.8H, Rn_VPR64.8B
is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
{
TMPD1 = Rn_VPR64.8B;
# simd resize Rd_VPR128.8H = zext(TMPD1) (lane size 1 to 2)
Rd_VPR128.8H[0,16] = zext(TMPD1[0,8]);
Rd_VPR128.8H[16,16] = zext(TMPD1[8,8]);
Rd_VPR128.8H[32,16] = zext(TMPD1[16,8]);
Rd_VPR128.8H[48,16] = zext(TMPD1[24,8]);
Rd_VPR128.8H[64,16] = zext(TMPD1[32,8]);
Rd_VPR128.8H[80,16] = zext(TMPD1[40,8]);
Rd_VPR128.8H[96,16] = zext(TMPD1[48,8]);
Rd_VPR128.8H[112,16] = zext(TMPD1[56,8]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.398 UXTL, UXTL2 page C7-2295 line 129122 MATCH x2f00a400/mask=xbf87fc00
# C7.2.391 USHLL, USHLL2 page C7-2280 line 128256 MATCH x2f00a400/mask=xbf80fc00
# CONSTRUCT x6f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2[1]:8 =$zext@2:16
# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl2/1@2
# AUNIT --inst x6f10a400/mask=xfffffc00 --status pass --comment "ext"
:uxtl2 Rd_VPR128.4S, Rn_VPR128.8H
is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPD1 = Rn_VPR128.8H[64,64];
# simd resize Rd_VPR128.4S = zext(TMPD1) (lane size 2 to 4)
Rd_VPR128.4S[0,32] = zext(TMPD1[0,16]);
Rd_VPR128.4S[32,32] = zext(TMPD1[16,16]);
Rd_VPR128.4S[64,32] = zext(TMPD1[32,16]);
Rd_VPR128.4S[96,32] = zext(TMPD1[48,16]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.399 UZP1 page C7-2297 line 129221 MATCH x0e001800/mask=xbf20fc00
# CONSTRUCT x4e001800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1@4-2@6-3@8-4@10-5@12-6@14-7:1 swap &=$shuffle@0-8@2-9@4-10@6-11@8-12@10-13@12-14@14-15:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@1
# AUNIT --inst x4e001800/mask=xffe0fc00 --status pass
:uzp1 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
TMPQ2 = Rm_VPR128.16B;
TMPQ1 = Rn_VPR128.16B;
# simd shuffle Rd_VPR128.16B = TMPQ1 (@0-0@2-1@4-2@6-3@8-4@10-5@12-6@14-7) lane size 1
Rd_VPR128.16B[0,8] = TMPQ1[0,8];
Rd_VPR128.16B[8,8] = TMPQ1[16,8];
Rd_VPR128.16B[16,8] = TMPQ1[32,8];
Rd_VPR128.16B[24,8] = TMPQ1[48,8];
Rd_VPR128.16B[32,8] = TMPQ1[64,8];
Rd_VPR128.16B[40,8] = TMPQ1[80,8];
Rd_VPR128.16B[48,8] = TMPQ1[96,8];
Rd_VPR128.16B[56,8] = TMPQ1[112,8];
# simd shuffle Rd_VPR128.16B = TMPQ2 (@0-8@2-9@4-10@6-11@8-12@10-13@12-14@14-15) lane size 1
Rd_VPR128.16B[64,8] = TMPQ2[0,8];
Rd_VPR128.16B[72,8] = TMPQ2[16,8];
Rd_VPR128.16B[80,8] = TMPQ2[32,8];
Rd_VPR128.16B[88,8] = TMPQ2[48,8];
Rd_VPR128.16B[96,8] = TMPQ2[64,8];
Rd_VPR128.16B[104,8] = TMPQ2[80,8];
Rd_VPR128.16B[112,8] = TMPQ2[96,8];
Rd_VPR128.16B[120,8] = TMPQ2[112,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.399 UZP1 page C7-2297 line 129221 MATCH x0e001800/mask=xbf20fc00
# CONSTRUCT x4ec01800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:8 swap &=$shuffle@0-1:8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@8
# AUNIT --inst x4ec01800/mask=xffe0fc00 --status pass
:uzp1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
TMPQ2 = Rm_VPR128.2D;
TMPQ1 = Rn_VPR128.2D;
# simd shuffle Rd_VPR128.2D = TMPQ1 (@0-0) lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64];
# simd shuffle Rd_VPR128.2D = TMPQ2 (@0-1) lane size 8
Rd_VPR128.2D[64,64] = TMPQ2[0,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.399 UZP1 page C7-2297 line 129221 MATCH x0e001800/mask=xbf20fc00
# CONSTRUCT x0e801800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:4 swap &=$shuffle@0-1:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@4
# AUNIT --inst x0e801800/mask=xffe0fc00 --status pass
:uzp1 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
TMPD2 = Rm_VPR64.2S;
TMPD1 = Rn_VPR64.2S;
# simd shuffle Rd_VPR64.2S = TMPD1 (@0-0) lane size 4
Rd_VPR64.2S[0,32] = TMPD1[0,32];
# simd shuffle Rd_VPR64.2S = TMPD2 (@0-1) lane size 4
Rd_VPR64.2S[32,32] = TMPD2[0,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.399 UZP1 page C7-2297 line 129221 MATCH x0e001800/mask=xbf20fc00
# CONSTRUCT x0e401800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1:2 swap &=$shuffle@0-2@2-3:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@2
# AUNIT --inst x0e401800/mask=xffe0fc00 --status pass
:uzp1 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
TMPD2 = Rm_VPR64.4H;
TMPD1 = Rn_VPR64.4H;
# simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@2-1) lane size 2
Rd_VPR64.4H[0,16] = TMPD1[0,16];
Rd_VPR64.4H[16,16] = TMPD1[32,16];
# simd shuffle Rd_VPR64.4H = TMPD2 (@0-2@2-3) lane size 2
Rd_VPR64.4H[32,16] = TMPD2[0,16];
Rd_VPR64.4H[48,16] = TMPD2[32,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.399 UZP1 page C7-2297 line 129221 MATCH x0e001800/mask=xbf20fc00
# CONSTRUCT x4e801800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1:4 swap &=$shuffle@0-2@2-3:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@4
# AUNIT --inst x4e801800/mask=xffe0fc00 --status pass
:uzp1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
TMPQ2 = Rm_VPR128.4S;
TMPQ1 = Rn_VPR128.4S;
# simd shuffle Rd_VPR128.4S = TMPQ1 (@0-0@2-1) lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32];
Rd_VPR128.4S[32,32] = TMPQ1[64,32];
# simd shuffle Rd_VPR128.4S = TMPQ2 (@0-2@2-3) lane size 4
Rd_VPR128.4S[64,32] = TMPQ2[0,32];
Rd_VPR128.4S[96,32] = TMPQ2[64,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.399 UZP1 page C7-2297 line 129221 MATCH x0e001800/mask=xbf20fc00
# CONSTRUCT x0e001800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1@4-2@6-3:1 swap &=$shuffle@0-4@2-5@4-6@6-7:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@1
# AUNIT --inst x0e001800/mask=xffe0fc00 --status pass
:uzp1 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
TMPD2 = Rm_VPR64.8B;
TMPD1 = Rn_VPR64.8B;
# simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@2-1@4-2@6-3) lane size 1
Rd_VPR64.8B[0,8] = TMPD1[0,8];
Rd_VPR64.8B[8,8] = TMPD1[16,8];
Rd_VPR64.8B[16,8] = TMPD1[32,8];
Rd_VPR64.8B[24,8] = TMPD1[48,8];
# simd shuffle Rd_VPR64.8B = TMPD2 (@0-4@2-5@4-6@6-7) lane size 1
Rd_VPR64.8B[32,8] = TMPD2[0,8];
Rd_VPR64.8B[40,8] = TMPD2[16,8];
Rd_VPR64.8B[48,8] = TMPD2[32,8];
Rd_VPR64.8B[56,8] = TMPD2[48,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.399 UZP1 page C7-2297 line 129221 MATCH x0e001800/mask=xbf20fc00
# CONSTRUCT x4e401800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1@4-2@6-3:2 swap &=$shuffle@0-4@2-5@4-6@6-7:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@2
# AUNIT --inst x4e401800/mask=xffe0fc00 --status pass
:uzp1 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
TMPQ2 = Rm_VPR128.8H;
TMPQ1 = Rn_VPR128.8H;
# simd shuffle Rd_VPR128.8H = TMPQ1 (@0-0@2-1@4-2@6-3) lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[0,16];
Rd_VPR128.8H[16,16] = TMPQ1[32,16];
Rd_VPR128.8H[32,16] = TMPQ1[64,16];
Rd_VPR128.8H[48,16] = TMPQ1[96,16];
# simd shuffle Rd_VPR128.8H = TMPQ2 (@0-4@2-5@4-6@6-7) lane size 2
Rd_VPR128.8H[64,16] = TMPQ2[0,16];
Rd_VPR128.8H[80,16] = TMPQ2[32,16];
Rd_VPR128.8H[96,16] = TMPQ2[64,16];
Rd_VPR128.8H[112,16] = TMPQ2[96,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.400 UZP2 page C7-2299 line 129332 MATCH x0e005800/mask=xbf20fc00
# CONSTRUCT x4e005800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:1 swap &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@1
# AUNIT --inst x4e005800/mask=xffe0fc00 --status pass
:uzp2 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
TMPQ2 = Rm_VPR128.16B;
TMPQ1 = Rn_VPR128.16B;
# simd shuffle Rd_VPR128.16B = TMPQ1 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 1
Rd_VPR128.16B[0,8] = TMPQ1[8,8];
Rd_VPR128.16B[8,8] = TMPQ1[24,8];
Rd_VPR128.16B[16,8] = TMPQ1[40,8];
Rd_VPR128.16B[24,8] = TMPQ1[56,8];
Rd_VPR128.16B[32,8] = TMPQ1[72,8];
Rd_VPR128.16B[40,8] = TMPQ1[88,8];
Rd_VPR128.16B[48,8] = TMPQ1[104,8];
Rd_VPR128.16B[56,8] = TMPQ1[120,8];
# simd shuffle Rd_VPR128.16B = TMPQ2 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1
Rd_VPR128.16B[64,8] = TMPQ2[8,8];
Rd_VPR128.16B[72,8] = TMPQ2[24,8];
Rd_VPR128.16B[80,8] = TMPQ2[40,8];
Rd_VPR128.16B[88,8] = TMPQ2[56,8];
Rd_VPR128.16B[96,8] = TMPQ2[72,8];
Rd_VPR128.16B[104,8] = TMPQ2[88,8];
Rd_VPR128.16B[112,8] = TMPQ2[104,8];
Rd_VPR128.16B[120,8] = TMPQ2[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.400 UZP2 page C7-2299 line 129332 MATCH x0e005800/mask=xbf20fc00
# CONSTRUCT x4ec05800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:8 swap &=$shuffle@1-1:8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@8
# AUNIT --inst x4ec05800/mask=xffe0fc00 --status pass
:uzp2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
TMPQ2 = Rm_VPR128.2D;
TMPQ1 = Rn_VPR128.2D;
# simd shuffle Rd_VPR128.2D = TMPQ1 (@1-0) lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[64,64];
# simd shuffle Rd_VPR128.2D = TMPQ2 (@1-1) lane size 8
Rd_VPR128.2D[64,64] = TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.400 UZP2 page C7-2299 line 129332 MATCH x0e005800/mask=xbf20fc00
# CONSTRUCT x0e805800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:4 swap &=$shuffle@1-1:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@4
# AUNIT --inst x0e805800/mask=xffe0fc00 --status pass
:uzp2 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
TMPD2 = Rm_VPR64.2S;
TMPD1 = Rn_VPR64.2S;
# simd shuffle Rd_VPR64.2S = TMPD1 (@1-0) lane size 4
Rd_VPR64.2S[0,32] = TMPD1[32,32];
# simd shuffle Rd_VPR64.2S = TMPD2 (@1-1) lane size 4
Rd_VPR64.2S[32,32] = TMPD2[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.400 UZP2 page C7-2299 line 129332 MATCH x0e005800/mask=xbf20fc00
# CONSTRUCT x0e405800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1:2 swap &=$shuffle@1-2@3-3:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@2
# AUNIT --inst x0e405800/mask=xffe0fc00 --status pass
:uzp2 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
TMPD2 = Rm_VPR64.4H;
TMPD1 = Rn_VPR64.4H;
# simd shuffle Rd_VPR64.4H = TMPD1 (@1-0@3-1) lane size 2
Rd_VPR64.4H[0,16] = TMPD1[16,16];
Rd_VPR64.4H[16,16] = TMPD1[48,16];
# simd shuffle Rd_VPR64.4H = TMPD2 (@1-2@3-3) lane size 2
Rd_VPR64.4H[32,16] = TMPD2[16,16];
Rd_VPR64.4H[48,16] = TMPD2[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.400 UZP2 page C7-2299 line 129332 MATCH x0e005800/mask=xbf20fc00
# CONSTRUCT x4e805800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1:4 swap &=$shuffle@1-2@3-3:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@4
# AUNIT --inst x4e805800/mask=xffe0fc00 --status pass
:uzp2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
TMPQ2 = Rm_VPR128.4S;
TMPQ1 = Rn_VPR128.4S;
# simd shuffle Rd_VPR128.4S = TMPQ1 (@1-0@3-1) lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[32,32];
Rd_VPR128.4S[32,32] = TMPQ1[96,32];
# simd shuffle Rd_VPR128.4S = TMPQ2 (@1-2@3-3) lane size 4
Rd_VPR128.4S[64,32] = TMPQ2[32,32];
Rd_VPR128.4S[96,32] = TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.400 UZP2 page C7-2299 line 129332 MATCH x0e005800/mask=xbf20fc00
# CONSTRUCT x0e005800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1@5-2@7-3:1 swap &=$shuffle@1-4@3-5@5-6@7-7:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@1
# AUNIT --inst x0e005800/mask=xffe0fc00 --status pass
:uzp2 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
TMPD2 = Rm_VPR64.8B;
TMPD1 = Rn_VPR64.8B;
# simd shuffle Rd_VPR64.8B = TMPD1 (@1-0@3-1@5-2@7-3) lane size 1
Rd_VPR64.8B[0,8] = TMPD1[8,8];
Rd_VPR64.8B[8,8] = TMPD1[24,8];
Rd_VPR64.8B[16,8] = TMPD1[40,8];
Rd_VPR64.8B[24,8] = TMPD1[56,8];
# simd shuffle Rd_VPR64.8B = TMPD2 (@1-4@3-5@5-6@7-7) lane size 1
Rd_VPR64.8B[32,8] = TMPD2[8,8];
Rd_VPR64.8B[40,8] = TMPD2[24,8];
Rd_VPR64.8B[48,8] = TMPD2[40,8];
Rd_VPR64.8B[56,8] = TMPD2[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.400 UZP2 page C7-2299 line 129332 MATCH x0e005800/mask=xbf20fc00
# CONSTRUCT x4e405800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1@5-2@7-3:2 swap &=$shuffle@1-4@3-5@5-6@7-7:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@2
# AUNIT --inst x4e405800/mask=xffe0fc00 --status pass
:uzp2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
TMPQ2 = Rm_VPR128.8H;
TMPQ1 = Rn_VPR128.8H;
# simd shuffle Rd_VPR128.8H = TMPQ1 (@1-0@3-1@5-2@7-3) lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[16,16];
Rd_VPR128.8H[16,16] = TMPQ1[48,16];
Rd_VPR128.8H[32,16] = TMPQ1[80,16];
Rd_VPR128.8H[48,16] = TMPQ1[112,16];
# simd shuffle Rd_VPR128.8H = TMPQ2 (@1-4@3-5@5-6@7-7) lane size 2
Rd_VPR128.8H[64,16] = TMPQ2[16,16];
Rd_VPR128.8H[80,16] = TMPQ2[48,16];
Rd_VPR128.8H[96,16] = TMPQ2[80,16];
Rd_VPR128.8H[112,16] = TMPQ2[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.401 XAR page C7-2301 line 129443 MATCH xce800000/mask=xffe00000
# CONSTRUCT xce800000/mask=xffe00000 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 ARG3 $|@8 ARG4 =var:8 =$>>@8
# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_xar/3@8
# AUNIT --inst xce800000/mask=xffe00000 --status noqemu
# Advanced SIMD variant
:xar Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, LSB_bitfield64_imm
is b_2131=0b11001110100 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & LSB_bitfield64_imm & Zd
{
# simd infix TMPQ1 = Rn_VPR128.2D | Rm_VPR128.2D on lane size 8
TMPQ1[0,64] = Rn_VPR128.2D[0,64] | Rm_VPR128.2D[0,64];
TMPQ1[64,64] = Rn_VPR128.2D[64,64] | Rm_VPR128.2D[64,64];
local tmp2:8 = LSB_bitfield64_imm;
# simd infix Rd_VPR128.2D = TMPQ1 >> tmp2 on lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64] >> tmp2;
Rd_VPR128.2D[64,64] = TMPQ1[64,64] >> tmp2;
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.402 XTN, XTN2 page C7-2302 line 129514 MATCH x0e212800/mask=xbf3ffc00
# CONSTRUCT x0ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@8:8 &=$shuffle@0-0@1-1:4
# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn/2@8
# AUNIT --inst x0ea12800/mask=xfffffc00 --status pass --comment "ext"
:xtn Rd_VPR64.2S, Rn_VPR128.2D
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
{
# simd resize TMPD1 = zext(Rn_VPR128.2D) (lane size 8 to 4)
TMPD1[0,32] = Rn_VPR128.2D[0,32];
TMPD1[32,32] = Rn_VPR128.2D[64,32];
# simd shuffle Rd_VPR64.2S = TMPD1 (@0-0@1-1) lane size 4
Rd_VPR64.2S[0,32] = TMPD1[0,32];
Rd_VPR64.2S[32,32] = TMPD1[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.402 XTN, XTN2 page C7-2302 line 129514 MATCH x0e212800/mask=xbf3ffc00
# CONSTRUCT x4ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@8:8 &=$shuffle@0-2@1-3:4
# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn2/2@8
# AUNIT --inst x4ea12800/mask=xfffffc00 --status pass --comment "ext"
:xtn2 Rd_VPR128.4S, Rn_VPR128.2D
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
{
# simd resize TMPD1 = zext(Rn_VPR128.2D) (lane size 8 to 4)
TMPD1[0,32] = Rn_VPR128.2D[0,32];
TMPD1[32,32] = Rn_VPR128.2D[64,32];
# simd shuffle Rd_VPR128.4S = TMPD1 (@0-2@1-3) lane size 4
Rd_VPR128.4S[64,32] = TMPD1[0,32];
Rd_VPR128.4S[96,32] = TMPD1[32,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.402 XTN, XTN2 page C7-2302 line 129514 MATCH x0e212800/mask=xbf3ffc00
# CONSTRUCT x0e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@4:8 &=$shuffle@0-0@1-1@2-2@3-3:2
# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn/2@4
# AUNIT --inst x0e612800/mask=xfffffc00 --status pass --comment "ext"
:xtn Rd_VPR64.4H, Rn_VPR128.4S
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
{
# simd resize TMPD1 = zext(Rn_VPR128.4S) (lane size 4 to 2)
TMPD1[0,16] = Rn_VPR128.4S[0,16];
TMPD1[16,16] = Rn_VPR128.4S[32,16];
TMPD1[32,16] = Rn_VPR128.4S[64,16];
TMPD1[48,16] = Rn_VPR128.4S[96,16];
# simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@1-1@2-2@3-3) lane size 2
Rd_VPR64.4H[0,16] = TMPD1[0,16];
Rd_VPR64.4H[16,16] = TMPD1[16,16];
Rd_VPR64.4H[32,16] = TMPD1[32,16];
Rd_VPR64.4H[48,16] = TMPD1[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.402 XTN, XTN2 page C7-2302 line 129514 MATCH x0e212800/mask=xbf3ffc00
# CONSTRUCT x4e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@4:8 &=$shuffle@0-4@1-5@2-6@3-7:2
# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn2/2@4
# AUNIT --inst x4e612800/mask=xfffffc00 --status pass --comment "ext"
:xtn2 Rd_VPR128.8H, Rn_VPR128.4S
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
{
# simd resize TMPD1 = zext(Rn_VPR128.4S) (lane size 4 to 2)
TMPD1[0,16] = Rn_VPR128.4S[0,16];
TMPD1[16,16] = Rn_VPR128.4S[32,16];
TMPD1[32,16] = Rn_VPR128.4S[64,16];
TMPD1[48,16] = Rn_VPR128.4S[96,16];
# simd shuffle Rd_VPR128.8H = TMPD1 (@0-4@1-5@2-6@3-7) lane size 2
Rd_VPR128.8H[64,16] = TMPD1[0,16];
Rd_VPR128.8H[80,16] = TMPD1[16,16];
Rd_VPR128.8H[96,16] = TMPD1[32,16];
Rd_VPR128.8H[112,16] = TMPD1[48,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.402 XTN, XTN2 page C7-2302 line 129514 MATCH x0e212800/mask=xbf3ffc00
# CONSTRUCT x0e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@2:8 &=$shuffle@0-0@1-1@2-2@3-3@4-4@5-5@6-6@7-7:1
# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn/2@2
# AUNIT --inst x0e212800/mask=xfffffc00 --status pass --comment "ext"
:xtn Rd_VPR64.8B, Rn_VPR128.8H
is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
{
# simd resize TMPD1 = zext(Rn_VPR128.8H) (lane size 2 to 1)
TMPD1[0,8] = Rn_VPR128.8H[0,8];
TMPD1[8,8] = Rn_VPR128.8H[16,8];
TMPD1[16,8] = Rn_VPR128.8H[32,8];
TMPD1[24,8] = Rn_VPR128.8H[48,8];
TMPD1[32,8] = Rn_VPR128.8H[64,8];
TMPD1[40,8] = Rn_VPR128.8H[80,8];
TMPD1[48,8] = Rn_VPR128.8H[96,8];
TMPD1[56,8] = Rn_VPR128.8H[112,8];
# simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@1-1@2-2@3-3@4-4@5-5@6-6@7-7) lane size 1
Rd_VPR64.8B[0,8] = TMPD1[0,8];
Rd_VPR64.8B[8,8] = TMPD1[8,8];
Rd_VPR64.8B[16,8] = TMPD1[16,8];
Rd_VPR64.8B[24,8] = TMPD1[24,8];
Rd_VPR64.8B[32,8] = TMPD1[32,8];
Rd_VPR64.8B[40,8] = TMPD1[40,8];
Rd_VPR64.8B[48,8] = TMPD1[48,8];
Rd_VPR64.8B[56,8] = TMPD1[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.402 XTN, XTN2 page C7-2302 line 129514 MATCH x0e212800/mask=xbf3ffc00
# CONSTRUCT x4e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG1 ARG2 $zext@2:8 &=$shuffle@0-8@1-9@2-10@3-11@4-12@5-13@6-14@7-15:1
# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn2/2@2
# AUNIT --inst x4e212800/mask=xfffffc00 --status pass --comment "ext"
:xtn2 Rd_VPR128.16B, Rn_VPR128.8H
is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
{
# simd resize TMPD1 = zext(Rn_VPR128.8H) (lane size 2 to 1)
TMPD1[0,8] = Rn_VPR128.8H[0,8];
TMPD1[8,8] = Rn_VPR128.8H[16,8];
TMPD1[16,8] = Rn_VPR128.8H[32,8];
TMPD1[24,8] = Rn_VPR128.8H[48,8];
TMPD1[32,8] = Rn_VPR128.8H[64,8];
TMPD1[40,8] = Rn_VPR128.8H[80,8];
TMPD1[48,8] = Rn_VPR128.8H[96,8];
TMPD1[56,8] = Rn_VPR128.8H[112,8];
# simd shuffle Rd_VPR128.16B = TMPD1 (@0-8@1-9@2-10@3-11@4-12@5-13@6-14@7-15) lane size 1
Rd_VPR128.16B[64,8] = TMPD1[0,8];
Rd_VPR128.16B[72,8] = TMPD1[8,8];
Rd_VPR128.16B[80,8] = TMPD1[16,8];
Rd_VPR128.16B[88,8] = TMPD1[24,8];
Rd_VPR128.16B[96,8] = TMPD1[32,8];
Rd_VPR128.16B[104,8] = TMPD1[40,8];
Rd_VPR128.16B[112,8] = TMPD1[48,8];
Rd_VPR128.16B[120,8] = TMPD1[56,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.403 ZIP1 page C7-2304 line 129621 MATCH x0e003800/mask=xbf20fc00
# CONSTRUCT x4e003800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2@2-4@3-6@4-8@5-10@6-12@7-14:1 swap &=$shuffle@0-1@1-3@2-5@3-7@4-9@5-11@6-13@7-15:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@1
# AUNIT --inst x4e003800/mask=xffe0fc00 --status pass
:zip1 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
TMPQ2 = Rm_VPR128.16B;
TMPQ1 = Rn_VPR128.16B;
# simd shuffle Rd_VPR128.16B = TMPQ1 (@0-0@1-2@2-4@3-6@4-8@5-10@6-12@7-14) lane size 1
Rd_VPR128.16B[0,8] = TMPQ1[0,8];
Rd_VPR128.16B[16,8] = TMPQ1[8,8];
Rd_VPR128.16B[32,8] = TMPQ1[16,8];
Rd_VPR128.16B[48,8] = TMPQ1[24,8];
Rd_VPR128.16B[64,8] = TMPQ1[32,8];
Rd_VPR128.16B[80,8] = TMPQ1[40,8];
Rd_VPR128.16B[96,8] = TMPQ1[48,8];
Rd_VPR128.16B[112,8] = TMPQ1[56,8];
# simd shuffle Rd_VPR128.16B = TMPQ2 (@0-1@1-3@2-5@3-7@4-9@5-11@6-13@7-15) lane size 1
Rd_VPR128.16B[8,8] = TMPQ2[0,8];
Rd_VPR128.16B[24,8] = TMPQ2[8,8];
Rd_VPR128.16B[40,8] = TMPQ2[16,8];
Rd_VPR128.16B[56,8] = TMPQ2[24,8];
Rd_VPR128.16B[72,8] = TMPQ2[32,8];
Rd_VPR128.16B[88,8] = TMPQ2[40,8];
Rd_VPR128.16B[104,8] = TMPQ2[48,8];
Rd_VPR128.16B[120,8] = TMPQ2[56,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.403 ZIP1 page C7-2304 line 129621 MATCH x0e003800/mask=xbf20fc00
# CONSTRUCT x4ec03800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:8 swap &=$shuffle@0-1:8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@8
# AUNIT --inst x4ec03800/mask=xffe0fc00 --status pass
:zip1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
TMPQ2 = Rm_VPR128.2D;
TMPQ1 = Rn_VPR128.2D;
# simd shuffle Rd_VPR128.2D = TMPQ1 (@0-0) lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[0,64];
# simd shuffle Rd_VPR128.2D = TMPQ2 (@0-1) lane size 8
Rd_VPR128.2D[64,64] = TMPQ2[0,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.403 ZIP1 page C7-2304 line 129621 MATCH x0e003800/mask=xbf20fc00
# CONSTRUCT x0e803800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:4 swap &=$shuffle@0-1:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@4
# AUNIT --inst x0e803800/mask=xffe0fc00 --status pass
:zip1 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
TMPD2 = Rm_VPR64.2S;
TMPD1 = Rn_VPR64.2S;
# simd shuffle Rd_VPR64.2S = TMPD1 (@0-0) lane size 4
Rd_VPR64.2S[0,32] = TMPD1[0,32];
# simd shuffle Rd_VPR64.2S = TMPD2 (@0-1) lane size 4
Rd_VPR64.2S[32,32] = TMPD2[0,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.403 ZIP1 page C7-2304 line 129621 MATCH x0e003800/mask=xbf20fc00
# CONSTRUCT x0e403800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2:2 swap &=$shuffle@0-1@1-3:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@2
# AUNIT --inst x0e403800/mask=xffe0fc00 --status pass
:zip1 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
TMPD2 = Rm_VPR64.4H;
TMPD1 = Rn_VPR64.4H;
# simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@1-2) lane size 2
Rd_VPR64.4H[0,16] = TMPD1[0,16];
Rd_VPR64.4H[32,16] = TMPD1[16,16];
# simd shuffle Rd_VPR64.4H = TMPD2 (@0-1@1-3) lane size 2
Rd_VPR64.4H[16,16] = TMPD2[0,16];
Rd_VPR64.4H[48,16] = TMPD2[16,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.403 ZIP1 page C7-2304 line 129621 MATCH x0e003800/mask=xbf20fc00
# CONSTRUCT x4e803800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2:4 swap &=$shuffle@0-1@1-3:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@4
# AUNIT --inst x4e803800/mask=xffe0fc00 --status pass
:zip1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
TMPQ2 = Rm_VPR128.4S;
TMPQ1 = Rn_VPR128.4S;
# simd shuffle Rd_VPR128.4S = TMPQ1 (@0-0@1-2) lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[0,32];
Rd_VPR128.4S[64,32] = TMPQ1[32,32];
# simd shuffle Rd_VPR128.4S = TMPQ2 (@0-1@1-3) lane size 4
Rd_VPR128.4S[32,32] = TMPQ2[0,32];
Rd_VPR128.4S[96,32] = TMPQ2[32,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.403 ZIP1 page C7-2304 line 129621 MATCH x0e003800/mask=xbf20fc00
# CONSTRUCT x0e003800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2@2-4@3-6:1 swap &=$shuffle@0-1@1-3@2-5@3-7:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@1
# AUNIT --inst x0e003800/mask=xffe0fc00 --status pass
:zip1 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
TMPD2 = Rm_VPR64.8B;
TMPD1 = Rn_VPR64.8B;
# simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@1-2@2-4@3-6) lane size 1
Rd_VPR64.8B[0,8] = TMPD1[0,8];
Rd_VPR64.8B[16,8] = TMPD1[8,8];
Rd_VPR64.8B[32,8] = TMPD1[16,8];
Rd_VPR64.8B[48,8] = TMPD1[24,8];
# simd shuffle Rd_VPR64.8B = TMPD2 (@0-1@1-3@2-5@3-7) lane size 1
Rd_VPR64.8B[8,8] = TMPD2[0,8];
Rd_VPR64.8B[24,8] = TMPD2[8,8];
Rd_VPR64.8B[40,8] = TMPD2[16,8];
Rd_VPR64.8B[56,8] = TMPD2[24,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.403 ZIP1 page C7-2304 line 129621 MATCH x0e003800/mask=xbf20fc00
# CONSTRUCT x4e403800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2@2-4@3-6:2 swap &=$shuffle@0-1@1-3@2-5@3-7:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@2
# AUNIT --inst x4e403800/mask=xffe0fc00 --status pass
:zip1 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
TMPQ2 = Rm_VPR128.8H;
TMPQ1 = Rn_VPR128.8H;
# simd shuffle Rd_VPR128.8H = TMPQ1 (@0-0@1-2@2-4@3-6) lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[0,16];
Rd_VPR128.8H[32,16] = TMPQ1[16,16];
Rd_VPR128.8H[64,16] = TMPQ1[32,16];
Rd_VPR128.8H[96,16] = TMPQ1[48,16];
# simd shuffle Rd_VPR128.8H = TMPQ2 (@0-1@1-3@2-5@3-7) lane size 2
Rd_VPR128.8H[16,16] = TMPQ2[0,16];
Rd_VPR128.8H[48,16] = TMPQ2[16,16];
Rd_VPR128.8H[80,16] = TMPQ2[32,16];
Rd_VPR128.8H[112,16] = TMPQ2[48,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.404 ZIP2 page C7-2306 line 129735 MATCH x0e007800/mask=xbf20fc00
# CONSTRUCT x4e007800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@8-0@9-2@10-4@11-6@12-8@13-10@14-12@15-14:1 swap &=$shuffle@8-1@9-3@10-5@11-7@12-9@13-11@14-13@15-15:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@1
# AUNIT --inst x4e007800/mask=xffe0fc00 --status pass
:zip2 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
{
TMPQ2 = Rm_VPR128.16B;
TMPQ1 = Rn_VPR128.16B;
# simd shuffle Rd_VPR128.16B = TMPQ1 (@8-0@9-2@10-4@11-6@12-8@13-10@14-12@15-14) lane size 1
Rd_VPR128.16B[0,8] = TMPQ1[64,8];
Rd_VPR128.16B[16,8] = TMPQ1[72,8];
Rd_VPR128.16B[32,8] = TMPQ1[80,8];
Rd_VPR128.16B[48,8] = TMPQ1[88,8];
Rd_VPR128.16B[64,8] = TMPQ1[96,8];
Rd_VPR128.16B[80,8] = TMPQ1[104,8];
Rd_VPR128.16B[96,8] = TMPQ1[112,8];
Rd_VPR128.16B[112,8] = TMPQ1[120,8];
# simd shuffle Rd_VPR128.16B = TMPQ2 (@8-1@9-3@10-5@11-7@12-9@13-11@14-13@15-15) lane size 1
Rd_VPR128.16B[8,8] = TMPQ2[64,8];
Rd_VPR128.16B[24,8] = TMPQ2[72,8];
Rd_VPR128.16B[40,8] = TMPQ2[80,8];
Rd_VPR128.16B[56,8] = TMPQ2[88,8];
Rd_VPR128.16B[72,8] = TMPQ2[96,8];
Rd_VPR128.16B[88,8] = TMPQ2[104,8];
Rd_VPR128.16B[104,8] = TMPQ2[112,8];
Rd_VPR128.16B[120,8] = TMPQ2[120,8];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.404 ZIP2 page C7-2306 line 129735 MATCH x0e007800/mask=xbf20fc00
# CONSTRUCT x4ec07800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:8 swap &=$shuffle@1-1:8
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@8
# AUNIT --inst x4ec07800/mask=xffe0fc00 --status pass
:zip2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
{
TMPQ2 = Rm_VPR128.2D;
TMPQ1 = Rn_VPR128.2D;
# simd shuffle Rd_VPR128.2D = TMPQ1 (@1-0) lane size 8
Rd_VPR128.2D[0,64] = TMPQ1[64,64];
# simd shuffle Rd_VPR128.2D = TMPQ2 (@1-1) lane size 8
Rd_VPR128.2D[64,64] = TMPQ2[64,64];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.404 ZIP2 page C7-2306 line 129735 MATCH x0e007800/mask=xbf20fc00
# CONSTRUCT x0e807800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:4 swap &=$shuffle@1-1:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@4
# AUNIT --inst x0e807800/mask=xffe0fc00 --status pass
:zip2 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
{
TMPD2 = Rm_VPR64.2S;
TMPD1 = Rn_VPR64.2S;
# simd shuffle Rd_VPR64.2S = TMPD1 (@1-0) lane size 4
Rd_VPR64.2S[0,32] = TMPD1[32,32];
# simd shuffle Rd_VPR64.2S = TMPD2 (@1-1) lane size 4
Rd_VPR64.2S[32,32] = TMPD2[32,32];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.404 ZIP2 page C7-2306 line 129735 MATCH x0e007800/mask=xbf20fc00
# CONSTRUCT x0e407800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@2-0@3-2:2 swap &=$shuffle@2-1@3-3:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@2
# AUNIT --inst x0e407800/mask=xffe0fc00 --status pass
:zip2 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
{
TMPD2 = Rm_VPR64.4H;
TMPD1 = Rn_VPR64.4H;
# simd shuffle Rd_VPR64.4H = TMPD1 (@2-0@3-2) lane size 2
Rd_VPR64.4H[0,16] = TMPD1[32,16];
Rd_VPR64.4H[32,16] = TMPD1[48,16];
# simd shuffle Rd_VPR64.4H = TMPD2 (@2-1@3-3) lane size 2
Rd_VPR64.4H[16,16] = TMPD2[32,16];
Rd_VPR64.4H[48,16] = TMPD2[48,16];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.404 ZIP2 page C7-2306 line 129735 MATCH x0e007800/mask=xbf20fc00
# CONSTRUCT x4e807800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@2-0@3-2:4 swap &=$shuffle@2-1@3-3:4
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@4
# AUNIT --inst x4e807800/mask=xffe0fc00 --status pass
:zip2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
{
TMPQ2 = Rm_VPR128.4S;
TMPQ1 = Rn_VPR128.4S;
# simd shuffle Rd_VPR128.4S = TMPQ1 (@2-0@3-2) lane size 4
Rd_VPR128.4S[0,32] = TMPQ1[64,32];
Rd_VPR128.4S[64,32] = TMPQ1[96,32];
# simd shuffle Rd_VPR128.4S = TMPQ2 (@2-1@3-3) lane size 4
Rd_VPR128.4S[32,32] = TMPQ2[64,32];
Rd_VPR128.4S[96,32] = TMPQ2[96,32];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.404 ZIP2 page C7-2306 line 129735 MATCH x0e007800/mask=xbf20fc00
# CONSTRUCT x0e007800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@4-0@5-2@6-4@7-6:1 swap &=$shuffle@4-1@5-3@6-5@7-7:1
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@1
# AUNIT --inst x0e007800/mask=xffe0fc00 --status pass
:zip2 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
{
TMPD2 = Rm_VPR64.8B;
TMPD1 = Rn_VPR64.8B;
# simd shuffle Rd_VPR64.8B = TMPD1 (@4-0@5-2@6-4@7-6) lane size 1
Rd_VPR64.8B[0,8] = TMPD1[32,8];
Rd_VPR64.8B[16,8] = TMPD1[40,8];
Rd_VPR64.8B[32,8] = TMPD1[48,8];
Rd_VPR64.8B[48,8] = TMPD1[56,8];
# simd shuffle Rd_VPR64.8B = TMPD2 (@4-1@5-3@6-5@7-7) lane size 1
Rd_VPR64.8B[8,8] = TMPD2[32,8];
Rd_VPR64.8B[24,8] = TMPD2[40,8];
Rd_VPR64.8B[40,8] = TMPD2[48,8];
Rd_VPR64.8B[56,8] = TMPD2[56,8];
zext_zd(Zd); # zero upper 24 bytes of Zd
}
# C7.2.404 ZIP2 page C7-2306 line 129735 MATCH x0e007800/mask=xbf20fc00
# CONSTRUCT x4e407800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@4-0@5-2@6-4@7-6:2 swap &=$shuffle@4-1@5-3@6-5@7-7:2
# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@2
# AUNIT --inst x4e407800/mask=xffe0fc00 --status pass
:zip2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
{
TMPQ2 = Rm_VPR128.8H;
TMPQ1 = Rn_VPR128.8H;
# simd shuffle Rd_VPR128.8H = TMPQ1 (@4-0@5-2@6-4@7-6) lane size 2
Rd_VPR128.8H[0,16] = TMPQ1[64,16];
Rd_VPR128.8H[32,16] = TMPQ1[80,16];
Rd_VPR128.8H[64,16] = TMPQ1[96,16];
Rd_VPR128.8H[96,16] = TMPQ1[112,16];
# simd shuffle Rd_VPR128.8H = TMPQ2 (@4-1@5-3@6-5@7-7) lane size 2
Rd_VPR128.8H[16,16] = TMPQ2[64,16];
Rd_VPR128.8H[48,16] = TMPQ2[80,16];
Rd_VPR128.8H[80,16] = TMPQ2[96,16];
Rd_VPR128.8H[112,16] = TMPQ2[112,16];
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.13 BFCVT page C7-1417 line 78462 MATCH x1e634000/mask=xfffffc00
# C7.2.69 FCVT page C7-1547 line 86009 MATCH x1e224000/mask=xff3e7c00
# CONSTRUCT x1e634000/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
# x1e634000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR
# SMACRO ARG1 ARG2 =float2float/1
# SMACRO(pseudo) ARG1 ARG2 =NEON_bfcvt/1
# b_0031=0001111001100011010000..........
:bfcvt Rd_FPR16, Rn_FPR32
is b_1031=0b0001111001100011010000 & Rd_FPR16 & Rn_FPR32 & Zd
{
Rd_FPR16 = float2float(Rn_FPR32);
zext_zh(Zd); # zero upper 30 bytes of Zd
}
# C7.2.14 BFCVTN, BFCVTN2 page C7-1418 line 78518 MATCH x0ea16800/mask=xbffffc00
# CONSTRUCT x0ea16800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# x0ea16800/mask=xbffffc00 NOT MATCHED BY ANY CONSTRUCTOR
# SMACRO ARG1 ARG2 =var =$float2float@4:8
# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@4
# b_0031=0.00111010100001011010..........
:bfcvtn Rd_VPR128.4S, Rn_VPR128.4H
is b_3131=0b0 & Q=0 & b_1029=0b00111010100001011010 & Rn_VPR128.4H & Rd_VPR128.4S & Zd
{
TMPQ1 = Rn_VPR128.4H;
# simd resize Rd_VPR128.4S = float2float(TMPQ1) (lane size 4 to 4)
Rd_VPR128.4S[0,32] = float2float(TMPQ1[0,32]);
Rd_VPR128.4S[32,32] = float2float(TMPQ1[32,32]);
Rd_VPR128.4S[64,32] = float2float(TMPQ1[64,32]);
Rd_VPR128.4S[96,32] = float2float(TMPQ1[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.14 BFCVTN, BFCVTN2 page C7-1418 line 78518 MATCH x0ea16800/mask=xbffffc00
# CONSTRUCT x4ea16800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
# x0ea16800/mask=xbffffc00 NOT MATCHED BY ANY CONSTRUCTOR
# SMACRO ARG1 ARG2 =var =$float2float@4:8
# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@4
:bfcvtn2 Rd_VPR128.4S, Rn_VPR128.8H
is b_3131=0b0 & Q=1 & b_1029=0b00111010100001011010 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
{
TMPQ1 = Rn_VPR128.8H;
# simd resize Rd_VPR128.4S = float2float(TMPQ1) (lane size 4 to 4)
Rd_VPR128.4S[0,32] = float2float(TMPQ1[0,32]);
Rd_VPR128.4S[32,32] = float2float(TMPQ1[32,32]);
Rd_VPR128.4S[64,32] = float2float(TMPQ1[64,32]);
Rd_VPR128.4S[96,32] = float2float(TMPQ1[96,32]);
zext_zq(Zd); # zero upper 16 bytes of Zd
}
# C7.2.15 BFDOT (by element) page C7-1420 line 78603 MATCH x0f40f000/mask=xbfc0f400
# CONSTRUCT x0f40f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# x0f40f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=0.00111101......1111.0..........
:bfdot Rd_VPR128.2S, Rn_VPR128.4H, , Re_VPR128.H.vIndexHL
is b_3131=0b0 & Q=0 & b_2229=0b00111101 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.4H & Rd_VPR128.2S
{
Rd_VPR128.2S = NEON_bfdot(Rn_VPR128.4H, Re_VPR128.H.vIndexHL);
}
# C7.2.15 BFDOT (by element) page C7-1420 line 78603 MATCH x0f40f000/mask=xbfc0f400
# CONSTRUCT x4f40f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
:bfdot Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128.H.vIndexHL
is b_3131=0b0 & Q=1 & b_2229=0b00111101 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8H & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_bfdot(Rn_VPR128.8H, Re_VPR128.H.vIndexHL);
}
# C7.2.16 BFDOT (vector) page C7-1422 line 78694 MATCH x2e40fc00/mask=xbfe0fc00
# CONSTRUCT x2e40fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# x2e40fc00/mask=xbfe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=0.101110010.....111111..........
:bfdot Rd_VPR128.2S, Rn_VPR128.4H, Rm_VPR128.4H
is b_3131=0b0 & Q=0 & b_2129=0b101110010 & Rm_VPR128.4H & b_1015=0b111111 & Rn_VPR128.4H & Rd_VPR128.2S
{
Rd_VPR128.2S = NEON_bfdot(Rn_VPR128.4H, Rm_VPR128.4H);
}
# C7.2.16 BFDOT (vector) page C7-1422 line 78694 MATCH x2e40fc00/mask=xbfe0fc00
# CONSTRUCT x6e40fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
:bfdot Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0b0 & Q=1 & b_2129=0b101110010 & Rm_VPR128.8H & b_1015=0b111111 & Rn_VPR128.8H & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_bfdot(Rn_VPR128.8H, Rm_VPR128.8H);
}
# C7.2.17 BFMLALB, BFMLALT (by element) page C7-1424 line 78780 MATCH x0fc0f000/mask=xbfc0f400
# CONSTRUCT x0fc0f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# x0fc0f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=0.00111111......1111.0..........
:bfmlalb Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0b0 & Q=0 & b_2229=0b00111111 & Re_VPR128Lo.H.vIndexHLM & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8H & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_bfmlalb(Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM);
}
# C7.2.17 BFMLALB, BFMLALT (by element) page C7-1424 line 78780 MATCH x0fc0f000/mask=xbfc0f400
# CONSTRUCT x4fc0f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
:bfmlalt Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
is b_3131=0b0 & Q=1 & b_2229=0b00111111 & Re_VPR128Lo.H.vIndexHLM & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8H & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_bfmlalt(Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM);
}
# C7.2.18 BFMLALB, BFMLALT (vector) page C7-1426 line 78870 MATCH x2ec0fc00/mask=xbfe0fc00
# CONSTRUCT x2ec0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# x2ec0fc00/mask=xbfe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=0.101110110.....111111..........
:bfmlalb Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0b0 & Q=0 & b_2129=0b101110110 & Rm_VPR128.8H & b_1015=0b111111 & Rn_VPR128.8H & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_bfmlalb(Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H);
}
# C7.2.18 BFMLALB, BFMLALT (vector) page C7-1426 line 78870 MATCH x2ec0fc00/mask=xbfe0fc00
# CONSTRUCT x6ec0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
:bfmlalt Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_3131=0b0 & Q=1 & b_2129=0b101110110 & Rm_VPR128.8H & b_1015=0b111111 & Rn_VPR128.8H & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_bfmlalt(Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H);
}
# C7.2.19 BFMMLA page C7-1427 line 78943 MATCH x6e40ec00/mask=xffe0fc00
# CONSTRUCT x6e40ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# x6e40ec00/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=01101110010.....111011..........
:bfmmla Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
is b_2131=0b01101110010 & Rm_VPR128.8H & b_1015=0b111011 & Rn_VPR128.8H & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_bfmmla(Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H);
}
# C7.2.147 FRINT32X (vector) page C7-1726 line 96547 MATCH x2e21e800/mask=xbfbffc00
# CONSTRUCT x2e21e800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES
# x2e21e800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=0.1011100.100001111010..........
:frint32x
is b_3131=0b0 & Q & b_2329=0b1011100 & b_22 & b_1021=0b100001111010 & Rn & Rd
unimpl
# C7.2.148 FRINT32X (scalar) page C7-1728 line 96636 MATCH x1e28c000/mask=xffbffc00
# CONSTRUCT x1e28c000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES
# x1e28c000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=000111100.101000110000..........
:frint32x
is b_2331=0b000111100 & b_22 & b_1021=0b101000110000 & Rn & Rd
unimpl
# C7.2.149 FRINT32Z (vector) page C7-1730 line 96730 MATCH x0e21e800/mask=xbfbffc00
# CONSTRUCT x0e21e800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES
# x0e21e800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=0.0011100.100001111010..........
:frint32z
is b_3131=0b0 & Q & b_2329=0b0011100 & b_22 & b_1021=0b100001111010 & Rn & Rd
unimpl
# C7.2.150 FRINT32Z (scalar) page C7-1732 line 96819 MATCH x1e284000/mask=xffbffc00
# CONSTRUCT x1e284000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES
# x1e284000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=000111100.101000010000..........
:frint32z
is b_2331=0b000111100 & b_22 & b_1021=0b101000010000 & Rn & Rd
unimpl
# C7.2.151 FRINT64X (vector) page C7-1734 line 96910 MATCH x2e21f800/mask=xbfbffc00
# CONSTRUCT x2e21f800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES
# x2e21f800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=0.1011100.100001111110..........
:frint64x
is b_3131=0b0 & Q & b_2329=0b1011100 & b_22 & b_1021=0b100001111110 & Rn & Rd
unimpl
# C7.2.152 FRINT64X (scalar) page C7-1736 line 96999 MATCH x1e29c000/mask=xffbffc00
# CONSTRUCT x1e29c000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES
# x1e29c000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=000111100.101001110000..........
:frint64x
is b_2331=0b000111100 & b_22 & b_1021=0b101001110000 & Rn & Rd
unimpl
# C7.2.153 FRINT64Z (vector) page C7-1738 line 97093 MATCH x0e21f800/mask=xbfbffc00
# CONSTRUCT x0e21f800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES
# x0e21f800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=0.0011100.100001111110..........
:frint64z
is b_3131=0b0 & Q & b_2329=0b0011100 & b_22 & b_1021=0b100001111110 & Rn & Rd
unimpl
# C7.2.154 FRINT64Z (scalar) page C7-1740 line 97182 MATCH x1e294000/mask=xffbffc00
# CONSTRUCT x1e294000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES
# x1e294000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=000111100.101001010000..........
:frint64z
is b_2331=0b000111100 & b_22 & b_1021=0b101001010000 & Rn & Rd
unimpl
# C7.2.278 SMMLA (vector) page C7-2006 line 112254 MATCH x4e80a400/mask=xffe0fc00
# CONSTRUCT x4e80a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# x4e80a400/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=01001110100.....101001..........
:smmla Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B
is b_2131=0b01001110100 & Rm_VPR128.16B & b_1015=0b101001 & Rn_VPR128.16B & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_smmla(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B);
}
# C7.2.336 SUDOT (by element) page C7-2163 line 121691 MATCH x0f00f000/mask=xbfc0f400
# CONSTRUCT x0f00f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# x0f00f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=0.00111100......1111.0..........
:sudot Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL
is b_3131=0b0 & Q=0 & b_2229=0b00111100 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8B & Rd_VPR128.2S
{
Rd_VPR128.2S = NEON_sudot(Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL);
}
# C7.2.336 SUDOT (by element) page C7-2163 line 121691 MATCH x0f00f000/mask=xbfc0f400
# CONSTRUCT x4f00f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
:sudot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL
is b_3131=0b0 & Q=1 & b_2229=0b00111100 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.16B & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_sudot(Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL);
}
# C7.2.370 UMMLA (vector) page C7-2235 line 125634 MATCH x6e80a400/mask=xffe0fc00
# CONSTRUCT x6e80a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# x6e80a400/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_ummla/3@1
# b_0031=01101110100.....101001..........
:ummla Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B
is b_2131=0b01101110100 & Rm_VPR128.16B & b_1015=0b101001 & Rn_VPR128.16B & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_ummla(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
# C7.2.388 USDOT (vector) page C7-2273 line 127924 MATCH x0e809c00/mask=xbfe0fc00
# CONSTRUCT x0e809c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# x0e809c00/mask=xbfe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=0.001110100.....100111..........
:usdot Rd_VPR128.2S, Rn_VPR128.8B, Rm_VPR128.8B
is b_3131=0b0 & Q=0 & b_2129=0b001110100 & Rm_VPR128.8B & b_1015=0b100111 & Rn_VPR128.8B & Rd_VPR128.2S
{
Rd_VPR128.2S = NEON_usdot(Rd_VPR128.2S, Rn_VPR128.8B, Rm_VPR128.8B);
}
# C7.2.388 USDOT (vector) page C7-2273 line 127924 MATCH x0e809c00/mask=xbfe0fc00
# CONSTRUCT x4e809c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
:usdot Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B
is b_3131=0b0 & Q=1 & b_2129=0b001110100 & Rn_VPR128.16B & b_1015=0b100111 & Rm_VPR128.16B & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_usdot(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B);
}
# C7.2.389 USDOT (by element) page C7-2275 line 128010 MATCH x0f80f000/mask=xbfc0f400
# CONSTRUCT x0f80f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
# x0f80f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=0.00111110......1111.0..........
:usdot Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL
is b_3131=0b0 & Q=0 & b_2229=0b00111110 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8B & Rd_VPR128.2S
{
Rd_VPR128.2S = NEON_usdot(Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL);
}
# C7.2.389 USDOT (by element) page C7-2275 line 128010 MATCH x0f80f000/mask=xbfc0f400
# CONSTRUCT x4f80f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
:usdot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL
is b_3131=0b0 & Q=1 & b_2229=0b00111110 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.16B & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_usdot(Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL);
}
# C7.2.393 USMMLA (vector) page C7-2285 line 128543 MATCH x4e80ac00/mask=xffe0fc00
# CONSTRUCT x4e80ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_usmmla/3@1
# x4e80ac00/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
# b_0031=01001110100.....101011..........
:usmmla Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B
is b_2131=0b01001110100 & Rm_VPR128.16B & b_1015=0b101011 & Rn_VPR128.16B & Rd_VPR128.4S
{
Rd_VPR128.4S = NEON_usmmla(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
}
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