465 lines
42 KiB
Plaintext
465 lines
42 KiB
Plaintext
define token gen_instr1(16)
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g_op13_3 = (13,15)
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g_op12_4 = (12,15)
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g_regsel11_1 = (11,11)
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g_op11_5 = (11,15)
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g_op10_6 = (10,15)
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g_regsel10_1 = (10,10)
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g_op9_7 = (9,15)
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g_rx9_4 = (9,12)
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g_opcode9_2 = (9,10)
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g_rs9_4 = (9,12)
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g_regsel9_1 = (9,9)
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g_offset9_4 = (9,12)
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g_disp9_4 = (9,12)
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g_rp9_4 = (9,12)
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g_update9_1 = (9,9)
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g_rb9_4 = (9,12)
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g_imm9_4 = (9,12)
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g_rd9_4 = (9,12)
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g_shift9_4 = (9,12)
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g_op8_1 = (8,8)
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g_op8_8 = (8,15)
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g_regsel8_1 = (8,8)
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g_op7_9 = (7,15)
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g_op7_2 = (7,8)
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g_regsel7_1 = (7,7)
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g_regsel6_1 = (6,6)
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g_regsel5_1 = (5,5)
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g_op5_4 = (5,8)
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g_imm4_1 = (4,4)
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g_disp4_5 = (4,8)
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g_imm4_6 = (4,9)
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g_shift4_1 = (4,4)
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g_imm4_8 = (4,11)
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g_disp4_1 = (4,4)
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g_offset4_1 = (4,4)
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g_disp4_4 = (4,7)
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g_op4_12 = (4,15)
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g_disp4_8 = (4,11)
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g_disp4_3 = (4,6)
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g_regsel4_1 = (4,4)
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g_imm4_3 = (4,6)
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g_op4_5 = (4,8)
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g_offset4_5 = (4,8)
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g_cond4_4 = (4,7)
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g_disp4_7 = (4,10)
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g_op3_1 = (3,3)
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g_op3_6 = (3,8)
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g_returnflag3_1 = (3,3)
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g_op2_2 = (2,3)
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g_rd1_3 = (1,3)
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g_rs1_3 = (1,3)
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g_ri0_4 = (0,3)
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g_cond0_4 = (0,3)
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g_shift0_4 = (0,3)
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g_op0_16 = (0,15)
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g_op0_9 = (0,8)
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g_op0_1 = (0,0)
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g_offset0_4 = (0,3)
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g_rs0_4 = (0,3)
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g_cond0_3 = (0,2)
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g_op0_3 = (0,2)
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g_opcode0_4 = (0,3)
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g_rd0_4 = (0,3)
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g_shift0_3 = (0,2)
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g_rp0_4 = (0,3)
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g_ry0_4 = (0,3)
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g_disp0_2 = (0,1)
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g_op0_4 = (0,3)
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;
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define token gen_instr2(16)
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eg_regsel15_1 = (15,15)
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eg_offset15_1 = (15,15)
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eg_regsel14_1 = (14,14)
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eg_op14_2 = (14,15)
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eg_op13_3 = (13,15)
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eg_xpart13_1 = (13,13)
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eg_cop13_3 = (13,15)
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eg_regsel13_1 = (13,13)
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eg_disp12_4 = (12,15)
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eg_op12_4 = (12,15)
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eg_regsel12_1 = (12,12)
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eg_op12_1 = (12,12)
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eg_update12_1 = (12,12)
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eg_ypart12_1 = (12,12)
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eg_cond12_4 = (12,15)
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eg_opcode12_1 = (12,12)
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eg_opcode11_5 = (11,15)
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eg_regsel11_1 = (11,11)
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eg_regsel10_1 = (10,10)
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eg_op10_6 = (10,15)
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eg_regsel9_1 = (9,9)
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eg_op9_7 = (9,15)
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eg_rd9_3 = (9,11)
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eg_rs9_3 = (9,11)
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eg_op9_3 = (9,11)
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eg_op8_1 = (8,8)
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eg_op8_4 = (8,11)
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eg_rd8_4 = (8,11)
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eg_op8_8 = (8,15)
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eg_cond8_4 = (8,11)
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eg_ri8_4 = (8,11)
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eg_regsel8_1 = (8,8)
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eg_rs8_4 = (8,11)
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eg_regsel7_1 = (7,7)
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eg_op6_3 = (6,8)
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eg_regsel6_1 = (6,6)
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eg_op6_2 = (6,7)
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eg_op6_10 = (6,15)
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eg_op5_11 = (5,15)
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eg_regsel5_1 = (5,5)
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eg_offset5_5 = (5,9)
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eg_xpart5_1 = (5,5)
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eg_regsel4_1 = (4,4)
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eg_rx4_4 = (4,7)
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eg_disp4_8 = (4,11)
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eg_ypart4_1 = (4,4)
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eg_shift4_5 = (4,8)
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eg_cond4_4 = (4,7)
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eg_returnflag4_1 = (4,4)
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eg_op4_12 = (4,15)
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eg_op4_4 = (4,7)
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eg_shift4_2 = (4,5)
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eg_regsel3_1 = (3,3)
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eg_regsel2_1 = (2,2)
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eg_regsel1_1 = (1,1)
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eg_ri0_4 = (0,3)
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eg_opcode0_8 = (0,7)
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eg_rd0_4 = (0,3)
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eg_imm0_8 = (0,7)
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eg_shift0_5 = (0,4)
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eg_regsel0_1 = (0,0)
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eg_disp0_16 = (0,15)
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eg_disp0_12 = (0,11)
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eg_disp0_8 = (0,7)
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eg_bits0_5 = (0,4)
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eg_disp0_9 = (0,8)
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eg_imm0_15 = (0,14)
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eg_rs0_4 = (0,3)
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eg_rb0_4 = (0,3)
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eg_offset0_5 = (0,4)
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eg_op0_8 = (0,7)
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eg_imm0_16 = (0,15)
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eg_op0_9 = (0,8)
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eg_ry0_4 = (0,3)
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eg_op0_16 = (0,15)
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eg_dbgregaddr0_8 = (0,7)
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eg_disp0_11 = (0,10)
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eg_rp0_4 = (0,3)
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eg_op0_4 = (0,3)
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;
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#:ABS g_rd0_4 is g_op4_12=0x5c4 & g_rd0_4 unimpl
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#:ACALL g_disp4_8 is g_op12_4=0xd & g_disp4_8 & g_op0_4=0x0 unimpl
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#:ACR g_rd0_4 is g_op4_12=0x5c0 & g_rd0_4 unimpl
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#:ADC g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x4 & eg_rd0_4 unimpl
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#:ADD g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 unimpl
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#:ADD g_rx9_4, g_ry0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x0 & eg_shift4_2 & eg_rd0_4 unimpl
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#:ADD_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x0 & eg_rd0_4 unimpl
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#:ADDABS g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xe4 & eg_rd0_4 unimpl
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#:ADDHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x38 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:AND g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x6 & g_rd0_4 unimpl
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#:AND g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x0 & eg_shift4_5 & eg_rd0_4 unimpl
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#:AND g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x1 & eg_shift4_5 & eg_rd0_4 unimpl
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#:AND_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x2 & eg_rd0_4 unimpl
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#:ANDH g_update9_1, g_rd0_4, eg_imm0_16 is g_op10_6=0x39 & g_update9_1 & g_op4_5=0x1 & g_rd0_4 ; eg_imm0_16 unimpl
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#:ANDL g_update9_1, g_rd0_4, eg_imm0_16 is g_op10_6=0x38 & g_update9_1 & g_op4_5=0x1 & g_rd0_4 ; eg_imm0_16 unimpl
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#:ANDN g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x8 & g_rd0_4 unimpl
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#:ASR g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x84 & eg_rd0_4 unimpl
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#:ASR g_shift9_4, g_shift4_1, g_rd0_4 is g_op13_3=0x5 & g_shift9_4 & g_op5_4=0xa & g_shift4_1 & g_rd0_4 unimpl
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#:ASR g_rs9_4, g_rd0_4, eg_shift0_5 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op5_11=0xa0 & eg_shift0_5 unimpl
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#:BFEXTS g_rd9_4, g_rs0_4, eg_offset5_5, eg_bits0_5 is g_op13_3=0x7 & g_rd9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op10_6=0x2c & eg_offset5_5 & eg_bits0_5 unimpl
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#:BFEXTU g_rd9_4, g_rs0_4, eg_offset5_5, eg_bits0_5 is g_op13_3=0x7 & g_rd9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op10_6=0x30 & eg_offset5_5 & eg_bits0_5 unimpl
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#:BFINS g_rd9_4, g_rs0_4, eg_offset5_5, eg_bits0_5 is g_op13_3=0x7 & g_rd9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op10_6=0x34 & eg_offset5_5 & eg_bits0_5 unimpl
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#:BLD g_rd0_4, eg_offset0_5 is g_op4_12=0xedb & g_rd0_4 ; eg_op5_11=0x0 & eg_offset0_5 unimpl
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#:BR_COND g_disp4_8, g_cond0_3 is g_op12_4=0xc & g_disp4_8 & g_op3_1=0x0 & g_cond0_3 unimpl
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#:BR_COND g_disp9_4, g_disp4_1, g_cond0_4, eg_disp0_16 is g_op13_3=0x7 & g_disp9_4 & g_op5_4=0x4 & g_disp4_1 & g_cond0_4 ; eg_disp0_16 unimpl
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#:BREAKPOINT is g_op0_16=0xd673 unimpl
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#:BREV g_rd0_4 is g_op4_12=0x5c9 & g_rd0_4 unimpl
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#:BST g_rd0_4, eg_offset0_5 is g_op4_12=0xefb & g_rd0_4 ; eg_op5_11=0x0 & eg_offset0_5 unimpl
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#:CACHE g_rp0_4, eg_opcode11_5, eg_disp0_11 is g_op4_12=0xf41 & g_rp0_4 ; eg_opcode11_5 & eg_disp0_11 unimpl
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#:CASTS.H g_rd0_4 is g_op4_12=0x5c8 & g_rd0_4 unimpl
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#:CASTS.B g_rd0_4 is g_op4_12=0x5c6 & g_rd0_4 unimpl
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#:CASTU.H g_rd0_4 is g_op4_12=0x5c7 & g_rd0_4 unimpl
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#:CASTU.B g_rd0_4 is g_op4_12=0x5c5 & g_rd0_4 unimpl
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#:CBR g_offset9_4, g_offset4_1, g_rd0_4 is g_op13_3=0x5 & g_offset9_4 & g_op5_4=0xe & g_offset4_1 & g_rd0_4 unimpl
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#:CLZ g_rs9_4, g_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op0_16=0x1200 unimpl
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#:COM g_rd0_4 is g_op4_12=0x5cd & g_rd0_4 unimpl
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#:COP g_opcode9_2, g_opcode0_4, eg_cop13_3, eg_opcode12_1, eg_rd8_4, eg_rx4_4, eg_ry0_4 is g_op11_5=0x1c & g_opcode9_2 & g_op4_5=0x1a & g_opcode0_4 ; eg_cop13_3 & eg_opcode12_1 & eg_rd8_4 & eg_rx4_4 & eg_ry0_4 unimpl
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#:CP.B g_rs9_4, g_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op0_16=0x1800 unimpl
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#:CP.H g_rs9_4, g_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op0_16=0x1900 unimpl
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#:CP.W g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x3 & g_rd0_4 unimpl
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#:CP.W g_imm4_6, g_rd0_4 is g_op10_6=0x16 & g_imm4_6 & g_rd0_4 unimpl
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#:CP.W g_imm9_4, g_imm4_1, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_imm9_4 & g_op5_4=0x2 & g_imm4_1 & g_rd0_4 ; eg_imm0_16 unimpl
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#:CPC g_rs9_4, g_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op0_16=0x1300 unimpl
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#:CPC g_rd0_4 is g_op4_12=0x5c2 & g_rd0_4 unimpl
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#:CSRF g_offset4_5 is g_op9_7=0x6a & g_offset4_5 & g_op0_4=0x3 unimpl
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#:CSRFCZ g_offset4_5 is g_op9_7=0x68 & g_offset4_5 & g_op0_4=0x3 unimpl
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#:DIVS g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xc0 & eg_rd0_4 unimpl
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#:DIVU g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xd0 & eg_rd0_4 unimpl
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#:EOR g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x5 & g_rd0_4 unimpl
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#:EOR g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x10 & eg_shift4_5 & eg_rd0_4 unimpl
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#:EOR g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x11 & eg_shift4_5 & eg_rd0_4 unimpl
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#:EOR_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x4 & eg_rd0_4 unimpl
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#:EORH g_rd0_4, eg_imm0_16 is g_op4_12=0xee1 & g_rd0_4 ; eg_imm0_16 unimpl
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#:EORL g_rd0_4, eg_imm0_16 is g_op4_12=0xec1 & g_rd0_4 ; eg_imm0_16 unimpl
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#:FRS is g_op0_16=0xd743 unimpl
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#:ICALL g_rd0_4 is g_op4_12=0x5d1 & g_rd0_4 unimpl
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#:INCJOSP g_imm4_3 is g_op7_9=0x1ad & g_imm4_3 & g_op0_4=0x3 unimpl
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#:LD.D g_rp9_4, g_rd1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x10 & g_rd1_3 & g_op0_1=0x1 unimpl
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#:LD.D g_rp9_4, g_rd1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x11 & g_rd1_3 & g_op0_1=0x0 unimpl
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#:LD.D g_rp9_4, g_rd1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x10 & g_rd1_3 & g_op0_1=0x0 unimpl
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#:LD.D g_rp9_4, g_rd1_3, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0xe & g_rd1_3 & g_op0_1=0x0 ; eg_disp0_16 unimpl
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#:LD.D g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x8 & eg_shift4_2 & eg_rd0_4 unimpl
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#:LD.SB g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x12 & g_rd0_4 ; eg_disp0_16 unimpl
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#:LD.SB g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x18 & eg_shift4_2 & eg_rd0_4 unimpl
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#:LD.SB_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x3 & eg_disp0_9 unimpl
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#:LD.UB g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x13 & g_rd0_4 unimpl
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#:LD.UB g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x17 & g_rd0_4 unimpl
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#:LD.UB g_rp9_4, g_disp4_3, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op7_2=0x3 & g_disp4_3 & g_rd0_4 unimpl
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#:LD.UB g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x13 & g_rd0_4 ; eg_disp0_16 unimpl
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#:LD.UB g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x1c & eg_shift4_2 & eg_rd0_4 unimpl
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#:LD.UB_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x4 & eg_disp0_9 unimpl
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#:LD.SH g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x11 & g_rd0_4 unimpl
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#:LD.SH g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x15 & g_rd0_4 unimpl
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#:LD.SH g_rp9_4, g_disp4_3, g_rd0_4 is g_op13_3=0x4 & g_rp9_4 & g_op7_2=0x0 & g_disp4_3 & g_rd0_4 unimpl
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#:LD.SH g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x10 & g_rd0_4 ; eg_disp0_16 unimpl
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#:LD.SH g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x10 & eg_shift4_2 & eg_rd0_4 unimpl
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#:LD.SH_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x1 & eg_disp0_9 unimpl
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#:LD.UH g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x12 & g_rd0_4 unimpl
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#:LD.UH g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x16 & g_rd0_4 unimpl
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#:LD.UH g_rp9_4, g_disp4_3, g_rd0_4 is g_op13_3=0x4 & g_rp9_4 & g_op7_2=0x1 & g_disp4_3 & g_rd0_4 unimpl
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#:LD.UH g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x11 & g_rd0_4 ; eg_disp0_16 unimpl
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#:LD.UH g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x14 & eg_shift4_2 & eg_rd0_4 unimpl
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#:LD.UH_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x2 & eg_disp0_9 unimpl
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#:LD.W g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x10 & g_rd0_4 unimpl
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#:LD.W g_rp9_4, g_rd0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0x14 & g_rd0_4 unimpl
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#:LD.W g_rp9_4, g_disp4_5, g_rd0_4 is g_op13_3=0x3 & g_rp9_4 & g_disp4_5 & g_rd0_4 unimpl
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#:LD.W g_rp9_4, g_rd0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0xf & g_rd0_4 ; eg_disp0_16 unimpl
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#:LD.W g_rb9_4, g_ri0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0xc & eg_shift4_2 & eg_rd0_4 unimpl
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#:LD.W g_rb9_4, g_ri0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x3e & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:LD.W_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x0 & eg_disp0_9 unimpl
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#:LDC.D g_rp0_4, eg_cop13_3, eg_rd9_3, eg_disp0_8 is g_op4_12=0xe9a & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rd9_3 & eg_op8_1=0x0 & eg_disp0_8 unimpl
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#:LDC.D g_rp0_4, eg_cop13_3, eg_rd9_3 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd9_3 & eg_op0_9=0x50 unimpl
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#:LDC.D g_rp0_4, eg_cop13_3, eg_rd9_3, eg_shift4_2, eg_ri0_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rd9_3 & eg_op6_3=0x1 & eg_shift4_2 & eg_ri0_4 unimpl
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#:LDC.W g_rp0_4, eg_cop13_3, eg_rd8_4, eg_disp0_8 is g_op4_12=0xe9a & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd8_4 & eg_disp0_8 unimpl
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#:LDC.W g_rp0_4, eg_cop13_3, eg_rd8_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd8_4 & eg_op0_8=0x40 unimpl
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#:LDC.W g_rp0_4, eg_cop13_3, eg_rd8_4, eg_shift4_2, eg_ri0_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rd8_4 & eg_op6_2=0x0 & eg_shift4_2 & eg_ri0_4 unimpl
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#:LDC0.D g_rp0_4, eg_disp12_4, eg_rd9_3, eg_disp0_8 is g_op4_12=0xf3a & g_rp0_4 ; eg_disp12_4 & eg_rd9_3 & eg_op8_1=0x0 & eg_disp0_8 unimpl
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#:LDC0.W g_rp0_4, eg_disp12_4, eg_rd8_4, eg_disp0_8 is g_op4_12=0xf1a & g_rp0_4 ; eg_disp12_4 & eg_rd8_4 & eg_disp0_8 unimpl
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#:LDCM.D g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x4 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl
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#:LDCM.W g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl
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#:LDCM.W g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x0 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl
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#:LDDPC g_disp4_7, g_rd0_4 is g_op11_5=0x9 & g_disp4_7 & g_rd0_4 unimpl
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#:LDDSP g_disp4_7, g_rd0_4 is g_op11_5=0x8 & g_disp4_7 & g_rd0_4 unimpl
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#:LDINS.B g_rp9_4, g_rd0_4, eg_xpart13_1, eg_ypart12_1, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op14_2=0x1 & eg_xpart13_1 & eg_ypart12_1 & eg_disp0_12 unimpl
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#:LDINS.H g_rp9_4, g_rd0_4, eg_ypart12_1, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op13_3=0x0 & eg_ypart12_1 & eg_disp0_12 unimpl
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#:LDM g_update9_1, g_rp0_4, eg_regsel15_1, eg_regsel14_1, eg_regsel13_1, eg_regsel12_1, eg_regsel11_1, eg_regsel10_1, eg_regsel9_1, eg_regsel8_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op10_6=0x38 & g_update9_1 & g_op4_5=0x1c & g_rp0_4 ; eg_regsel15_1 & eg_regsel14_1 & eg_regsel13_1 & eg_regsel12_1 & eg_regsel11_1 & eg_regsel10_1 & eg_regsel9_1 & eg_regsel8_1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl
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#:LDMTS g_update9_1, g_rp0_4, eg_regsel15_1, eg_regsel14_1, eg_regsel13_1, eg_regsel12_1, eg_regsel11_1, eg_regsel10_1, eg_regsel9_1, eg_regsel8_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op10_6=0x39 & g_update9_1 & g_op4_5=0x1c & g_rp0_4 ; eg_regsel15_1 & eg_regsel14_1 & eg_regsel13_1 & eg_regsel12_1 & eg_regsel11_1 & eg_regsel10_1 & eg_regsel9_1 & eg_regsel8_1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl
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#:LDSWP.SH g_rp9_4, g_rd0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op12_4=0x2 & eg_disp0_12 unimpl
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#:LDSWP.UH g_rp9_4, g_rd0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op12_4=0x3 & eg_disp0_12 unimpl
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#:LDSWP.W g_rp9_4, g_rd0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rd0_4 ; eg_op12_4=0x8 & eg_disp0_12 unimpl
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#:LSL g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x94 & eg_rd0_4 unimpl
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#:LSL g_shift9_4, g_shift4_1, g_rd0_4 is g_op13_3=0x5 & g_shift9_4 & g_op5_4=0xb & g_shift4_1 & g_rd0_4 unimpl
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#:LSL g_rs9_4, g_rd0_4, eg_shift0_5 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op5_11=0xa8 & eg_shift0_5 unimpl
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#:LSR g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xa4 & eg_rd0_4 unimpl
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#:LSR g_shift9_4, g_shift4_1, g_rd0_4 is g_op13_3=0x5 & g_shift9_4 & g_op5_4=0xc & g_shift4_1 & g_rd0_4 unimpl
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#:LSR g_rs9_4, g_rd0_4, eg_shift0_5 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op5_11=0xb0 & eg_shift0_5 unimpl
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#:MAC g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x34 & eg_rd0_4 unimpl
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#:MACHH.D g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x16 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MACHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x12 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MACS.D g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x54 & eg_rd0_4 unimpl
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#:MACSATHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x1a & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MACU.D g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x74 & eg_rd0_4 unimpl
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#:MACWH.D g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x64 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MAX g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xc4 & eg_rd0_4 unimpl
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#:MCALL g_rp0_4, eg_disp0_16 is g_op4_12=0xf01 & g_rp0_4 ; eg_disp0_16 unimpl
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#:MEMC g_offset0_4, eg_offset15_1, eg_imm0_15 is g_op4_12=0xf61 & g_offset0_4 ; eg_offset15_1 & eg_imm0_15 unimpl
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#:MEMS g_offset0_4, eg_offset15_1, eg_imm0_15 is g_op4_12=0xf81 & g_offset0_4 ; eg_offset15_1 & eg_imm0_15 unimpl
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#:MEMT g_offset0_4, eg_offset15_1, eg_imm0_15 is g_op4_12=0xfa1 & g_offset0_4 ; eg_offset15_1 & eg_imm0_15 unimpl
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#:MFDR g_rd0_4, eg_dbgregaddr0_8 is g_op4_12=0xe5b & g_rd0_4 ; eg_op8_8=0x0 & eg_dbgregaddr0_8 unimpl
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#:MFSR g_rd0_4, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xe1b & g_rd0_4 ; eg_op8_8=0x0 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl
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#:MIN g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xd4 & eg_rd0_4 unimpl
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#:MOV g_imm4_8, g_rd0_4 is g_op12_4=0x3 & g_imm4_8 & g_rd0_4 unimpl
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#:MOV g_imm9_4, g_imm4_1, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_imm9_4 & g_op5_4=0x3 & g_imm4_1 & g_rd0_4 ; eg_imm0_16 unimpl
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#:MOV g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x9 & g_rd0_4 unimpl
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#:MOV_COND g_rs9_4, g_rd0_4, eg_cond4_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op8_8=0x17 & eg_cond4_4 & eg_op0_4=0x0 unimpl
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#:MOV_COND g_rd0_4, eg_cond8_4, eg_imm0_8 is g_op4_12=0xf9b & g_rd0_4 ; eg_op12_4=0x0 & eg_cond8_4 & eg_imm0_8 unimpl
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#:MOVHI g_rd0_4, eg_imm0_16 is g_op4_12=0xfc1 & g_rd0_4 ; eg_imm0_16 unimpl
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#:MTDR g_rs0_4, eg_dbgregaddr0_8 is g_op4_12=0xe7b & g_rs0_4 ; eg_op8_8=0x0 & eg_dbgregaddr0_8 unimpl
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#:MTSR g_rs0_4, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xe3b & g_rs0_4 ; eg_op8_8=0x0 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl
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#:MUL g_rs9_4, g_rd0_4 is g_op13_3=0x5 & g_rs9_4 & g_op4_5=0x13 & g_rd0_4 unimpl
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#:MUL g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x24 & eg_rd0_4 unimpl
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#:MUL g_rs9_4, g_rd0_4, eg_imm0_8 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op8_8=0x10 & eg_imm0_8 unimpl
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#:MULHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x1e & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MULNHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x6 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MULNWH.D g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x14 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MULS.D g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x44 & eg_rd0_4 unimpl
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#:MULSATHH.H g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x22 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MULSATHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x26 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MULSATRNDHH.H g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x2a & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MULSATRNDWH.W g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x5c & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MULSATWH.W g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x74 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MULU.D g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x64 & eg_rd0_4 unimpl
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#:MULWH.D g_rx9_4, g_ry0_4, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op5_11=0x6c & eg_ypart4_1 & eg_rd0_4 unimpl
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#:MUSFR g_rs0_4 is g_op4_12=0x5d3 & g_rs0_4 unimpl
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#:MUSTR g_rd0_4 is g_op4_12=0x5d2 & g_rd0_4 unimpl
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#:MVCR.D g_rd1_3, eg_cop13_3, eg_rs9_3 is g_op4_12=0xefa & g_rd1_3 & g_op0_1=0x0 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs9_3 & eg_op0_9=0x10 unimpl
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#:MVCR.W g_rd0_4, eg_cop13_3, eg_rs8_4 is g_op4_12=0xefa & g_rd0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs8_4 & eg_op0_8=0x0 unimpl
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#:MVRC.D g_rs1_3, eg_cop13_3, eg_rd9_3 is g_op4_12=0xefa & g_rs1_3 & g_op0_1=0x0 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd9_3 & eg_op0_9=0x30 unimpl
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#:MVRC.W g_rs0_4, eg_cop13_3, eg_rd8_4 is g_op4_12=0xefa & g_rs0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rd8_4 & eg_op0_8=0x20 unimpl
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#:NEG g_rd0_4 is g_op4_12=0x5c3 & g_rd0_4 unimpl
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#:NOP is g_op0_16=0xd703 unimpl
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#:OR g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x4 & g_rd0_4 unimpl
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#:OR g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x8 & eg_shift4_5 & eg_rd0_4 unimpl
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#:OR g_rx9_4, g_ry0_4, eg_shift4_5, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op9_7=0x9 & eg_shift4_5 & eg_rd0_4 unimpl
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#:OR_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x3 & eg_rd0_4 unimpl
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#:ORH g_rd0_4, eg_imm0_16 is g_op4_12=0xea1 & g_rd0_4 ; eg_imm0_16 unimpl
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#:ORL g_rd0_4, eg_imm0_16 is g_op4_12=0xe81 & g_rd0_4 ; eg_imm0_16 unimpl
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#:PABS.SB g_rs0_4, eg_rd0_4 is g_op4_12=0xe00 & g_rs0_4 ; eg_op4_12=0x23e & eg_rd0_4 unimpl
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#:PABS.SH g_rs0_4, eg_rd0_4 is g_op4_12=0xe00 & g_rs0_4 ; eg_op4_12=0x23f & eg_rd0_4 unimpl
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#:PACKSH.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x24c & eg_rd0_4 unimpl
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#:PACKSH.SB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x24d & eg_rd0_4 unimpl
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#:PACKW.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x247 & eg_rd0_4 unimpl
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#:PADD.B g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x230 & eg_rd0_4 unimpl
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#:PADD.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x200 & eg_rd0_4 unimpl
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#:PADDH.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x236 & eg_rd0_4 unimpl
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#:PADDH.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20c & eg_rd0_4 unimpl
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#:PADDS.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x234 & eg_rd0_4 unimpl
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#:PADDS.SB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x232 & eg_rd0_4 unimpl
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#:PADDS.UH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x208 & eg_rd0_4 unimpl
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#:PADDS.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x204 & eg_rd0_4 unimpl
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#:PADDSUB.H g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x84 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:PADDSUBH.SH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x8a & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:PADDSUBS.UH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x88 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:PADDSUBS.SH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x86 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:PADDX.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x202 & eg_rd0_4 unimpl
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#:PADDXH.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20e & eg_rd0_4 unimpl
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#:PADDXS.UH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20a & eg_rd0_4 unimpl
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#:PADDXS.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x206 & eg_rd0_4 unimpl
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#:PASR.B g_rs9_4, g_shift0_3, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op3_6=0x0 & g_shift0_3 ; eg_op4_12=0x241 & eg_rd0_4 unimpl
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#:PASR.H g_rs9_4, g_shift0_4, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_shift0_4 ; eg_op4_12=0x244 & eg_rd0_4 unimpl
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#:PAVG.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x23c & eg_rd0_4 unimpl
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#:PAVG.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x23d & eg_rd0_4 unimpl
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#:PLSL.B g_rs9_4, g_shift0_3, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op3_6=0x0 & g_shift0_3 ; eg_op4_12=0x242 & eg_rd0_4 unimpl
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#:PLSL.H g_rs9_4, g_shift0_4, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_shift0_4 ; eg_op4_12=0x245 & eg_rd0_4 unimpl
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#:PLSR.B g_rs9_4, g_shift0_3, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op3_6=0x0 & g_shift0_3 ; eg_op4_12=0x243 & eg_rd0_4 unimpl
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#:PLSR.H g_rs9_4, g_shift0_4, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_shift0_4 ; eg_op4_12=0x246 & eg_rd0_4 unimpl
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#:PMAX.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x238 & eg_rd0_4 unimpl
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#:PMAX.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x239 & eg_rd0_4 unimpl
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#:PMIN.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x23a & eg_rd0_4 unimpl
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#:PMIN.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x23b & eg_rd0_4 unimpl
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#:POPJC is g_op0_16=0xd713 unimpl
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#:POPM g_regsel11_1, g_regsel10_1, g_regsel9_1, g_regsel8_1, g_regsel7_1, g_regsel6_1, g_regsel5_1, g_regsel4_1, g_returnflag3_1 is g_op12_4=0xd & g_regsel11_1 & g_regsel10_1 & g_regsel9_1 & g_regsel8_1 & g_regsel7_1 & g_regsel6_1 & g_regsel5_1 & g_regsel4_1 & g_returnflag3_1 & g_op0_3=0x2 unimpl
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#:PREF g_rp0_4, eg_disp0_16 is g_op4_12=0xf21 & g_rp0_4 ; eg_disp0_16 unimpl
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#:PSAD g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x240 & eg_rd0_4 unimpl
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#:PSUB.B g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x231 & eg_rd0_4 unimpl
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#:PSUB.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x201 & eg_rd0_4 unimpl
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#:PSUBADD.H g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x85 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:PSUBADDH.SH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x8b & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:PSUBADDS.UH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x89 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:PSUBADDS.SH g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x87 & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:PSUBH.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x237 & eg_rd0_4 unimpl
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#:PSUBH.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20d & eg_rd0_4 unimpl
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#:PSUBS.UB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x235 & eg_rd0_4 unimpl
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#:PSUBS.SB g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x233 & eg_rd0_4 unimpl
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#:PSUBS.UH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x209 & eg_rd0_4 unimpl
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#:PSUBS.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x205 & eg_rd0_4 unimpl
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#:PSUBX.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x203 & eg_rd0_4 unimpl
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#:PSUBXH.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20f & eg_rd0_4 unimpl
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#:PSUBXS.UH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x20b & eg_rd0_4 unimpl
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#:PSUBXS.SH g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x207 & eg_rd0_4 unimpl
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#:PUNPCKUB.H g_rs9_4, eg_returnflag4_1, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op0_9=0x0 ; eg_op5_11=0x124 & eg_returnflag4_1 & eg_rd0_4 unimpl
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#:PUNPCKSB.H g_rs9_4, eg_returnflag4_1, eg_rd0_4 is g_op13_3=0x7 & g_rs9_4 & g_op0_9=0x0 ; eg_op5_11=0x125 & eg_returnflag4_1 & eg_rd0_4 unimpl
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#:PUSHJC is g_op0_16=0xd723 unimpl
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#:PUSHM g_regsel11_1, g_regsel10_1, g_regsel9_1, g_regsel8_1, g_regsel7_1, g_regsel6_1, g_regsel5_1, g_regsel4_1 is g_op12_4=0xd & g_regsel11_1 & g_regsel10_1 & g_regsel9_1 & g_regsel8_1 & g_regsel7_1 & g_regsel6_1 & g_regsel5_1 & g_regsel4_1 & g_op0_4=0x1 unimpl
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#:RCALL g_disp4_8, g_disp0_2 is g_op12_4=0xc & g_disp4_8 & g_op2_2=0x3 & g_disp0_2 unimpl
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#:RCALL g_disp9_4, g_disp4_1, eg_disp0_16 is g_op13_3=0x7 & g_disp9_4 & g_op5_4=0x5 & g_disp4_1 & g_op0_4=0x0 ; eg_disp0_16 unimpl
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#:RET_COND g_cond4_4, g_rs0_4 is g_op8_8=0x5e & g_cond4_4 & g_rs0_4 unimpl
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#:RETD is g_op0_16=0xd623 unimpl
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#:RETE is g_op0_16=0xd603 unimpl
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#:RETJ is g_op0_16=0xd633 unimpl
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#:RETS is g_op0_16=0xd613 unimpl
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#:RJMP g_disp4_8, g_disp0_2 is g_op12_4=0xc & g_disp4_8 & g_op2_2=0x2 & g_disp0_2 unimpl
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#:ROL g_rd0_4 is g_op4_12=0x5cf & g_rd0_4 unimpl
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#:ROR g_rd0_4 is g_op4_12=0x5d0 & g_rd0_4 unimpl
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#:RSUB g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x2 & g_rd0_4 unimpl
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#:RSUB g_rs9_4, g_rd0_4, eg_imm0_8 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0x0 & g_rd0_4 ; eg_op8_8=0x11 & eg_imm0_8 unimpl
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#:RSUB_COND g_rd0_4, eg_cond8_4, eg_imm0_8 is g_op4_12=0xfbb & g_rd0_4 ; eg_op12_4=0x0 & eg_cond8_4 & eg_imm0_8 unimpl
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#:SATADD.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x2c & eg_rd0_4 unimpl
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#:SATADD.W g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xc & eg_rd0_4 unimpl
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#:SATRNDS g_rd0_4, eg_offset5_5, eg_shift0_5 is g_op4_12=0xf3b & g_rd0_4 ; eg_op10_6=0x0 & eg_offset5_5 & eg_shift0_5 unimpl
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#:SATRNDU g_rd0_4, eg_offset5_5, eg_shift0_5 is g_op4_12=0xf3b & g_rd0_4 ; eg_op10_6=0x1 & eg_offset5_5 & eg_shift0_5 unimpl
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#:SATS g_rd0_4, eg_offset5_5, eg_shift0_5 is g_op4_12=0xf1b & g_rd0_4 ; eg_op10_6=0x0 & eg_offset5_5 & eg_shift0_5 unimpl
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#:SATSUB.H g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x3c & eg_rd0_4 unimpl
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#:SATSUB.W g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x1c & eg_rd0_4 unimpl
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#:SATSUB.W g_rs9_4, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0xd & g_rd0_4 ; eg_imm0_16 unimpl
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#:SATU g_rd0_4, eg_offset5_5, eg_shift0_5 is g_op4_12=0xf1b & g_rd0_4 ; eg_op10_6=0x1 & eg_offset5_5 & eg_shift0_5 unimpl
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#:SBC g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0x14 & eg_rd0_4 unimpl
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#:SBR g_offset9_4, g_offset4_1, g_rd0_4 is g_op13_3=0x5 & g_offset9_4 & g_op5_4=0xd & g_offset4_1 & g_rd0_4 unimpl
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#:SCALL is g_op0_16=0xd733 unimpl
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#:SCR g_rd0_4 is g_op4_12=0x5c1 & g_rd0_4 unimpl
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#:SLEEP eg_opcode0_8 is g_op0_16=0xe9b0 ; eg_op8_8=0x0 & eg_opcode0_8 unimpl
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#:SR_COND g_cond4_4, g_rd0_4 is g_op8_8=0x5f & g_cond4_4 & g_rd0_4 unimpl
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#:SSRF g_offset4_5 is g_op9_7=0x69 & g_offset4_5 & g_op0_4=0x3 unimpl
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#:ST.B g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xc & g_rs0_4 unimpl
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#:ST.B g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xf & g_rs0_4 unimpl
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#:ST.B g_rp9_4, g_disp4_3, g_rs0_4 is g_op13_3=0x5 & g_rp9_4 & g_op7_2=0x1 & g_disp4_3 & g_rs0_4 unimpl
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#:ST.B g_rp9_4, g_rs0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x16 & g_rs0_4 ; eg_disp0_16 unimpl
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#:ST.B g_rb9_4, g_ri0_4, eg_shift4_2, eg_rs0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x2c & eg_shift4_2 & eg_rs0_4 unimpl
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#:ST.B_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x7 & eg_disp0_9 unimpl
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#:ST.D g_rp9_4, g_rs1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x12 & g_rs1_3 & g_op0_1=0x0 unimpl
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#:ST.D g_rp9_4, g_rs1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x12 & g_rs1_3 & g_op0_1=0x1 unimpl
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#:ST.D g_rp9_4, g_rs1_3 is g_op13_3=0x5 & g_rp9_4 & g_op4_5=0x11 & g_rs1_3 & g_op0_1=0x1 unimpl
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#:ST.D g_rp9_4, g_rs1_3, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0xe & g_rs1_3 & g_op0_1=0x1 ; eg_disp0_16 unimpl
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#:ST.D g_rb9_4, g_ri0_4, eg_shift4_2, eg_rs0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x20 & eg_shift4_2 & eg_rs0_4 unimpl
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#:ST.H g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xb & g_rs0_4 unimpl
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#:ST.H g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xe & g_rs0_4 unimpl
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#:ST.H g_rp9_4, g_disp4_3, g_rs0_4 is g_op13_3=0x5 & g_rp9_4 & g_op7_2=0x0 & g_disp4_3 & g_rs0_4 unimpl
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#:ST.H g_rp9_4, g_rs0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x15 & g_rs0_4 ; eg_disp0_16 unimpl
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#:ST.H g_rb9_4, g_ri0_4, eg_shift4_2, eg_rs0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x28 & eg_shift4_2 & eg_rs0_4 unimpl
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#:ST.H_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x6 & eg_disp0_9 unimpl
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#:ST.W g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xa & g_rs0_4 unimpl
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#:ST.W g_rp9_4, g_rs0_4 is g_op13_3=0x0 & g_rp9_4 & g_op4_5=0xd & g_rs0_4 unimpl
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#:ST.W g_rp9_4, g_disp4_4, g_rs0_4 is g_op13_3=0x4 & g_rp9_4 & g_op8_1=0x1 & g_disp4_4 & g_rs0_4 unimpl
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#:ST.W g_rp9_4, g_rs0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x14 & g_rs0_4 ; eg_disp0_16 unimpl
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#:ST.W g_rb9_4, g_ri0_4, eg_shift4_2, eg_rs0_4 is g_op13_3=0x7 & g_rb9_4 & g_op4_5=0x0 & g_ri0_4 ; eg_op6_10=0x24 & eg_shift4_2 & eg_rs0_4 unimpl
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#:ST.W_COND g_rp9_4, g_rd0_4, eg_cond12_4, eg_disp0_9 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1f & g_rd0_4 ; eg_cond12_4 & eg_op9_3=0x5 & eg_disp0_9 unimpl
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#:STC.D g_rp0_4, eg_cop13_3, eg_rs9_3, eg_disp0_8 is g_op4_12=0xeba & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rs9_3 & eg_op8_1=0x0 & eg_disp0_8 unimpl
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#:STC.D g_rp0_4, eg_cop13_3, eg_rs9_3 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs9_3 & eg_op0_9=0x70 unimpl
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#:STC.D g_rp0_4, eg_cop13_3, eg_rs9_3, eg_shift4_2, eg_ri0_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rs9_3 & eg_op6_3=0x3 & eg_shift4_2 & eg_ri0_4 unimpl
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#:STC.W g_rp0_4, eg_cop13_3, eg_rs8_4, eg_disp0_8 is g_op4_12=0xeba & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs8_4 & eg_disp0_8 unimpl
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#:STC.W g_rp0_4, eg_cop13_3, eg_rs8_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x0 & eg_rs8_4 & eg_op0_8=0x60 unimpl
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#:STC.W g_rp0_4, eg_cop13_3, eg_rs8_4, eg_shift4_2, eg_ri0_4 is g_op4_12=0xefa & g_rp0_4 ; eg_cop13_3 & eg_op12_1=0x1 & eg_rs8_4 & eg_op6_2=0x2 & eg_shift4_2 & eg_ri0_4 unimpl
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#:STC0.D g_rp0_4, eg_disp12_4, eg_rs9_3, eg_disp0_8 is g_op4_12=0xf7a & g_rp0_4 ; eg_disp12_4 & eg_rs9_3 & eg_op8_1=0x0 & eg_disp0_8 unimpl
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#:STC0.W g_rp0_4, eg_disp12_4, eg_rs8_4, eg_disp0_8 is g_op4_12=0xf5a & g_rp0_4 ; eg_disp12_4 & eg_rs8_4 & eg_disp0_8 unimpl
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#:STCM.D g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x5 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl
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#:STCM.W g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x3 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl
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#:STCM.W g_rp0_4, eg_cop13_3, eg_update12_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op4_12=0xeda & g_rp0_4 ; eg_cop13_3 & eg_update12_1 & eg_op8_4=0x2 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl
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#:STCOND g_rp9_4, g_rs0_4, eg_disp0_16 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x17 & g_rs0_4 ; eg_disp0_16 unimpl
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#:STDSP g_disp4_7, g_rs0_4 is g_op11_5=0xa & g_disp4_7 & g_rs0_4 unimpl
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#:STHH.W g_rx9_4, g_ry0_4, eg_xpart13_1, eg_ypart12_1, eg_disp4_8, eg_rp0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op14_2=0x3 & eg_xpart13_1 & eg_ypart12_1 & eg_disp4_8 & eg_rp0_4 unimpl
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#:STHH.W g_rx9_4, g_ry0_4, eg_xpart13_1, eg_ypart12_1, eg_ri8_4, eg_shift4_2, eg_rb0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1e & g_ry0_4 ; eg_op14_2=0x2 & eg_xpart13_1 & eg_ypart12_1 & eg_ri8_4 & eg_op6_2=0x0 & eg_shift4_2 & eg_rb0_4 unimpl
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#:STM g_update9_1, g_rp0_4, eg_regsel15_1, eg_regsel14_1, eg_regsel13_1, eg_regsel12_1, eg_regsel11_1, eg_regsel10_1, eg_regsel9_1, eg_regsel8_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op10_6=0x3a & g_update9_1 & g_op4_5=0x1c & g_rp0_4 ; eg_regsel15_1 & eg_regsel14_1 & eg_regsel13_1 & eg_regsel12_1 & eg_regsel11_1 & eg_regsel10_1 & eg_regsel9_1 & eg_regsel8_1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl
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#:STMTS g_update9_1, g_rp0_4, eg_regsel15_1, eg_regsel14_1, eg_regsel13_1, eg_regsel12_1, eg_regsel11_1, eg_regsel10_1, eg_regsel9_1, eg_regsel8_1, eg_regsel7_1, eg_regsel6_1, eg_regsel5_1, eg_regsel4_1, eg_regsel3_1, eg_regsel2_1, eg_regsel1_1, eg_regsel0_1 is g_op10_6=0x3b & g_update9_1 & g_op4_5=0x1c & g_rp0_4 ; eg_regsel15_1 & eg_regsel14_1 & eg_regsel13_1 & eg_regsel12_1 & eg_regsel11_1 & eg_regsel10_1 & eg_regsel9_1 & eg_regsel8_1 & eg_regsel7_1 & eg_regsel6_1 & eg_regsel5_1 & eg_regsel4_1 & eg_regsel3_1 & eg_regsel2_1 & eg_regsel1_1 & eg_regsel0_1 unimpl
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#:STSWP.H g_rp9_4, g_rs0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op12_4=0x9 & eg_disp0_12 unimpl
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#:STSWP.W g_rp9_4, g_rs0_4, eg_disp0_12 is g_op13_3=0x7 & g_rp9_4 & g_op4_5=0x1d & g_rs0_4 ; eg_op12_4=0xa & eg_disp0_12 unimpl
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#:SUB g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x1 & g_rd0_4 unimpl
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#:SUB g_rx9_4, g_ry0_4, eg_shift4_2, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x4 & eg_shift4_2 & eg_rd0_4 unimpl
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#:SUB g_imm4_8, g_rd0_4 is g_op12_4=0x2 & g_imm4_8 & g_rd0_4 unimpl
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#:SUB g_imm9_4, g_imm4_1, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_imm9_4 & g_op5_4=0x1 & g_imm4_1 & g_rd0_4 ; eg_imm0_16 unimpl
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#:SUB g_rs9_4, g_rd0_4, eg_imm0_16 is g_op13_3=0x7 & g_rs9_4 & g_op4_5=0xc & g_rd0_4 ; eg_imm0_16 unimpl
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#:SUB_F_COND g_update9_1, g_rd0_4, eg_cond8_4, eg_imm0_8 is g_op10_6=0x3d & g_update9_1 & g_op4_5=0x1b & g_rd0_4 ; eg_op12_4=0x0 & eg_cond8_4 & eg_imm0_8 unimpl
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#:SUB_COND g_rx9_4, g_ry0_4, eg_cond8_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x1d & g_ry0_4 ; eg_op12_4=0xe & eg_cond8_4 & eg_op4_4=0x1 & eg_rd0_4 unimpl
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#:SUBHH.W g_rx9_4, g_ry0_4, eg_xpart5_1, eg_ypart4_1, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op6_10=0x3c & eg_xpart5_1 & eg_ypart4_1 & eg_rd0_4 unimpl
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#:SWAP.B g_rd0_4 is g_op4_12=0x5cb & g_rd0_4 unimpl
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#:SWAP.BH g_rd0_4 is g_op4_12=0x5cc & g_rd0_4 unimpl
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#:SWAP.H g_rd0_4 is g_op4_12=0x5ca & g_rd0_4 unimpl
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#:SYNC eg_opcode0_8 is g_op0_16=0xebb0 ; eg_op8_8=0x0 & eg_opcode0_8 unimpl
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#:TLBR is g_op0_16=0xd643 unimpl
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#:TLBS is g_op0_16=0xd653 unimpl
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#:TLBW is g_op0_16=0xd663 unimpl
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#:TNBZ g_rd0_4 is g_op4_12=0x5ce & g_rd0_4 unimpl
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#:TST g_rs9_4, g_rd0_4 is g_op13_3=0x0 & g_rs9_4 & g_op4_5=0x7 & g_rd0_4 unimpl
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#:XCHG g_rx9_4, g_ry0_4, eg_rd0_4 is g_op13_3=0x7 & g_rx9_4 & g_op4_5=0x0 & g_ry0_4 ; eg_op4_12=0xb4 & eg_rd0_4 unimpl
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