401 lines
7.2 KiB
Plaintext
401 lines
7.2 KiB
Plaintext
# CR16B
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# TODO: instructions not implemented
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# Basic ================================================================================
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# define endian=big; # Defined in file that includes this file
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define alignment=2;
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define space ram type=ram_space size=3 default;
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define space register type=register_space size=2;
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# Registers ============================================================================
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define register offset=0 size=2 [
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R0 R1 R2 R3 R4 R5 R6 R7
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R8 R9 R10 R11 R12_L R12_H R13_L R13_H
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RA_L RA_H SP_L _
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];
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# Fields =================================================================================
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define token instr(16)
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b0=(0,0) # bit0
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op1=(1,4) # operand1
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op2=(5,8) # operand2
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opcode1=(9,12) # opcode1
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i=(13,13) # integer operation length bit: i=0=8bit, i=1=16bit
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opcode2=(14,15) # opcode2
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op1_b02=(1,3) # bits 0,1,2 of op1
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op1_b12=(2,3) # bits 1,2 of op1
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op2_b23=(7,8) # bits 2,3 of op2
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op2_b12=(6,7) # bits 1,2 of op2
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opcode1_b23=(11,12) # bits 2,3 of opcode1
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opcode1_b13=(10,12) # bits 1,2,3 of opcode1
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;
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# Context variables ====================================================
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# Attach variables =====================================================
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# attach normal registers
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#attach variables [ N_0 M_0 ] [
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# r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
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#];
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# Constructors =======================================================================
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# MOVES
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:MOV is opcode2=1 & i & opcode1=0xc & op2 & op1 & b0=1 {
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}
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:MOV is opcode2=0 & i & opcode1=0xc & op2 & op1 & b0 {
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}
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:MOVXB is opcode2=1 & i=1 & opcode1=0x4 & op2 & op1 & b0=0 {
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}
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:MOVZB is opcode2=1 & i=1 & opcode1=0x5 & op2 & op1 & b0=0 {
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}
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:MOVD is opcode2=1 & i=1 & opcode1_b13=1 & op2 & op1 & b0=0 {
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}
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# ARITHMETIC
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:ADD is opcode2=1 & i & opcode1=0 & op2 & op1 & b0=1 {
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}
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:ADD is opcode2=0 & i & opcode1=0 & op2 & op1 & b0 {
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}
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:ADDU is opcode2=1 & i & opcode1=1 & op2 & op1 & b0=1 {
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}
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:ADDU is opcode2=0 & i & opcode1=1 & op2 & op1 & b0 {
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}
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:ADDC is opcode2=1 & i & opcode1=9 & op2 & op1 & b0=1 {
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}
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:ADDC is opcode2=0 & i & opcode1=9 & op2 & op1 & b0 {
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}
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:MUL is opcode2=1 & i & opcode1=3 & op2 & op1 & b0=1 {
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}
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:MUL is opcode2=0 & i & opcode1=3 & op2 & op1 & b0 {
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}
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:MULSB is opcode2=1 & i=1 & opcode1=0 & op2 & op1 & b0=0 {
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}
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:MULSW is opcode2=1 & i=1 & opcode1=1 & op2 & op1 & b0=0 {
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}
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:MULUW is opcode2=1 & i=1 & opcode1=0xf & op2 & op1_b12=0 & b0=0 {
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}
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:SUB is opcode2=1 & i & opcode1=0xf & op2 & op1 & b0=1 {
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}
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:SUB is opcode2=0 & i & opcode1=0xf & op2 & op1 & b0 {
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}
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:SUBC is opcode2=1 & i & opcode1=0xd & op2 & op1 & b0=1 {
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}
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:SUBC is opcode2=0 & i & opcode1=0xd & op2 & op1 & b0 {
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}
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# INTEGER COMPARISON
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:CMP is opcode2=1 & i & opcode1=0x7 & op2 & op1 & b0=1 {
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}
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:CMP is opcode2=0 & i & opcode1=0x7 & op2 & op1 & b0 {
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}
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:BEQ0 is opcode2=0 & i & opcode1=0xa & op2_b12=0 & op1 & b0=1 {
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}
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:BEQ1 is opcode2=0 & i & opcode1=0xa & op2_b12=1 & op1 & b0=1 {
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}
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:BNE0 is opcode2=0 & i & opcode1=0xa & op2_b12=2 & op1 & b0=1 {
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}
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:BNE1 is opcode2=0 & i & opcode1=0xa & op2_b12=3 & op1 & b0=1 {
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}
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# LOGICAL / BOOLEAN
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:AND is opcode2=1 & i & opcode1=0x8 & op2 & op1 & b0=1 {
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}
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:AND is opcode2=0 & i & opcode1=0x8 & op2 & op1 & b0 {
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}
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:OR is opcode2=1 & i & opcode1=0xe & op2 & op1 & b0=1 {
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}
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:OR is opcode2=0 & i & opcode1=0xe & op2 & op1 & b0 {
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}
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:S is opcode2=1 & i & opcode1=0x7 & op2 & op1 & b0=0 {
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}
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:XOR is opcode2=1 & i & opcode1=0x6 & op2 & op1 & b0=1 {
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}
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:XOR is opcode2=0 & i & opcode1=0x6 & op2 & op1 & b0 {
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}
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# SHIFTS
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:ASHU is opcode2=1 & i & opcode1=0x4 & op2 & op1 & b0=1 {
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}
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:ASHU is opcode2=0 & i & opcode1=0x4 & op2 & op1 & b0 {
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}
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:LSH is opcode2=1 & i & opcode1=0x5 & op2 & op1 & b0=1 {
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}
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:LSH is opcode2=0 & i & opcode1=0x5 & op2 & op1 & b0 {
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}
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# BITS
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:TBIT is opcode2=1 & i=1 & opcode1=0xb & op2 & op1 & b0=1 {
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}
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:TBIT is opcode2=0 & i=1 & opcode1=0xb & op2 & op1 & b0 {
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}
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:TBIT is opcode2=1 & i & opcode1=2 & op2_b12=2 & op1 & b0=1 {
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}
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:TBIT is opcode2=0 & i & opcode1=2 & op2_b12=2 & op1 & b0=1 {
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}
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:TBIT is opcode2=0 & i & opcode1=2 & op2_b12=2 & op1 & b0=0 {
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}
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:CBIT is opcode2=1 & i & opcode1=2 & op2_b12=0 & op1 & b0=1 {
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}
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:CBIT is opcode2=0 & i & opcode1=2 & op2_b12=0 & op1 & b0=1 {
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}
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:CBIT is opcode2=0 & i & opcode1=2 & op2_b12=0 & op1 & b0=0 {
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}
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:SBIT is opcode2=1 & i & opcode1=2 & op2_b12=1 & op1 & b0=1 {
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}
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:SBIT is opcode2=0 & i & opcode1=2 & op2_b12=1 & op1 & b0=1 {
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}
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:SBIT is opcode2=0 & i & opcode1=2 & op2_b12=1 & op1 & b0=0 {
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}
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# PROCESSOR REGISTER MANIPULATION
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:LPR is opcode2=1 & i=1 & opcode1=8 & op2 & op1 & b0=0 {
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}
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:SPR is opcode2=1 & i=1 & opcode1=9 & op2 & op1 & b0=0 {
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}
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# JUMPS / LINKS
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:Bcond is opcode2=1 & i=0 & opcode1 & op2 & op1 & b0=0 {
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}
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:Bcond is opcode2=0 & i=0 & opcode1=0xa & op2 & op1_b02=7 & b0=0 {
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}
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:Bcond is opcode2=1 & i=1 & opcode1=0xa & op2 & op1 & b0=0 {
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}
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:BAL is opcode2=0 & i=1 & opcode1=0xa & op2 & op1_b02=7 & b0=0 {
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}
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:BAL is opcode2=1 & i=1 & opcode1=0xb & op2 & op1 & b0=0 {
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}
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:BR is opcode2=1 & i=0 & opcode1 & op2=0xe & op1 & b0=0 {
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}
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:BR is opcode2=0 & i=0 & opcode1=0xa & op2=0xe & op1_b02=7 & b0=0 {
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}
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:BR is opcode2=1 & i=1 & opcode1=0xa & op2=0xe & op1 & b0=0 {
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}
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:EXCP is opcode2=1 & i=1 & opcode1=0xd & op2=0xf & op1 & b0=0 {
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}
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:Jcond is opcode2=1 & i=0 & opcode1=0xa & op2 & op1 & b0=1 {
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}
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:Jcond is opcode2=0 & i=0 & opcode1=0xb & op2 & op1 & b0=1 {
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}
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:JAL is opcode2=1 & i=1 & opcode1=0xa & op2 & op1 & b0=1 {
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}
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:JAL is opcode2=0 & i=0 & opcode1=0xb & op2 & op1 & b0=0 {
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}
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:JUMP is opcode2=1 & i=0 & opcode1=0xa & op2=0xe & op1 & b0=1 {
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}
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:JUMP is opcode2=0 & i=0 & opcode1=0xb & op2=0xe & op1 & b0=1 {
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}
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:RETX is opcode2=1 & i=1 & opcode1=0xc & op2=0xf & op1=0xf & b0=0 {
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}
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:PUSH is opcode2=1 & i=1 & opcode1=0x6 & op2_b23=0 & op1 & b0=0 {
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}
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:POP is opcode2=1 & i=1 & opcode1=0x6 & op2_b23=1 & op1 & b0=0 {
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}
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:POPRET is opcode2=1 & i=1 & opcode1=0x6 & op2_b23=2 & op1 & b0=0 {
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}
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:POPRET is opcode2=1 & i=1 & opcode1=0x6 & op2_b23=3 & op1 & b0=0 {
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}
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# LOAD / STORE
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:LOAD is opcode2=2 & i & opcode1 & op2 & op1 & b0 {
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}
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:LOAD is opcode2=2 & i & opcode1_b23=2 & op2 & op1 & b0=1 {
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}
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:LOAD is opcode2=2 & i & opcode1_b23=3 & op2 & op1 & b0=1 {
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}
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:LOAD is opcode2=2 & i & opcode1_b23=3 & op2 & op1=0xf & b0=1 {
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}
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:LOADM is opcode2=1 & i=1 & opcode1=0xf & op2_b23=0 & op1=2 & b0=0 {
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}
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:STORE is opcode2=3 & i & opcode1 & op2 & op1 & b0 {
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}
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:STORE is opcode2=3 & i & opcode1_b23=2 & op2 & op1 & b0=1 {
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}
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:STORE is opcode2=3 & i & opcode1_b23=3 & op2 & op1 & b0=1 {
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}
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:STORE is opcode2=3 & i & opcode1_b23=3 & op2 & op1=0xf & b0=1 {
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}
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:STORE is opcode2=1 & i & opcode1=2 & op2_b12=3 & op1 & b0=1 {
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}
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:STORE is opcode2=0 & i & opcode1=2 & op2_b12=3 & op1 & b0=1 {
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}
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:STORE is opcode2=0 & i & opcode1=2 & op2_b12=3 & op1 & b0=0 {
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}
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:STORM is opcode2=1 & i=1 & opcode1=0xf & op2_b23=1 & op1=2 & b0=0 {
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}
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# MISC
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:DI is opcode2=1 & i=1 & opcode1=0xe & op2=0xe & op1=0xf & b0=0 {
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}
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:EI is opcode2=1 & i=1 & opcode1=0xe & op2=0xf & op1=0xf & b0=0 {
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}
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:NOP is opcode2=0 & i=0 & opcode1=0x1 & op2=0 & op1=0 & b0=0 {
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}
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:WAIT is opcode2=1 & i=1 & opcode1=0xf & op2=0xf & op1=0xf & b0=0 {
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}
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:EIWAIT is opcode2=1 & i=1 & opcode1=0xf & op2=0xf & op1=0x3 & b0=0 {
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}
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