445 lines
16 KiB
Plaintext
445 lines
16 KiB
Plaintext
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############################
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#
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# MIPS64 Instructions
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#
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############################
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# 0111 00ss ssst tttt dddd d000 0010 0101
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:dclo RD, RSsrc is $(AMODE) & ((REL6=0 & prime=0x1C & sa=0x0 & fct=0x25) | (REL6=1 & prime=0x00 & sa=0x1 & fct=0x13 & op=0)) & RD & RSsrc {
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RD = countLeadingOnes( RSsrc );
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}
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# 0111 00ss ssst tttt dddd d000 0010 0100
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:dclz RD, RSsrc is $(AMODE) & ((REL6=0 & prime=0x1C & sa=0x0 & fct=0x24) | (REL6=1 & prime=0x00 & sa=0x1 & fct=0x12 & op=0)) & RD & RSsrc {
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RD = countLeadingZeros( RSsrc );
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}
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# 0111 11ss ssst tttt mmmm mLLL LL00 0011
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:dext RT, RSsrc, lsb, ExtSize is $(AMODE) & prime=0x1F & fct=0x03 & RT & RSsrc & lsb & msbd & ExtSize {
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val:8 = (RSsrc >> lsb);
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val = val & (0xffffffff >> (32 - ExtSize));
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RT = zext(val);
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}
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# 0111 11ss ssst tttt mmmm mLLL LL00 0001
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:dextm RT, RSsrc, lsb, DextmSize is $(AMODE) & prime=0x1F & fct=0x01 & RT & RSsrc & lsb & msbd & DextmSize {
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val:8 = (RSsrc >> lsb);
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val = val & (0xffffffffffffffff >> (64 - DextmSize));
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RT = zext(val);
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}
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# 0111 11ss ssst tttt mmmm mLLL LL00 0010
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:dextu RT, RSsrc, DXuPos, ExtSize is $(AMODE) & prime=0x1F & fct=0x02 & RT & RSsrc & lsb & msbd & DXuPos & ExtSize {
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val:8 = (RSsrc >> DXuPos);
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val = val & (0xffffffff >> (32 - ExtSize));
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RT = zext(val);
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}
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# 0111 11ss ssst tttt mmmm mLLL LL00 0111
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:dins RT, RSsrc, lsb, InsSize is $(AMODE) & prime=0x1F & fct=0x07 & RT & RTsrc & RSsrc & lsb & msbd & InsSize {
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tmpa:$(REGSIZE) = -1;
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tmpa = tmpa >> ($(REGSIZE) - InsSize);
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tmpb:$(REGSIZE) = RSsrc & tmpa;
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tmpa = tmpa << lsb;
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tmpa = ~tmpa;
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tmpb = tmpb << lsb;
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RT = (RT & tmpa) | tmpb;
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}
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# 0111 11ss ssst tttt mmmm mLLL LL00 0101
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:dinsm RT, RSsrc, lsb, DinsXSize is $(AMODE) & prime=0x1F & fct=0x05 & RT & RTsrc & RSsrc & lsb & msbd & DinsXSize {
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tmpa:$(REGSIZE) = -1;
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tmpa = tmpa >> ($(REGSIZE) - DinsXSize);
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tmpb:$(REGSIZE) = RSsrc & tmpa;
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tmpa = tmpa << lsb;
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tmpa = ~tmpa;
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tmpb = tmpb << lsb;
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RT = (RT & tmpa) | tmpb;
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}
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# 0111 11ss ssst tttt mmmm mLLL LL00 0110
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:dinsu RT, RSsrc, DXuPos, DinsXSize is $(AMODE) & prime=0x1F & fct=0x06 & RT & RTsrc & RSsrc & lsb & msbd & DXuPos & DinsXSize {
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tmpa:$(REGSIZE) = -1;
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tmpa = tmpa >> ($(REGSIZE) - DinsXSize);
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tmpb:$(REGSIZE) = RSsrc & tmpa;
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tmpa = tmpa << DXuPos;
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tmpa = ~tmpa;
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tmpb = tmpb << DXuPos;
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RT = (RT & tmpa) | tmpb;
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}
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# 0100 0000 001t tttt dddd d000 0000 0eee
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:dmfc0 RT, RD0 is $(AMODE) & prime=16 & copop=1 & RT & RD0 & zero6=0 {
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RT = RD0;
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}
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:dmfc1 RT, fs is $(AMODE) & prime=17 & copop=1 & RT & fs & bigfunct=0 {
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RT = fs;
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}
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:dmfc2 RT, immed is $(AMODE) & prime=18 & copop=1 & RT & immed {
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RT = getCopReg(2:1, immed:4);
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}
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# 0100 0000 101t tttt dddd d000 0000 0eee
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:dmtc0 RTsrc, RD0 is $(AMODE) & prime=16 & copop=5 & RTsrc & RD0 & zero6=0 {
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RD0 = RTsrc;
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}
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# 0100 0100 101t tttt ssss s000 0000 0000
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:dmtc1 RTsrc, fs is $(AMODE) & prime=17 & copop=5 & RTsrc & fs & bigfunct=0 {
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fs = RTsrc;
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}
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:dmtc2 RTsrc, immed is $(AMODE) & prime=18 & copop=5 & RTsrc & immed {
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setCopReg(2:1, immed:4, RTsrc);
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}
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# 0000 0000 001t tttt dddd daaa aa11 1010
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:drotr RD, RTsrc, sa is $(AMODE) & prime=0x0 & zero1=0x0 & bit21=0x1 & fct=0x3A & RD & RTsrc & sa {
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tmp:8 = RTsrc;
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tmp1:8 = tmp >> sa;
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tmp2:8 = tmp << (64 - sa);
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RD = tmp1 + tmp2;
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}
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# 0000 0000 001t tttt dddd daaa aa11 1110
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:drotr32 RD, RTsrc, sa is $(AMODE) & prime=0x0 & zero1=0x0 & bit21=0x1 & fct=0x3E & RD & RTsrc & sa {
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shift:1 = sa + 32;
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tmp:8 = RTsrc;
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tmp1:8 = tmp >> shift;
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tmp2:8 = tmp << (64 - shift);
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RD = tmp1 + tmp2;
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}
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# 0000 00ss ssst tttt dddd d000 0101 0110
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:drotrv RD, RTsrc, RSsrc is $(AMODE) & prime=0x0 & zero2=0x0 & bit6=0x1 & fct=0x16 & RD & RTsrc & RSsrc {
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shift:8 = RSsrc & 0x3f;
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tmp:8 = RTsrc;
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tmp1:8 = tmp >> shift;
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tmp2:8 = tmp << (32 - shift);
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RD = tmp1 + tmp2;
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}
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# 0111 1100 000t tttt dddd d000 1010 0100
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:dsbh RD, RTsrc is $(AMODE) & prime=0x1F & rs=0x0 & fct2=0x02 & fct=0x24 & RD & RTsrc {
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tmp1:8 = RTsrc & 0xff;
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tmp2:8 = (RTsrc >> 8) & 0xff;
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tmp3:8 = (RTsrc >> 16) & 0xff;
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tmp4:8 = (RTsrc >> 24) & 0xff;
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tmp5:8 = (RTsrc >> 32) & 0xff;
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tmp6:8 = (RTsrc >> 40) & 0xff;
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tmp7:8 = (RTsrc >> 48) & 0xff;
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tmp8:8 = (RTsrc >> 56) & 0xff;
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RD = (tmp7 << 56) | (tmp8 << 48) | (tmp5 << 40) | (tmp6 << 32)
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| (tmp3 << 24) | (tmp4 << 16) | (tmp1 << 8) | (tmp2);
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}
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# 0111 1100 000t tttt dddd d001 0110 0100
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:dshd RD, RTsrc is$(AMODE) & prime=0x1F & rs=0x0 & fct2=0x05 & fct=0x24 & RD & RTsrc {
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tmp1:8 = RTsrc & 0xffff;
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tmp2:8 = (RTsrc >> 16) & 0xffff;
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tmp3:8 = (RTsrc >> 32) & 0xffff;
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tmp4:8 = (RTsrc >> 48) & 0xffff;
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RD = (tmp1 << 48) | (tmp2 << 32) | (tmp3 << 16) | tmp4;
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}
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# 0000 0000 000t tttt dddd daaa aa11 1000
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:dsll RD, RTsrc, sa is $(AMODE) & prime=0 & fct=56 & rs=0 & RTsrc & RD & sa {
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RD = RTsrc << sa;
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}
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# 0000 0000 000t tttt dddd daaa aa11 1100
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:dsll32 RD, RTsrc, sa is $(AMODE) & prime=0 & fct=60 & rs=0 & RTsrc & RD & sa {
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RD = RTsrc << (sa + 32);
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}
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# 0000 00ss ssst tttt dddd d000 0001 0100
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:dsllv RD, RTsrc, RSsrc is $(AMODE) & prime=0 & fct=20 & RSsrc & RTsrc & RD & sa=0 {
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RD = RTsrc << RSsrc;
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}
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# 0000 0000 000t tttt dddd daaa aa11 1011
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:dsra RD, RTsrc, sa is $(AMODE) & prime=0 & fct=59 & rs=0 & RTsrc & RD & sa {
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RD = RTsrc s>> sa;
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}
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# 0000 0000 000t tttt dddd daaa aa11 1111
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:dsra32 RD, RTsrc, sa is $(AMODE) & prime=0 & fct=63 & rs=0 & RTsrc & RD & sa {
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RD = RTsrc s>> (sa + 32);
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}
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# 0000 00ss ssst tttt dddd d000 0001 0111
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:dsrav RD, RTsrc, RSsrc is $(AMODE) & prime=0 & fct=23 & RSsrc & RTsrc & RD & sa=0 {
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RD = RTsrc s>> RSsrc;
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}
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# 0000 0000 000t tttt dddd daaa aa11 1010
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:dsrl RD, RTsrc, sa is $(AMODE) & prime=0 & fct=58 & rs=0 & RTsrc & RD & sa {
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RD = RTsrc >> sa;
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}
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# 0000 0000 000t tttt dddd daaa aa11 1110
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:dsrl32 RD, RTsrc, sa is $(AMODE) & prime=0 & fct=62 & rs=0 & RTsrc & RD & sa {
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RD = RTsrc >> (sa + 32);
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}
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# 0000 00ss ssst tttt dddd d000 0101 0110
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:dsrlv RD, RTsrc, RSsrc is $(AMODE) & prime=0 & fct=22 & RSsrc & RTsrc & RD & sa=0 {
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RD = RTsrc >> RSsrc;
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}
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# 0000 00ss ssst tttt dddd d000 0010 1110
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:dsub RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=46 & RSsrc & RTsrc & RD & sa=0 {
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RD = RSsrc - RTsrc;
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}
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# 0000 00ss ssst tttt dddd d000 0010 1111
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:dsubu RD, RSsrc, RTsrc is $(AMODE) & prime=0 & fct=47 & RSsrc & RTsrc & RD & sa=0 {
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RD = RSsrc - RTsrc;
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}
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# 1101 11bb bbbt tttt iiii iiii iiii iiii
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:ld RT, OFF_BASE is $(AMODE) & prime=55 & OFF_BASE & RT {
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RT = *[ram]:8 OFF_BASE;
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}
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@if ENDIAN == "big"
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# 0110 10bb bbbt tttt iiii iiii iiii iiii
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:ldl RT, OFF_BASE is $(AMODE) & prime=26 & OFF_BASE & RT {
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shft:$(ADDRSIZE) = OFF_BASE & 0x7;
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addr:$(ADDRSIZE) = OFF_BASE - shft;
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valOrig:8 = RT & (0xffffffffffffffff >> ((8-shft) * 8));
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valLoad:8 = *(addr) << (shft * 8);
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RT = valLoad | valOrig;
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}
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# 0110 11bb bbbt tttt iiii iiii iiii iiii
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:ldr RT, OFF_BASE is $(AMODE) & prime=27 & OFF_BASE & RT {
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# no-op
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# see ldl instruction
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shft:$(ADDRSIZE) = OFF_BASE & 0x7;
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addr:$(ADDRSIZE) = OFF_BASE - shft;
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valOrig:8 = RT & (0xffffffffffffffff << ((shft+1) * 8));
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valLoad:8 = *(addr) >> ((7-shft) * 8);
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RT = valOrig | valLoad;
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}
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@else # ENDIAN == "little
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# 0110 10bb bbbt tttt iiii iiii iiii iiii
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:ldl RT, OFF_BASE is $(AMODE) & prime=26 & OFF_BASE & RT {
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shft:$(ADDRSIZE) = OFF_BASE & 0x7;
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addr:$(ADDRSIZE) = OFF_BASE - shft;
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valOrig:8 = RT & (0xffffffffffffffff >> ((shft+1) * 8));
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valLoad:8 = *(addr) << ((7-shft) * 8);
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RT = valLoad | valOrig;
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}
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# 0110 11bb bbbt tttt iiii iiii iiii iiii
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:ldr RT, OFF_BASE is $(AMODE) & prime=27 & OFF_BASE & RT {
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# no-op
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# see ldl instruction
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shft:$(ADDRSIZE) = OFF_BASE & 0x7;
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addr:$(ADDRSIZE) = OFF_BASE - shft;
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valOrig:8 = RT & (0xffffffffffffffff << ((8-shft) * 8));
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valLoad:8 = *(addr) >> (shft * 8);
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RT = valOrig | valLoad;
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}
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@endif # ENDIAN
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# ldl and ldr almost always come in pairs.
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# When the analyzer does finds a matching ldl/ldr pair, the pcode is simplified so that
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# ldl does all the loading while ldr is a no-op
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@if ENDIAN == "big"
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:ldl RT, OFF_BASE is $(AMODE) & prime=26 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] {
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RT = *[ram]:8 OFF_BASE;
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}
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:ldr RT, OFF_BASE is $(AMODE) & prime=27 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] {
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}
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@else
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:ldl RT, OFF_BASE is $(AMODE) & prime=26 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] {
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}
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:ldr RT, OFF_BASE is $(AMODE) & prime=27 & OFF_BASE & RT & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] {
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RT = *[ram]:8 OFF_BASE;
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}
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@endif
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# 1101 00bb bbbt tttt iiii iiii iiii iiii
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:lld RT, OFF_BASE is $(AMODE) & prime=52 & OFF_BASE & RT {
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RT = *[ram]:8 OFF_BASE;
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}
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# 1001 11bb bbbt tttt iiii iiii iiii iiii
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:lwu RT, OFF_BASE is $(AMODE) & prime=39 & OFF_BASE & RT {
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RT = zext( *[ram]:4 OFF_BASE );
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}
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# 1111 00bb bbbt tttt iiii iiii iiii iiii
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:scd RTsrc, OFF_BASE is $(AMODE) & prime=60 & OFF_BASE & RT & RTsrc {
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*[ram]:8 OFF_BASE = RTsrc;
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RT = 1;
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}
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# 1111 11bb bbbt tttt iiii iiii iiii iiii
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:sd RTsrc, OFF_BASE is $(AMODE) & prime=63 & OFF_BASE & RTsrc {
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*[ram]:8 OFF_BASE = RTsrc;
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}
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@if ENDIAN == "big"
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# 1011 00bb bbbt tttt iiii iiii iiii iiii
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:sdl RTsrc, OFF_BASE is $(AMODE) & prime=44 & OFF_BASE & RTsrc {
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shft:$(ADDRSIZE) = OFF_BASE & 0x7;
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addr:$(ADDRSIZE) = OFF_BASE - shft;
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valOrig:8 = *(addr) & (0xffffffffffffffff << ((8-shft) * 8));
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valStore:8 = RTsrc >> (shft * 8);
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*(addr) = valOrig | valStore;
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}
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# 1011 01bb bbbt tttt iiii iiii iiii iiii
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:sdr RTsrc, OFF_BASE is $(AMODE) & prime=45 & OFF_BASE & RTsrc {
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shft:$(ADDRSIZE) = OFF_BASE & 0x7;
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addr:$(ADDRSIZE) = OFF_BASE - shft;
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valOrig:8 = *(addr) & (0xffffffffffffffff >> ((shft+1) * 8));
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valStore:8 = RTsrc << ((7-shft)*8);
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*(addr) = valStore | valOrig;
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}
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@else # ENDIAN == "little
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# 1011 00bb bbbt tttt iiii iiii iiii iiii
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:sdl RTsrc, OFF_BASE is $(AMODE) & prime=44 & OFF_BASE & RTsrc {
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shft:$(ADDRSIZE) = OFF_BASE & 0x7;
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addr:$(ADDRSIZE) = OFF_BASE - shft;
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valOrig:8 = *(addr) & (0xffffffffffffffff << ((shft+1) * 8));
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valStore:8 = RTsrc >> ((7-shft) * 8);
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*(addr) = valOrig | valStore;
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}
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# 1011 01bb bbbt tttt iiii iiii iiii iiii
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:sdr RTsrc, OFF_BASE is $(AMODE) & prime=45 & OFF_BASE & RTsrc {
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shft:$(ADDRSIZE) = OFF_BASE & 0x7;
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addr:$(ADDRSIZE) = OFF_BASE - shft;
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valOrig:8 = *(addr) & (0xffffffffffffffff >> ((8-shft) * 8));
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valStore:8 = RTsrc << (shft*8);
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*(addr) = valStore | valOrig;
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}
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@endif # ENDIAN
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# When the analyzer finds a matching sdl/sdr pair, the pcode is simplified so that
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# sdl does all the storing while sdr is a no-op
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@if ENDIAN == "big"
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:sdl RTsrc, OFF_BASE is $(AMODE) & prime=44 & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] {
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*[ram]:8 OFF_BASE = RTsrc;
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}
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:sdr RTsrc, OFF_BASE is $(AMODE) & prime=45 & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] {
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}
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@else
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:sdl RTsrc, OFF_BASE is $(AMODE) & prime=44 & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 1; globalset(inst_next, PAIR_INSTRUCTION_FLAG);] {
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}
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:sdr RTsrc, OFF_BASE is $(AMODE) & prime=45 & OFF_BASE & RTsrc & PAIR_INSTRUCTION_FLAG=1 [ PAIR_INSTRUCTION_FLAG = 0; ] {
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*[ram]:8 OFF_BASE = RTsrc;
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}
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@endif
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####
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#
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# Pre-6 semantics
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#
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####
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# 0000 00ss ssst tttt 0000 0000 0001 1110
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:ddiv RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & fct=30 & RSsrc & RTsrc & rd=0 & sa=0 {
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lo = RSsrc s/ RTsrc;
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hi = RSsrc s% RTsrc;
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}
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# 0000 00ss ssst tttt 0000 0000 0001 1111
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:ddivu RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & fct=31 & RSsrc & RTsrc & rd=0 & sa=0 {
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lo = RSsrc / RTsrc;
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hi = RSsrc % RTsrc;
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}
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# 0000 00ss ssst tttt 0000 0000 0001 1100
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:dmult RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & fct=28 & RSsrc & RTsrc & rd=0 & sa=0 {
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prod:16 = sext( RSsrc ) * sext( RTsrc );
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lo = prod(0);
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hi = prod(8);
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}
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# 0000 00ss ssst tttt 0000 0000 0001 1101
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:dmultu RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0 & fct=29 & RSsrc & RTsrc & rd=0 & sa=0 {
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prod:16 = zext( RSsrc ) * zext( RTsrc );
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lo = prod(0);
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hi = prod(8);
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}
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####
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#
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# Release 6 semantics
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#
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####
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:dalign RD, RSsrc, RTsrc, bp3 is $(AMODE) & REL6=1 & prime=0x1F & spec2=0x1 & fct=0x24 & bp3 & RSsrc & RTsrc & RD {
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tmp:8 = RTsrc << (8 * bp3);
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tmp = tmp | (RSsrc >> (64 - (8 * bp3)));
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RD = sext(tmp);
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}
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:daui RTsrc, RSsrc, S16L16 is $(AMODE) & REL6=1 & prime=0x1D & rs!=0 & RSsrc & RTsrc & S16L16 {
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RTsrc = RSsrc + sext(S16L16);
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}
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:dahi RSsrc, S16L32 is $(AMODE) & REL6=1 & prime=0x01 & op=0x06 & RSsrc & S16L32 {
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RSsrc = RSsrc + sext(S16L32);
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}
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:dati RSsrc, S16L48 is $(AMODE) & REL6=1 & prime=0x01 & op=0x1E & RSsrc & S16L48 {
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RSsrc = RSsrc + sext(S16L48);
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}
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:dbitswap RD, RTsrc is $(AMODE) & REL6=1 & prime=0x1F & zero21=0 & fct2=0 & bshfl=0x24 & RTsrc & RD {
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RD = bitSwap(RTsrc);
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}
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:ddiv RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1E & fct2=0x02 & RD & RSsrc & RTsrc {
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RD = RSsrc s/ RTsrc;
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}
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:dmod RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1E & fct2=0x03 & RD & RSsrc & RTsrc {
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RD = RSsrc s% RTsrc;
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}
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:ddivu RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1F & fct2=0x02 & RD & RSsrc & RTsrc {
|
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RD = RSsrc / RTsrc;
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}
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:dmodu RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1F & fct2=0x03 & RD & RSsrc & RTsrc {
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RD = RSsrc % RTsrc;
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}
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:dmul RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1C & fct2=0x02 & RD & RSsrc & RTsrc {
|
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tmpS:16 = sext(RSsrc);
|
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tmpT:16 = sext(RTsrc);
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|
tmpS = tmpS * tmpT;
|
|
RD = tmpS[0,64];
|
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}
|
|
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:dmuh RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1C & fct2=0x03 & RD & RSsrc & RTsrc {
|
|
tmpS:16 = sext(RSsrc);
|
|
tmpT:16 = sext(RTsrc);
|
|
tmpS = tmpS * tmpT;
|
|
RD = tmpS[64,64];
|
|
}
|
|
|
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:dmulu RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1D & fct2=0x02 & RD & RSsrc & RTsrc {
|
|
tmpS:16 = zext(RSsrc);
|
|
tmpT:16 = zext(RTsrc);
|
|
tmpS = tmpS * tmpT;
|
|
RD = tmpS[0,64];
|
|
}
|
|
|
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:dmuhu RD, RSsrc, RTsrc is $(AMODE) & REL6=1 & prime=0x00 & fct=0x1D & fct2=0x03 & RD & RSsrc & RTsrc {
|
|
tmpS:16 = zext(RSsrc);
|
|
tmpT:16 = zext(RTsrc);
|
|
tmpS = tmpS * tmpT;
|
|
RD = tmpS[64,64];
|
|
}
|
|
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:dlsa RD, RSsrc, RTsrc, SAV is $(AMODE) & REL6=1 & prime=0x00 & fct=0x15 & spec3=0 & SAV & RD & RSsrc & RTsrc {
|
|
RD = (RSsrc << SAV) + RTsrc;
|
|
}
|
|
|
|
:ldpc RS, S18L3 is $(AMODE) & REL6=1 & prime=0x3B & pcrel2=0x6 & RS & S18L3 {
|
|
tmp:8 = inst_start + sext(S18L3);
|
|
tmpa:$(ADDRSIZE) = 0;
|
|
ValCast(tmpa,tmp);
|
|
RS = sext(*[ram]:8 tmpa);
|
|
}
|
|
|
|
:lldx RT, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1F & fct=0x37 & bit6=1 & OFF_BASER6 & RT {
|
|
RT = *[ram]:8 OFF_BASER6;
|
|
}
|
|
|
|
:lwupc RS, S19L2 is $(AMODE) & REL6=1 & prime=0x3B & pcrel=0x2 & RS & S19L2 {
|
|
tmp:8 = inst_start + sext(S19L2);
|
|
tmpa:$(ADDRSIZE) = 0;
|
|
ValCast(tmpa,tmp);
|
|
RS = zext(*[ram]:4 tmpa);
|
|
}
|
|
|
|
:sdcx RTsrc, OFF_BASER6 is $(AMODE) & REL6=1 & prime=0x1E & fct=0x27 & bit6=1 & OFF_BASER6 & RTsrc {
|
|
*[ram]:8 OFF_BASER6 = RTsrc;
|
|
}
|