96 lines
3.0 KiB
Plaintext
96 lines
3.0 KiB
Plaintext
#
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# PIC-16 Main Section
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# includes constants, memory space and common register space definitions
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#
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# STATUS bit definitions
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@define STATUS_IRP_BIT 7
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@define STATUS_RP0_BIT 5
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@define STATUS_Z_BIT 2
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@define STATUS_DC_BIT 1
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@define STATUS_C_BIT 0
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# STATUS bit masks used for setting
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@define STATUS_IRP_MASK 0x80
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@define STATUS_RP_MASK 0x60
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@define STATUS_Z_MASK 0x04
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@define STATUS_DC_MASK 0x02
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@define STATUS_C_MASK 0x01
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# STATUS bit masks used for clearing
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@define STATUS_IRP_CLEARMASK 0x7F
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@define STATUS_RP_CLEARMASK 0x9F
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@define STATUS_Z_CLEARMASK 0xFB
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@define STATUS_DC_CLEARMASK 0xFD
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@define STATUS_C_CLEARMASK 0xFE
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define endian=little;
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define alignment=2;
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# Instruction Memory (ROM-based)
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define space CODE type=ram_space wordsize=2 size=2 default;
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# General Purpose Register Memory consists of 4-banks of 255-bytes for PIC16,
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# or 32-banks of 255 bytes each for PIC_16F.
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# Bank selection occurs using STATUS register bits RP0 & RP1
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define space DATA type=ram_space size=2;
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# HWSTACK consists of a 8-word by 13-bit RAM and a corresponding to a hidden stack pointer (STKPTR).
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define space HWSTACK type=ram_space wordsize=2 size=1; # WORDSIZE is actually 13-bits
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define space register type=register_space size=2;
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# Program Counter (13-bits) - PC Latch: PCLATH<PC:12-8> / PCL<PC:7-0>
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define register offset=0x0000 size=2 [ PC ];
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# Stack Pointer
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define register offset=0x0002 size=1 [ STKPTR ];
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# Working register
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define register offset=0x0003 size=1 [ W SkipNext ];
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# Status bit registers (these do not really exist and must get reflected into the STATUS byte register)
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@if PROCESSOR == "PIC_16"
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define register offset=0x0007 size=1 [ IRP RP ];
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@elif PROCESSOR == "PIC_16F"
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define register offset=0x0007 size=1 [ IRP RP ];
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@endif
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@define C "STATUS[0,1]"
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@define DC "STATUS[1,1]"
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@define Z "STATUS[2,1]"
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@define PD "STATUS[3,1]"
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@define TO "STATUS[4,1]"
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@define PA0 "STATUS[5,1]"
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#
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# WARNING! - Reflection of these DATA-based registers with the corresponding register
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# is not fully implemented due to the complexity of doing so within this language specification.
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# Reflection of certain registers (e.g., STATUS) within other memory banks is also not modeled.
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#
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# NOTES -
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# 1. Chips with voltage comparator and reference functions may replace A/D registers (ADCON0 and ADCON1) with (VMCON and VRCON)
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# Instances of this include PIC16F627A/628A/648A (there could be others)
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# 2. If a specific PIC-16 has a different register set, this file and the pic16.pspec file may be copied/renamed and
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# slightly modified to specify a the correct Register File Map.
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#
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#
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# Bank-0 File Registers
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#
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@if PROCESSOR == "PIC_16"
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define DATA offset=0x0000 size=1 [
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INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H
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];
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@elif PROCESSOR == "PIC_16F"
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define DATA offset=0x0000 size=1 [
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INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON _ _ _ _
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];
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define DATA offset=0x0004 size=2 [ FSR0 FSR1 ];
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@endif
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# Additional Data Bank data registers are defined in the .PSPEC file.
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