131 lines
3.3 KiB
Plaintext
131 lines
3.3 KiB
Plaintext
# Based on "PowerISA Version 2.06 Revision B" document dated July 23, 2010
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# Category: SPE.Embedded Float Vector Instructions
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# version 1.0
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define register offset=0x600 size=1 [
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spef_sovh spef_ovh spef_fgh spef_fxh spef_finvh spef_fdbzh spef_funfh spef_fovfh
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spef_reserved1 spef_reserved2
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spef_finxs spef_finvs spef_fdbzs spef_funfs spef_fovfs
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spef_reserved3
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spef_sov spef_ov spef_fg spef_fx spef_finv spef_fdbz spef_funf spef_fovf
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spef_reserved4
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spef_finxe spef_finve spef_fdbze spef_funfe spef_fovfe spef_frmc0 spef_frmc1
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];
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macro setSPEFSCR_L(result) {
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spef_finv = nan(result);
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spef_finvs = spef_finvs | spef_finv;
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}
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macro setSPEFSCR_H(result) {
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spef_finvh = nan(result);
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spef_finvs = spef_finvs | spef_finvh;
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}
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macro setSummarySPEFSCR() {
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spef_sov = spef_sov | spef_ov;
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spef_sovh = spef_sovh | spef_ovh;
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spef_finxs = spef_finxs | spef_fx | spef_fxh;
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spef_finvs = spef_finvs | spef_finv | spef_finvh;
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spef_fdbzs = spef_fdbzs | spef_fdbz | spef_fdbzh;
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spef_funfs = spef_funfs | spef_funf | spef_funfh;
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spef_fovfs = spef_fovfs | spef_fovf | spef_fovfh;
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}
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macro setSPEFSCRAddFlags_L(op1, op2, result) {
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setSPEFSCR_L(result);
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spef_fx = spef_fx | nan(op1) | nan(op2);
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spef_finv = spef_fx;
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setSummarySPEFSCR();
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}
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macro setSPEFSCRAddFlags_H(op1, op2, result) {
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setSPEFSCR_H(result);
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spef_fxh = spef_fxh | nan(op1) | nan(op2);
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spef_finvh = spef_fxh;
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setSummarySPEFSCR();
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}
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macro setSPEFSCRDivFlags_L(op1, op2, result) {
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setSPEFSCR_L(result);
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spef_fdbz = spef_fdbz | (op2 f== 0);
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spef_fx = spef_fx | nan(op1) | nan(op2);
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spef_finv = spef_fx;
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setSummarySPEFSCR();
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}
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macro setSPEFSCRDivFlags_H(op1, op2, result) {
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setSPEFSCR_H(result);
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spef_fdbzh = spef_fdbzh | (op2 f== 0);
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spef_fxh = spef_fxh | nan(op1) | nan(op2);
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spef_finvh = spef_fxh;
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setSummarySPEFSCR();
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}
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macro setSPEFSCRMulFlags_L(op1, op2, result) {
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setSPEFSCR_L(result);
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spef_fx = spef_fx | nan(op1) | nan(op2);
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spef_finv = spef_fx;
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setSummarySPEFSCR();
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}
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macro setSPEFSCRMulFlags_H(op1, op2, result) {
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setSPEFSCR_H(result);
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spef_fxh = spef_fxh | nan(op1) | nan(op2);
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spef_finvh = spef_fxh;
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setSummarySPEFSCR();
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}
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macro setSPEFSCRSubFlags_L(op1, op2, result) {
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setSPEFSCR_L(result);
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spef_fx = spef_fx | nan(op1) | nan(op2);
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spef_finv = spef_fx;
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setSummarySPEFSCR();
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}
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macro setSPEFSCRSubFlags_H(op1, op2, result) {
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setSPEFSCR_H(result);
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spef_fxh = spef_fxh | nan(op1) | nan(op2);
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spef_finvh = spef_fxh;
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setSummarySPEFSCR();
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}
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macro packSPEFSCR(tmp) {
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packbits(tmp,
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spef_sovh, spef_ovh, spef_fgh, spef_fxh, spef_finvh, spef_fdbzh, spef_funfh, spef_fovfh,
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spef_reserved1, spef_reserved2,
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spef_finxs, spef_finvs, spef_fdbzs, spef_funfs, spef_fovfs,
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spef_reserved3,
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spef_sov, spef_ov, spef_fg, spef_fx, spef_finv, spef_fdbz, spef_funf, spef_fovf,
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spef_reserved4,
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spef_finxe, spef_finve, spef_fdbze, spef_funfe, spef_fovfe, spef_frmc0, spef_frmc1 );
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}
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macro unpackSPEFSCR(tmp) {
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unpackbits(tmp,
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spef_sovh, spef_ovh, spef_fgh, spef_fxh, spef_finvh, spef_fdbzh, spef_funfh, spef_fovfh,
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spef_reserved1, spef_reserved2,
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spef_finxs, spef_finvs, spef_fdbzs, spef_funfs, spef_fovfs,
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spef_reserved3,
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spef_sov, spef_ov, spef_fg, spef_fx, spef_finv, spef_fdbz, spef_funf, spef_fovf,
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spef_reserved4,
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spef_finxe, spef_finve, spef_fdbze, spef_funfe, spef_fovfe, spef_frmc0, spef_frmc1 );
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}
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