799 lines
20 KiB
Plaintext
799 lines
20 KiB
Plaintext
# Based on "PowerISA Version 2.06 Revision B" document dated July 23, 2010
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# Category: SPE.Embedded Float Scalar Double
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# version 1.0
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# =================================================================
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# Page 576
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# efdabs rT,rA
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# ISA-cmt: efdabs - Floating-Point Double-Precision Absolute Value
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# ISA-info: efdabs - Form "EVX" Page 576 Category "SP.FD"
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# binutils: e500.d: 34: 10 a4 02 e4 efdabs r5,r4
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:efdabs D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=740
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{
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D = abs( A );
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}
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# =================================================================
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# Page 577
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# efdadd rT,rA,rB
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# ISA-cmt: efdadd - Floating-Point Double-Precision Add
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# ISA-info: efdadd - Form "EVX" Page 577 Category "SP.FD"
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# binutils: e500.d: 40: 10 a4 1a e0 efdadd r5,r4,r3
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:efdadd D,A,B is OP=4 & D & A & B & XOP_0_10=736
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{
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D = A f+ B;
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setSPEFSCRAddFlags_L( A, B, D );
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}
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# =================================================================
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# Page 582
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# efdcfs rT,rB
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# ISA-cmt: efdcfs - Floating-Point Double-Precision Convert from Single-Precision
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# ISA-info: efdcfs - Form "EVX" Page 582 Category "SP.FD"
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# binutils: e500.d: a4: 10 a0 22 ef efdcfs r5,r4
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:efdcfs D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=751
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{
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D = float2float( B:4 );
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setSPEFSCR_L( D );
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setSummarySPEFSCR();
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}
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# =================================================================
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# Page 580
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# efdcfsf rT,rB
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# ISA-cmt: efdcfsf - Convert Floating-Point Double-Precision from Signed Fraction
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# ISA-info: efdcfsf - Form "EVX" Page 580 Category "SP.FD"
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# binutils: e500.d: 7c: 10 a0 22 f3 efdcfsf r5,r4
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:efdcfsf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=755
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{
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# load fractional divisor as a float
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tmpA:4 = 0x80000000;
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tmpA = int2float( tmpA );
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setSPEFSCR_L( tmpA );
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# check if negative
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if ( ( B:4 & 0x80000000 ) != 0 ) goto <negative>;
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# float the fractional portion of register B
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tmpB:4 = int2float( B:4 );
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setSPEFSCR_L( tmpB );
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tmpB = tmpB f/ tmpA;
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setSPEFSCRDivFlags_L( tmpB, tmpA, tmpB );
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goto <done>;
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<negative>
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# float the fractional portion of register B, 2's complement negate
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tmpB = int2float( -( B:4 ) );
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setSPEFSCR_L( tmpB );
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tmpB = tmpB f/ tmpA;
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setSPEFSCRDivFlags_L( tmpB, tmpA, tmpB );
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# negate the float
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tmpB = f-( tmpB );
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setSPEFSCR_L( tmpB );
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<done>
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tmpC:8 = float2float( tmpB );
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setSPEFSCR_L( tmpC );
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setSummarySPEFSCR();
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D = tmpC;
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}
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# =================================================================
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# Page 579
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# efdcfsi rT,rB
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# ISA-cmt: efdcfsi - Convert Floating-Point Double-Precision from Signed Integer
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# ISA-info: efdcfsi - Form "EVX" Page 579 Category "SP.FD"
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# binutils: e500.d: 6c: 10 a0 22 f1 efdcfsi r5,r4
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:efdcfsi D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=753
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{
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# check if negative
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if ( ( B:4 & 0x80000000 ) != 0 ) goto <negative>;
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# float the integer portion of register B
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tmpB:8 = int2float( B:4 );
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setSPEFSCR_L( tmpB );
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goto <done>;
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<negative>
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# float the integer portion of register B, 2's complement negate
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tmpB = int2float( -( B:4 ) );
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setSPEFSCR_L( tmpB );
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# negate the float
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tmpB = f-( tmpB );
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setSPEFSCR_L( tmpB );
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<done>
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setSummarySPEFSCR();
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D = tmpB;
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}
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# =================================================================
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# Page 580
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# efdcfsid rT,rB
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# ISA-cmt: efdcfsid - Convert Floating-Point Double-Precision from Signed Integer Doubleword
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# ISA-info: efdcfsid - Form "EVX" Page 580 Category "SP.FD"
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# binutils: e500.d: 70: 10 a0 22 e3 efdcfsid r5,r4
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:efdcfsid D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=739
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{
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# check if negative
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if ( ( B & 0x8000000000000000 ) != 0 ) goto <negative>;
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# float the integer portion of register B
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tmpB:8 = int2float( B );
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setSPEFSCR_L( tmpB );
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goto <done>;
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<negative>
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# float the integer portion of register B, 2's complement negate
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tmpB = int2float( -( B ) );
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setSPEFSCR_L( tmpB );
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# negate the float
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tmpB = f-( tmpB );
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setSPEFSCR_L( tmpB );
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<done>
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setSummarySPEFSCR();
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D = tmpB;
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}
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# =================================================================
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# Page 580
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# efdcfuf rT,rB
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# ISA-cmt: efdcfuf - Convert Floating-Point Double-Precision from Unsigned Fraction
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# ISA-info: efdcfuf - Form "EVX" Page 580 Category "SP.FD"
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# binutils: e500.d: 80: 10 a0 22 f2 efdcfuf r5,r4
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:efdcfuf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=754
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{
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# load fractional divisor as a float
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tmpA:8 = 0x0000000100000000;
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tmpA = int2float( tmpA );
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setSPEFSCR_L( tmpA );
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# float the fractional portion of register B
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tmpB:8 = int2float( B:4 );
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setSPEFSCR_L( tmpB );
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tmpB = tmpB f/ tmpA;
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setSPEFSCRDivFlags_L( tmpB, tmpA, tmpB );
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D = tmpB;
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}
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# =================================================================
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# Page 579
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#efdcfui rT,rB
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# ISA-cmt: efdcfui - Convert Floating-Point Double-Precision from Unsigned Integer
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# ISA-info: efdcfui - Form "EVX" Page 579 Category "SP.FD"
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# binutils: e500.d: 74: 10 a0 22 f0 efdcfui r5,r4
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:efdcfui D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=752
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{
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tmp:8 = int2float( B:4 );
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setSPEFSCR_L( tmp );
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setSummarySPEFSCR();
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D = tmp;
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}
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# =================================================================
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# Page 580
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#efdcfuid rT,rB
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# ISA-cmt: efdcfuid - Convert Floating-Point Double-Precision from Unsigned Integer Doubleword
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# ISA-info: efdcfuid - Form "EVX" Page 580 Category "SP.FD"
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# binutils: e500.d: 78: 10 a0 22 e2 efdcfuid r5,r4
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:efdcfuid D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=738
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{
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tmp:8 = int2float( B );
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setSPEFSCR_L( tmp );
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setSummarySPEFSCR();
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D = tmp;
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}
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# =================================================================
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# Page 578
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# efdcmpeq CRFD,rA,rB
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# ISA-cmt: efdcmpeq - Floating-Point Double-Precision Compare Equal
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# ISA-info: efdcmpeq - Form "EVX" Page 578 Category "SP.FD"
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# binutils: e500.d: 58: 12 84 1a ee efdcmpeq cr5,r4,r3
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:efdcmpeq CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=750
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{
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CRFD = A f== B;
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}
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# =================================================================
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# Page 578
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# efdcmpgt CRFD,rA,rB
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# ISA-cmt: efdcmpgt - Floating-Point Double-Precision Compare Greater Than
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# ISA-info: efdcmpgt - Form "EVX" Page 578 Category "SP.FD"
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# binutils: e500.d: 50: 12 84 1a ec efdcmpgt cr5,r4,r3
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:efdcmpgt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=748
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{
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CRFD = A f> B;
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}
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# =================================================================
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# Page 578
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# efdcmplt CRFD,rA,rB
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# ISA-cmt: efdcmplt - Floating-Point Double-Precision Compare Less Than
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# ISA-info: efdcmplt - Form "EVX" Page 578 Category "SP.FD"
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# binutils: e500.d: 54: 12 84 1a ed efdcmplt cr5,r4,r3
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:efdcmplt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=749
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{
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CRFD = A f< B;
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}
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# =================================================================
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# Page 578
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# efdctsf rT,rB
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# ISA-cmt: efdctsf - Convert Floating-Point Double-Precision to Signed Fraction
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# ISA-info: efdctsf - Form "EVX" Page 582 Category "SP.FD"
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# binutils: e500.d: 9c: 10 a0 22 f7 efdctsf r5,r4
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:efdctsf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=759
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{
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# multiply by 0x8000 0000 0000 0000 to scale the fraction up to integer range
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# load fractional multiplier as a float
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tmpM:8 = 0x8000000000000000;
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tmpM = int2float( tmpM );
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setSPEFSCR_L( tmpM );
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# load saturation limit as a float
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tmpL:8 = 0x8000000000000000 - 1;
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tmpL = int2float( tmpL );
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setSPEFSCR_L( tmpL );
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# scale the saturation limit to a fractional float
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tmpL = tmpL f/ tmpM;
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setSPEFSCRDivFlags_L( tmpL, tmpM, tmpL );
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tmpB:8 = B;
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# check if less than or equal to positive saturation limit
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if ( tmpB f<= tmpL ) goto <check_negative>;
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# set to positive saturation
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tmpB = tmpL;
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spef_fx = 1;
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spef_finxs = 1;
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spef_fg = 1;
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goto <done>;
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<check_negative>
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# check if greater than or equal to negative saturation limit
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tmpL = f-( tmpL );
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if ( tmpB f>= tmpL ) goto <done>;
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# set to negative saturation
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tmpB = tmpL;
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spef_fx = 1;
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spef_finxs = 1;
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spef_fg = 1;
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<done>
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# scale the fractional portion up to integer side of mantissa
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tmpB = tmpB f* tmpM;
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setSPEFSCRMulFlags_L( tmpB, tmpM, tmpB );
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# truncate back to signed fraction format
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tmpC:8 = trunc( tmpB );
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setSPEFSCR_L( tmpB );
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setSummarySPEFSCR();
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D = tmpC;
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}
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# =================================================================
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# Page 580
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# efdctsi rT,rB
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# ISA-cmt: efdctsi - Convert Floating-Point Double-Precision to Signed Integer
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# ISA-info: efdctsi - Form "EVX" Page 580 Category "SP.FD"
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# binutils: e500.d: 84: 10 a0 22 f5 efdctsi r5,r4
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:efdctsi D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=757
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{
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# create zero float constant
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tmpA:8 = 0;
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tmpA = int2float( tmpA );
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# check if negative
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if ( B f< tmpA ) goto <negative>;
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tmpB:8 = round( B );
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setSPEFSCR_L( tmpB );
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# limit to positive saturation
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if ( tmpB <= 0x000000007FFFFFFF ) goto <positive_clipped>;
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tmpB = 0x000000007FFFFFFF;
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spef_fx = 1;
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spef_finxs = 1;
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spef_fg = 1;
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<positive_clipped>
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goto <done>;
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<negative>
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# negate the float
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tmpB = round( f-( B ) );
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setSPEFSCR_L( tmpB );
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# limit to negative saturation
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if ( tmpB <= 0x0000000080000000 ) goto <negative_clipped>;
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tmpB = 0x0000000080000000;
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spef_fx = 1;
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spef_finxs = 1;
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spef_fg = 1;
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<negative_clipped>
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# negate the signed int
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tmpB = -( tmpB );
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<done>
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setSummarySPEFSCR();
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# assign to lower word of D
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D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 );
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}
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# =================================================================
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# Page 581
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# efdctsidz rT,rB
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# ISA-cmt: efdctsidz - Convert Floating-Point Double-Precision to Signed Integer Doubleword with Round toward Zero
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# ISA-info: efdctsidz - Form "EVX" Page 581 Category "SP.FD"
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# binutils: e500.d: 88: 10 a0 22 eb efdctsidz r5,r4
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# Note: This may not work correctly as the number approaches saturation; too little (16 digits) precision in mantissa
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:efdctsidz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=747
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{
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# create zero float constant
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tmpA:8 = 0;
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tmpA = int2float( tmpA );
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tmpB:8 = B;
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# check if negative
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if ( tmpB f< tmpA ) goto <negative>;
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# load saturation limit as a float
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tmpL:8 = 0x8000000000000000 - 1;
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tmpL = int2float( tmpL );
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setSPEFSCR_L( tmpL );
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# limit to saturation
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if ( tmpB <= tmpL ) goto <positive_clipped>;
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tmpB = tmpL;
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spef_fx = 1;
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spef_finxs = 1;
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spef_fg = 1;
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<positive_clipped>
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tmpB = trunc( tmpB );
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setSPEFSCR_L( tmpB );
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goto <done>;
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<negative>
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# load saturation limit as a float
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tmpL = 0x8000000000000000;
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tmpL = int2float( tmpL );
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setSPEFSCR_L( tmpL );
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# negate float (make positive)
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tmpB = f-( tmpB );
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# limit to saturation
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if ( tmpB <= tmpL ) goto <negative_clipped>;
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tmpB = tmpL;
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spef_fx = 1;
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spef_finxs = 1;
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spef_fg = 1;
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<negative_clipped>
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tmpB = trunc( tmpB );
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setSPEFSCR_L( tmpB );
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# negate the signed int
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tmpB = -( tmpB );
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<done>
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setSummarySPEFSCR();
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D = tmpB;
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}
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# =================================================================
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# Page 582
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# efdctsiz rT,rB
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# ISA-cmt: efdctsiz - Convert Floating-Point Double-Precision to Signed Integer with Round toward Zero
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# ISA-info: efdctsiz - Form "EVX" Page 582 Category "SP.FD"
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# binutils: e500.d: 8c: 10 a0 22 fa efdctsiz r5,r4
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:efdctsiz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=762
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{
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# create zero float constant
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tmpA:8 = 0;
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tmpA = int2float( tmpA );
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# check if negative
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if ( B f< tmpA ) goto <negative>;
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tmpB:8 = trunc( B );
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setSPEFSCR_L( tmpB );
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# limit to positive saturation
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if ( tmpB <= 0x000000007FFFFFFF ) goto <positive_clipped>;
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tmpB = 0x000000007FFFFFFF;
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spef_fx = 1;
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spef_finxs = 1;
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spef_fg = 1;
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<positive_clipped>
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goto <done>;
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<negative>
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# negate the float
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tmpB = trunc( f-( B ) );
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setSPEFSCR_L( tmpB );
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# limit to negative saturation
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if ( tmpB <= 0x0000000080000000 ) goto <negative_clipped>;
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tmpB = 0x0000000080000000;
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spef_fx = 1;
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spef_finxs = 1;
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spef_fg = 1;
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<negative_clipped>
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# negate the signed int
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tmpB = -( tmpB );
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<done>
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setSummarySPEFSCR();
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# assign to lower word of D
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D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 );
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}
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# =================================================================
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# Page 582
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|
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# efdctuf rT,rB
|
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# ISA-cmt: efdctuf - Convert Floating-Point Double-Precision to Unsigned Fraction
|
|
# ISA-info: efdctuf - Form "EVX" Page 582 Category "SP.FD"
|
|
# binutils: e500.d: a0: 10 a0 22 f6 efdctuf r5,r4
|
|
:efdctuf D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=758
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|
{
|
|
# multiply by 0x0000 0001 0000 0000 to scale the fraction up to integer range
|
|
|
|
# load fractional multiplier as a float
|
|
tmpM:8 = 0x0000000100000000;
|
|
tmpM = int2float( tmpM );
|
|
setSPEFSCR_L( tmpM );
|
|
|
|
# load saturation limit as a float
|
|
tmpL:8 = 0x0000000100000000 - 1;
|
|
tmpL = int2float( tmpL );
|
|
setSPEFSCR_L( tmpL );
|
|
|
|
# scale the saturation limit to a fractional float
|
|
tmpL = tmpL f/ tmpM;
|
|
setSPEFSCRDivFlags_L( tmpL, tmpM, tmpL );
|
|
|
|
# get B float up to 64 bit width
|
|
tmpB:8 = B;
|
|
setSPEFSCR_L( tmpB );
|
|
|
|
# check if less than or equal to positive saturation limit
|
|
if ( tmpB f<= tmpL ) goto <done>;
|
|
|
|
# set to saturation
|
|
tmpB = tmpL;
|
|
spef_fx = 1;
|
|
spef_finxs = 1;
|
|
spef_fg = 1;
|
|
|
|
<done>
|
|
|
|
# scale the fractional portion up to integer side of mantissa
|
|
tmpB = tmpB f* tmpM;
|
|
setSPEFSCRMulFlags_L( tmpB, tmpM, tmpB );
|
|
|
|
# truncate back to integer
|
|
tmpC:4 = trunc( tmpB );
|
|
setSPEFSCR_L( tmpC );
|
|
|
|
setSummarySPEFSCR();
|
|
|
|
# assign to lower word of D
|
|
D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpC );
|
|
}
|
|
|
|
|
|
# =================================================================
|
|
# Page 580
|
|
|
|
# efdctui rT,rB
|
|
# ISA-cmt: efdctui - Convert Floating-Point Double-Precision to Unsigned Integer
|
|
# ISA-info: efdctui - Form "EVX" Page 580 Category "SP.FD"
|
|
# binutils: e500.d: 90: 10 a0 22 f4 efdctui r5,r4
|
|
:efdctui D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=756
|
|
{
|
|
tmpB:8 = B;
|
|
|
|
# load saturation limit as a float
|
|
tmpL:8 = 0x00000000FFFFFFFF;
|
|
tmpL = int2float( tmpL );
|
|
setSPEFSCR_L( tmpL );
|
|
|
|
# limit to saturation
|
|
if ( tmpB f<= tmpL ) goto <positive_clipped>;
|
|
tmpB = tmpL;
|
|
spef_fx = 1;
|
|
spef_finxs = 1;
|
|
spef_fg = 1;
|
|
|
|
<positive_clipped>
|
|
|
|
# round back to integer
|
|
tmpC:4 = trunc(round( tmpB ));
|
|
setSPEFSCR_L( tmpB );
|
|
|
|
setSummarySPEFSCR();
|
|
|
|
# assign to lower word of D
|
|
D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpC );
|
|
}
|
|
|
|
|
|
# =================================================================
|
|
# Page 581
|
|
|
|
# efdctuidz rT,rB
|
|
# ISA-cmt: efdctuidz - Convert Floating-Point Double-Precision to Unsigned Integer Doubleword with Round toward Zero
|
|
# ISA-info: efdctuidz - Form "EVX" Page 581 Category "SP.FD"
|
|
# binutils: e500.d: 94: 10 a0 22 ea efdctuidz r5,r4
|
|
:efdctuidz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=746
|
|
{
|
|
tmpB:8 = B;
|
|
|
|
# load saturation limit as a float
|
|
tmpL:8 = 0xFFFFFFFFFFFFFFFF;
|
|
tmpL = int2float( tmpL );
|
|
setSPEFSCR_L( tmpL );
|
|
|
|
# limit to saturation
|
|
if ( tmpB f<= tmpL ) goto <positive_clipped>;
|
|
tmpB = tmpL;
|
|
spef_fx = 1;
|
|
spef_finxs = 1;
|
|
spef_fg = 1;
|
|
|
|
<positive_clipped>
|
|
|
|
tmpB = trunc( tmpB );
|
|
|
|
setSummarySPEFSCR();
|
|
|
|
D = tmpB;
|
|
}
|
|
|
|
|
|
# =================================================================
|
|
# Page 582
|
|
|
|
# efdctuiz rT,rB
|
|
# ISA-cmt: efdctuiz - Convert Floating-Point Double-Precision to Unsigned Integer with Round toward Zero
|
|
# ISA-info: efdctuiz - Form "EVX" Page 582 Category "SP.FD"
|
|
# binutils: e500.d: 98: 10 a0 22 f8 efdctuiz r5,r4
|
|
:efdctuiz D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=760
|
|
{
|
|
tmpB:8 = B;
|
|
|
|
# load saturation limit as a float
|
|
tmpL:8 = 0x00000000FFFFFFFF;
|
|
tmpL = int2float( tmpL );
|
|
setSPEFSCR_L( tmpL );
|
|
|
|
# limit to saturation
|
|
if ( tmpB f<= tmpL ) goto <positive_clipped>;
|
|
tmpB = tmpL;
|
|
spef_fx = 1;
|
|
spef_finxs = 1;
|
|
spef_fg = 1;
|
|
|
|
<positive_clipped>
|
|
|
|
tmpB = trunc( tmpB );
|
|
|
|
setSummarySPEFSCR();
|
|
|
|
# assign to lower word of D
|
|
D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB:4 );
|
|
}
|
|
|
|
|
|
# =================================================================
|
|
# Page 577
|
|
|
|
# efddiv rT,rA,rB
|
|
# ISA-cmt: efddiv - Floating-Point Double-Precision Divide
|
|
# ISA-info: efddiv - Form "EVX" Page 577 Category "SP.FD"
|
|
# binutils: e500.d: 4c: 10 a4 1a e9 efddiv r5,r4,r3
|
|
:efddiv D,A,B is OP=4 & D & A & B & XOP_0_10=745
|
|
{
|
|
D = A f/ B;
|
|
setSPEFSCRDivFlags_L( A, B, D );
|
|
}
|
|
|
|
|
|
# =================================================================
|
|
# Page 577
|
|
|
|
# efdmul rT,rA,rB
|
|
# ISA-cmt: efdmul - Floating-Point Double-Precision Multiply
|
|
# ISA-info: efdmul - Form "EVX" Page 577 Category "SP.FD"
|
|
# binutils: e500.d: 48: 10 a4 1a e8 efdmul r5,r4,r3
|
|
:efdmul D,A,B is OP=4 & D & A & B & XOP_0_10=744
|
|
{
|
|
D = A f* B;
|
|
setSPEFSCRMulFlags_L( A, B, D );
|
|
}
|
|
|
|
|
|
# =================================================================
|
|
# Page 576
|
|
|
|
# efdnabs rT,rA
|
|
# ISA-cmt: efdnabs - Floating-Point Double-Precision Negative Absolute Value
|
|
# ISA-info: efdnabs - Form "EVX" Page 576 Category "SP.FD"
|
|
# binutils: e500.d: 38: 10 a4 02 e5 efdnabs r5,r4
|
|
:efdnabs D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=741
|
|
{
|
|
D = f- ( abs( A ) );
|
|
}
|
|
|
|
|
|
# =================================================================
|
|
# Page 577
|
|
|
|
# efdneg rT,rA
|
|
# ISA-cmt: efdneg - Floating-Point Double-Precision Negate
|
|
# ISA-info: efdneg - Form "EVX" Page 576 Category "SP.FD"
|
|
# binutils: e500.d: 3c: 10 a4 02 e6 efdneg r5,r4
|
|
:efdneg D,A is OP=4 & D & A & BITS_11_15=0 & XOP_0_10=742
|
|
{
|
|
D = f-( A );
|
|
}
|
|
|
|
|
|
# =================================================================
|
|
# Page 577
|
|
|
|
# efdsub rT,rA,rB
|
|
# ISA-cmt: efdsub - Floating-Point Double-Precision Subtract
|
|
# ISA-info: efdsub - Form "EVX" Page 577 Category "SP.FD"
|
|
# binutils: e500.d: 44: 10 a4 1a e1 efdsub r5,r4,r3
|
|
:efdsub D,A,B is OP=4 & D & A & B & XOP_0_10=737
|
|
{
|
|
D = A f- B;
|
|
setSPEFSCRSubFlags_L( A, B, D );
|
|
}
|
|
|
|
|
|
# =================================================================
|
|
# Page 579
|
|
|
|
# efdtsteq CRFD,rA,rB
|
|
# ISA-cmt: efdtsteq - Floating-Point Double-Precision Test Equal
|
|
# ISA-info: efdtsteq - Form "EVX" Page 579 Category "SP.FD"
|
|
# binutils: e500.d: 68: 12 84 1a fe efdtsteq cr5,r4,r3
|
|
:efdtsteq CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=766
|
|
{
|
|
CRFD = A f== B;
|
|
}
|
|
|
|
|
|
# =================================================================
|
|
# Page 578
|
|
|
|
# efdtstgt CRFD,rA,rB
|
|
# ISA-cmt: efdtstgt - Floating-Point Double-Precision Test Greater Than
|
|
# ISA-info: efdtstgt - Form "EVX" Page 578 Category "SP.FD"
|
|
# binutils: e500.d: 5c: 12 84 1a fc efdtstgt cr5,r4,r3
|
|
# binutils: e500.d: 60: 12 84 1a fc efdtstgt cr5,r4,r3
|
|
:efdtstgt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=764
|
|
{
|
|
CRFD = A f> B;
|
|
}
|
|
|
|
|
|
# =================================================================
|
|
# Page 579
|
|
|
|
# efdtstlt CRFD,rA,rB
|
|
# ISA-cmt: efdtstlt - Floating-Point Double-Precision Test Less Than
|
|
# ISA-info: efdtstlt - Form "EVX" Page 579 Category "SP.FD"
|
|
# binutils: e500.d: 64: 12 84 1a fd efdtstlt cr5,r4,r3
|
|
:efdtstlt CRFD,A,B is OP=4 & CRFD & BITS_21_22=0 & A & B & XOP_0_10=765
|
|
{
|
|
CRFD = A f< B;
|
|
}
|
|
|
|
|
|
# =================================================================
|
|
# Page 583
|
|
|
|
# efscfd rT,rB
|
|
# ISA-cmt: efscfd - Floating-Point Single-Precision Convert from Double-Precision
|
|
# ISA-info: efscfd - Form "EVX" Page 583 Category "SP.FD"
|
|
# binutils: e500.d: 30: 10 a0 22 cf efscfd r5,r4
|
|
:efscfd D,B is OP=4 & D & BITS_16_20=0 & B & XOP_0_10=719
|
|
{
|
|
tmpB:4 = float2float( B );
|
|
setSPEFSCR_L( tmpB );
|
|
setSummarySPEFSCR();
|
|
|
|
# assign to lower word of D
|
|
D = ( D & 0xFFFFFFFF00000000 ) | zext( tmpB );
|
|
}
|