143 lines
3.1 KiB
Plaintext
143 lines
3.1 KiB
Plaintext
# RISC-V Privileged Instructions
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define pcodeop wfi;
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define pcodeop sfence.vm;
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define pcodeop sfence.vma;
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# Trap-Return
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# dret 7b200073 ffffffff SIMPLE (0, 0)
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:dret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0xf640
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{
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return [dpc];
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}
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# hret 20200073 ffffffff SIMPLE (0, 0)
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# deprecated instruction in latest spec
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#:hret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x4040
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# mret 30200073 ffffffff SIMPLE (0, 0)
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:mret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x6040
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{
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return [mepc];
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}
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# sret 10200073 ffffffff SIMPLE (0, 0)
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:sret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2040
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{
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return [sepc];
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}
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# uret 00200073 ffffffff SIMPLE (0, 0)
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:uret is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x40
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{
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return [uepc];
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}
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# Interrupt-Management
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# wfi 10500073 ffffffff SIMPLE (0, 0)
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:wfi is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x20a0
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{
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wfi();
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}
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# Supervisor Memory-Management
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# sfence.vm 10400073 ffffffff SIMPLE (0, 0)
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:sfence.vm is op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op1531=0x2080
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{
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sfence.vm();
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}
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# sfence.vm s 10400073 fff07fff SIMPLE (0, 0)
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:sfence.vm rs1 is rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x104
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{
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sfence.vm(rs1);
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}
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# sfence.vma s,t 12000073 fe007fff SIMPLE (0, 0)
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:sfence.vma rs1,rs2 is rs2 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2531=0x9
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{
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sfence.vma(rs1, rs2);
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}
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# Hypervisor Memory-Management
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#TODO move to rv32h and rv64h?
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:hlv.b rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x30 & rs1 & rd & op2024=0x0
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{
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rd = sext(*[ram]:1 rs1);
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}
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:hlv.bu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x30 & rs1 & rd & op2024=0x1
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{
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rd = zext(*[ram]:1 rs1);
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}
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:hlv.h rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x32 & rs1 & rd & op2024=0x0
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{
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rd = sext(*[ram]:2 rs1);
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}
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:hlv.hu rd,rs1, is op0006=0x73 & funct3=0x4 & funct7=0x32 & rs1 & rd & op2024=0x1
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{
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rd = zext(*[ram]:2 rs1);
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}
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:hlvx.hu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x32 & rs1 & rd & op2024=0x3
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{
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rd = zext(*[ram]:2 rs1);
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}
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:hlv.w rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x34 & rs1 & rd & op2024=0x0
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{
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assignW(rd, *[ram]:4 rs1);
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}
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:hlvx.wu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x34 & rs1 & rd & op2024=0x3
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{
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zassignW(rd, *[ram]:4 rs1);
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}
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:hsv.b rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x31 & op0711=0x0 & rs1 & rs2
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{
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*[ram]:1 rs1 = rs2:1;
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}
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:hsv.h rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x33 & op0711=0x0 & rs1 & rs2
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{
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*[ram]:2 rs1 = rs2:2;
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}
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:hsv.w rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x35 & op0711=0x0 & rs1 & rs2
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{
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*[ram]:4 rs1 = rs2:4;
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}
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@if ADDRSIZE == "64"
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:hlv.wu rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x34 & rs1 & rd & op2024=0x1
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{
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rd = zext(*[ram]:4 rs1);
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}
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:hlv.d rd,rs1 is op0006=0x73 & funct3=0x4 & funct7=0x36 & rs1 & rd & op2024=0x0
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{
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rd = *[ram]:8 rs1;
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}
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:hsv.d rs1,rs2 is op0006=0x73 & funct3=0x4 & funct7=0x37 & op0711=0x0 & rs1 & rs2
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{
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*[ram]:8 rs1 = rs2;
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}
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@endif
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