ghidra/Ghidra/Processors/V850/data/languages/Helpers/Register.sinc

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#####################################################
##### Register #####
#####################################################
##### General-purpose registers (r0 to r31) #####
define register offset=0x0 size=0x4 # offset = 0 because it's the start
[
r0 r1 r2 sp gp tp r6 r7 r8 r9
r10 r11 r12 r13 r14 r15 r16 r17 r18 r19
r20 r21 r22 r23 r24 r25 r26 r27 r28 r29
ep lp
];
##### Control/Special registers #####
define register offset=0x80 size=0x4 # offset = 0x80(128) = PreOffset+PreRegister*Size = 0+32*4 = 128
[
EIPC EIPSW FEPC FEPSW ECR PSW FPSR FPEPC FPST FPCC
FPCFG SCCFG SCBP EIIC FEIC DBIC CTPC CTPSW DBPC DBPSW
CTBP DIR DBG22 DBG23 DBG24 DBG25 DBG26 DBG27 EIWR FEWR
DBWR BSEL
];
define register offset=0x0 size=0x8
[
r0r1 r2sp r4r5 r6r7 r8r9
r10r11 r12r13 r14r15 r16r17 r18r19
r20r21 r22r23 r24r25 r26r27 r28r29
_
];
define register offset=0x100 size=0x4 [ PC ]; # offset = 0x100(256) = PreOffset+PreRegister*Size = 128+32*4 = 256