143 lines
4.1 KiB
Plaintext
143 lines
4.1 KiB
Plaintext
# Due to limitations on variable length matching that preclude opcode matching afterwards, all memory addressing forms of PCLMULQDQ are decoded to PCLMULQDQ, not the macro names.
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# Display is non-standard, but semantics, and de-compilation should be correct.
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:PCLMULLQLQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x00
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{
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XmmReg1 = zext(XmmReg2[0,64]) * zext(XmmReg1[0,64]);
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}
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:PCLMULHQLQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x01
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{
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XmmReg1 = zext(XmmReg2[0,64]) * zext(XmmReg1[64,64]);
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}
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:PCLMULLQHQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x10
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{
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XmmReg1 = zext(XmmReg2[64,64]) * zext(XmmReg1[0,64]);
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}
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:PCLMULHQHQDQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; byte=0x11
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{
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XmmReg1 = zext(XmmReg2[64,64]) * zext(XmmReg1[64,64]);
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}
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:PCLMULQDQ XmmReg1, XmmReg2, imm8 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; xmmmod=3 & XmmReg1 & XmmReg2; imm8 & imm8_4 & imm8_0
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{
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if (imm8_0:1) goto <src1_b>;
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src1:16 = zext(XmmReg1[0,64]);
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goto <done1>;
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<src1_b>
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src1 = zext(XmmReg1[64,64]);
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<done1>
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if (imm8_4:1) goto <src2_b>;
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src2:16 = zext(XmmReg2[0,64]);
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goto <done2>;
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<src2_b>
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src2 = zext(XmmReg2[64,64]);
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<done2>
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XmmReg1 = src2 * src1;
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}
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:PCLMULQDQ XmmReg, m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0f; byte=0x3a; byte=0x44; XmmReg ... & m128; imm8 & imm8_4 & imm8_0
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{
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if (imm8_0:1) goto <src1_b>;
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src1:16 = zext(XmmReg[0,64]);
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goto <done1>;
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<src1_b>
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src1 = zext(XmmReg[64,64]);
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<done1>
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local m:16 = m128;
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if (imm8_4:1) goto <src2_b>;
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src2:16 = zext(m[0,64]);
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goto <done2>;
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<src2_b>
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src2 = zext(m[64,64]);
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<done2>
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XmmReg = src2 * src1;
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}
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:VPCLMULLQLQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x00
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{
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tmp:16 = zext(XmmReg2[0,64]) * zext(vexVVVV_XmmReg[0,64]);
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YmmReg1 = zext(tmp);
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}
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:VPCLMULHQLQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x01
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{
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tmp:16 = zext(XmmReg2[0,64]) * zext(vexVVVV_XmmReg[64,64]);
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YmmReg1 = zext(tmp);
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}
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:VPCLMULLQHQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x10
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{
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tmp:16 = zext(XmmReg2[64,64]) * zext(vexVVVV_XmmReg[0,64]);
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YmmReg1 = zext(tmp);
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}
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:VPCLMULHQHQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; byte=0x11
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{
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tmp:16 = zext(XmmReg2[64,64]) * zext(vexVVVV_XmmReg[64,64]);
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YmmReg1 = zext(tmp);
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}
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:VPCLMULQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; xmmmod=3 & (XmmReg1 & YmmReg1) & XmmReg2; imm8 & imm8_4 & imm8_0
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{
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if (imm8_0:1) goto <src1_b>;
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src1:16 = zext(vexVVVV_XmmReg[0,64]);
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goto <done1>;
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<src1_b>
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src1 = zext(vexVVVV_XmmReg[64,64]);
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<done1>
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if (imm8_4:1) goto <src2_b>;
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src2:16 = zext(XmmReg2[0,64]);
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goto <done2>;
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<src2_b>
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src2 = zext(XmmReg2[64,64]);
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<done2>
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tmp:16 = src2 * src1;
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YmmReg1 = zext(tmp);
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}
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:VPCLMULQDQ XmmReg1, vexVVVV_XmmReg, m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x44; (XmmReg1 & YmmReg1) ... & m128; imm8 & imm8_4 & imm8_0
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{
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if (imm8_0:1) goto <src1_b>;
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src1:16 = zext(vexVVVV_XmmReg[0,64]);
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goto <done1>;
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<src1_b>
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src1 = zext(vexVVVV_XmmReg[64,64]);
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<done1>
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local m:16 = m128;
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if (imm8_4:1) goto <src2_b>;
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src2:16 = zext(m[0,64]);
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goto <done2>;
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<src2_b>
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src2 = zext(m[64,64]);
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<done2>
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tmp:16 = src2 * src1;
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YmmReg1 = zext(tmp);
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}
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