ghidra/Ghidra/Processors/x86/data/languages/sha.sinc

54 lines
1.9 KiB
Plaintext

# INFO This file automatically generated by andre on Fri Mar 16 15:13:25 2018
# INFO Direct edits to this file may be lost in future updates
# INFO Command line arguments: ['--sinc', '--cpuid-match', 'SHA']
# SHA1RNDS4 4-602 PAGE 1722 LINE 89511
define pcodeop sha1rnds4_sha ;
:SHA1RNDS4 XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & byte=0x0F; byte=0x3A; byte=0xCC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128; imm8
{
XmmReg1 = sha1rnds4_sha( XmmReg1, XmmReg2_m128, imm8:1 );
}
# SHA1NEXTE 4-604 PAGE 1724 LINE 89602
define pcodeop sha1nexte_sha ;
:SHA1NEXTE XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xC8; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
XmmReg1 = sha1nexte_sha( XmmReg1, XmmReg2_m128 );
}
# SHA1MSG1 4-605 PAGE 1725 LINE 89654
define pcodeop sha1msg1_sha ;
:SHA1MSG1 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xC9; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
XmmReg1 = sha1msg1_sha( XmmReg1, XmmReg2_m128 );
}
# SHA1MSG2 4-606 PAGE 1726 LINE 89708
define pcodeop sha1msg2_sha ;
:SHA1MSG2 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCA; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
XmmReg1 = sha1msg2_sha( XmmReg1, XmmReg2_m128 );
}
# SHA256RNDS2 4-607 PAGE 1727 LINE 89765
define pcodeop sha256rnds2_sha ;
:SHA256RNDS2 XmmReg1, XmmReg2_m128, XMM0 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCB; (XmmReg1 & YmmReg1) ... & XmmReg2_m128 & XMM0
{
XmmReg1 = sha256rnds2_sha( XmmReg1, XmmReg2_m128, XMM0 );
}
# SHA256MSG1 4-609 PAGE 1729 LINE 89847
define pcodeop sha256msg1_sha ;
:SHA256MSG1 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCC; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
XmmReg1 = sha256msg1_sha( XmmReg1, XmmReg2_m128 );
}
# SHA256MSG2 4-610 PAGE 1730 LINE 89900
define pcodeop sha256msg2_sha ;
:SHA256MSG2 XmmReg1, XmmReg2_m128 is vexMode=0 & byte=0x0F; byte=0x38; byte=0xCD; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
{
XmmReg1 = sha256msg2_sha( XmmReg1, XmmReg2_m128 );
}