253 lines
7.2 KiB
C
253 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include "stm32_firewall.h"
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/*
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* RIFSC offset register
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*/
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#define RIFSC_RISC_SECCFGR0 0x10
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#define RIFSC_RISC_PRIVCFGR0 0x30
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#define RIFSC_RISC_PER0_CIDCFGR 0x100
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#define RIFSC_RISC_PER0_SEMCR 0x104
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#define RIFSC_RISC_HWCFGR2 0xFEC
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/*
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* SEMCR register
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*/
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#define SEMCR_MUTEX BIT(0)
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/*
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* HWCFGR2 register
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*/
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#define HWCFGR2_CONF1_MASK GENMASK(15, 0)
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#define HWCFGR2_CONF2_MASK GENMASK(23, 16)
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#define HWCFGR2_CONF3_MASK GENMASK(31, 24)
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/*
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* RIFSC miscellaneous
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*/
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#define RIFSC_RISC_CFEN_MASK BIT(0)
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#define RIFSC_RISC_SEM_EN_MASK BIT(1)
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#define RIFSC_RISC_SCID_MASK GENMASK(6, 4)
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#define RIFSC_RISC_SEML_SHIFT 16
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#define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16)
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#define RIFSC_RISC_PER_ID_MASK GENMASK(31, 24)
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#define RIFSC_RISC_PERx_CID_MASK (RIFSC_RISC_CFEN_MASK | \
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RIFSC_RISC_SEM_EN_MASK | \
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RIFSC_RISC_SCID_MASK | \
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RIFSC_RISC_SEMWL_MASK)
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#define IDS_PER_RISC_SEC_PRIV_REGS 32
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/* RIF miscellaneous */
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/*
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* CIDCFGR register fields
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*/
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#define CIDCFGR_CFEN BIT(0)
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#define CIDCFGR_SEMEN BIT(1)
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#define CIDCFGR_SEMWL(x) BIT(RIFSC_RISC_SEML_SHIFT + (x))
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#define SEMWL_SHIFT 16
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/* Compartiment IDs */
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#define RIF_CID0 0x0
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#define RIF_CID1 0x1
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static bool stm32_rifsc_is_semaphore_available(void __iomem *addr)
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{
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return !(readl(addr) & SEMCR_MUTEX);
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}
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static int stm32_rif_acquire_semaphore(struct stm32_firewall_controller *stm32_firewall_controller,
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int id)
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{
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void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id;
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writel(SEMCR_MUTEX, addr);
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/* Check that CID1 has the semaphore */
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if (stm32_rifsc_is_semaphore_available(addr) ||
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FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) != RIF_CID1)
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return -EACCES;
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return 0;
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}
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static void stm32_rif_release_semaphore(struct stm32_firewall_controller *stm32_firewall_controller,
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int id)
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{
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void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id;
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if (stm32_rifsc_is_semaphore_available(addr))
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return;
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writel(SEMCR_MUTEX, addr);
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/* Ok if another compartment takes the semaphore before the check */
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WARN_ON(!stm32_rifsc_is_semaphore_available(addr) &&
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FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) == RIF_CID1);
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}
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static int stm32_rifsc_grant_access(struct stm32_firewall_controller *ctrl, u32 firewall_id)
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{
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struct stm32_firewall_controller *rifsc_controller = ctrl;
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u32 reg_offset, reg_id, sec_reg_value, cid_reg_value;
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int rc;
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if (firewall_id >= rifsc_controller->max_entries) {
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dev_err(rifsc_controller->dev, "Invalid sys bus ID %u", firewall_id);
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return -EINVAL;
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}
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/*
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* RIFSC_RISC_PRIVCFGRx and RIFSC_RISC_SECCFGRx both handle configuration access for
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* 32 peripherals. On the other hand, there is one _RIFSC_RISC_PERx_CIDCFGR register
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* per peripheral
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*/
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reg_id = firewall_id / IDS_PER_RISC_SEC_PRIV_REGS;
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reg_offset = firewall_id % IDS_PER_RISC_SEC_PRIV_REGS;
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sec_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id);
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cid_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * firewall_id);
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/* First check conditions for semaphore mode, which doesn't take into account static CID. */
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if ((cid_reg_value & CIDCFGR_SEMEN) && (cid_reg_value & CIDCFGR_CFEN)) {
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if (cid_reg_value & BIT(RIF_CID1 + SEMWL_SHIFT)) {
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/* Static CID is irrelevant if semaphore mode */
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goto skip_cid_check;
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} else {
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dev_dbg(rifsc_controller->dev,
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"Invalid bus semaphore configuration: index %d\n", firewall_id);
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return -EACCES;
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}
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}
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/*
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* Skip CID check if CID filtering isn't enabled or filtering is enabled on CID0, which
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* corresponds to whatever CID.
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*/
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if (!(cid_reg_value & CIDCFGR_CFEN) ||
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FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0)
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goto skip_cid_check;
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/* Coherency check with the CID configuration */
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if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) {
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dev_dbg(rifsc_controller->dev, "Invalid CID configuration for peripheral: %d\n",
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firewall_id);
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return -EACCES;
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}
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skip_cid_check:
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/* Check security configuration */
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if (sec_reg_value & BIT(reg_offset)) {
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dev_dbg(rifsc_controller->dev,
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"Invalid security configuration for peripheral: %d\n", firewall_id);
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return -EACCES;
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}
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/*
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* If the peripheral is in semaphore mode, take the semaphore so that
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* the CID1 has the ownership.
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*/
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if ((cid_reg_value & CIDCFGR_SEMEN) && (cid_reg_value & CIDCFGR_CFEN)) {
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rc = stm32_rif_acquire_semaphore(rifsc_controller, firewall_id);
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if (rc) {
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dev_err(rifsc_controller->dev,
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"Couldn't acquire semaphore for peripheral: %d\n", firewall_id);
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return rc;
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}
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}
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return 0;
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}
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static void stm32_rifsc_release_access(struct stm32_firewall_controller *ctrl, u32 firewall_id)
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{
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stm32_rif_release_semaphore(ctrl, firewall_id);
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}
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static int stm32_rifsc_probe(struct platform_device *pdev)
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{
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struct stm32_firewall_controller *rifsc_controller;
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struct device_node *np = pdev->dev.of_node;
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u32 nb_risup, nb_rimu, nb_risal;
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struct resource *res;
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void __iomem *mmio;
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int rc;
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rifsc_controller = devm_kzalloc(&pdev->dev, sizeof(*rifsc_controller), GFP_KERNEL);
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if (!rifsc_controller)
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return -ENOMEM;
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mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(mmio))
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return PTR_ERR(mmio);
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rifsc_controller->dev = &pdev->dev;
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rifsc_controller->mmio = mmio;
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rifsc_controller->name = dev_driver_string(rifsc_controller->dev);
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rifsc_controller->type = STM32_PERIPHERAL_FIREWALL | STM32_MEMORY_FIREWALL;
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rifsc_controller->grant_access = stm32_rifsc_grant_access;
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rifsc_controller->release_access = stm32_rifsc_release_access;
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/* Get number of RIFSC entries*/
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nb_risup = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF1_MASK;
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nb_rimu = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF2_MASK;
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nb_risal = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF3_MASK;
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rifsc_controller->max_entries = nb_risup + nb_rimu + nb_risal;
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platform_set_drvdata(pdev, rifsc_controller);
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rc = stm32_firewall_controller_register(rifsc_controller);
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if (rc) {
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dev_err(rifsc_controller->dev, "Couldn't register as a firewall controller: %d",
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rc);
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return rc;
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}
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rc = stm32_firewall_populate_bus(rifsc_controller);
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if (rc) {
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dev_err(rifsc_controller->dev, "Couldn't populate RIFSC bus: %d",
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rc);
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return rc;
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}
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/* Populate all allowed nodes */
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return of_platform_populate(np, NULL, NULL, &pdev->dev);
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}
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static const struct of_device_id stm32_rifsc_of_match[] = {
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{ .compatible = "st,stm32mp25-rifsc" },
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{}
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};
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MODULE_DEVICE_TABLE(of, stm32_rifsc_of_match);
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static struct platform_driver stm32_rifsc_driver = {
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.probe = stm32_rifsc_probe,
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.driver = {
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.name = "stm32-rifsc",
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.of_match_table = stm32_rifsc_of_match,
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},
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};
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module_platform_driver(stm32_rifsc_driver);
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MODULE_AUTHOR("Gatien Chevallier <gatien.chevallier@foss.st.com>");
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MODULE_DESCRIPTION("STMicroelectronics RIFSC driver");
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MODULE_LICENSE("GPL");
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