48 lines
1.8 KiB
Markdown
48 lines
1.8 KiB
Markdown
## SMP spin-up
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From the ADT:
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* `/arm-io/pmgr[reg]` power manager registers
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* CPU start block is at a device-dependent offset to this register
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* 0x30000 for A7-A8(X)
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* 0xd4000 for A9(X)-A11, T2
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* 0x54000 for M1 series
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* 0x34000 for M2 and M3
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* 0x28000 for M2 Pro/Max
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* 0x88000 for M3 Pro/Max
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* For multi-die systems, each die has its own power manager registers.
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The power manager registers for each die is at offset
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`die * 0x2000000000` from the registers of die 0.
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* `/cpus/cpu<n>[cpu-impl-reg]` CPU implementation registers
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* `/cpus/cpu<n>[reg]` CPU startup information
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* Bits [0:7] holds the core id
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* Bits [8:10] holds the cluster id
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* Bits [11:14] holds the die id
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A11 does not handle clusters properly, so both P and E CPUs are considered cluster 0.
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ECPUs are 0-3 while PCPUs are 4-5.
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For old firmwares, `/cpus/cpu<n>[cpu-impl-reg]` may not exist, in this case
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`/arm-io/reg[2*n+2]` can be used to find the location to write the start address.
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CPU start registers in PMGR:
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```
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offset + 0x4: System-wide CPU core startup/active bitmask
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offset + 0x8: Cluster 0 (e) CPU core startup
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offset + 0xc: Cluster 1 (p) CPU core startup
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```
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### Startup sequence
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* Write start address to RVBAR at `cpu-impl-reg + 0x00`
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* This is locked for cpu0 by iBoot, other CPUs are free to change
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* Set (1 << cpu) in `pmgr[offset + 0x4]`
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* This seems to be some kind of system-wide "core alive" signal. It is not
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required for the core to spin up, but without it AIC interrupts won't
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work, and probably other things.
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* Set (1 << core) in `pmgr[(offset + 0x8) + 4*cluster]` (that's core from 0-3, cluster 0-1)
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* This starts up the core itself.
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Core starts up at RVBAR. Chicken bits / etc must be applied as usual.
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