88 lines
2.6 KiB
Markdown
88 lines
2.6 KiB
Markdown
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# Guarded execution
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Guarded execution mode is a lateral exception level next to EL1 and EL2 which uses the same pagetables but different permissions (see SPRR). These levels are called GL1 and GL2. It's enabled with bit 1 in S3_6_C15_1_2.
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The instruction `0x00201420` is genter and switches from EL to GL and sets the PC to `S3_6_C15_C8_1`.
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`0x00201420` is gexit which returns to EL.
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```
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#define SYS_GXF_ENTER_EL1 sys_reg(3, 6, 15, 8, 1)
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```
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Guarded mode has a separate set of ELR, FAR, ESR, SPSR, VBAR and TPIDR registers just like EL1/2.
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Additionally the ASPSR register indicates if gexit should return to GL or EL.
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```
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#define SYS_TPIDR_GL1 sys_reg(3, 6, 15, 10, 1)
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#define SYS_VBAR_GL1 sys_reg(3, 6, 15, 10, 2)
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#define SYS_SPSR_GL1 sys_reg(3, 6, 15, 10, 3)
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#define SYS_ASPSR_GL1 sys_reg(3, 6, 15, 10, 4)
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#define SYS_ESR_GL1 sys_reg(3, 6, 15, 10, 5)
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#define SYS_ELR_GL1 sys_reg(3, 6, 15, 10, 6)
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#define SYS_FAR_GL1 sys_reg(3, 6, 15, 10, 7)
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```
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# SPRR
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SPRR takes the permission bits from pagetable entries and converts them into an attribute index similar to how MAIR works:
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```
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3 2 1 0
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AP[1] AP[0] UXN PXN
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```
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Note that UXN and PXN are flipped compared to APRR!
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This is then used to index into a system register where each entry has four bits:
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```
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3 2 1 0
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GL[1] GL[0] EL[1] EL[0]
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```
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GL/EL can be treated mostly separate but there are two exceptions where a specific GL permissions
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modifies what the two EL bits usually mean.
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| register value | EL page permissions | GL page permissions |
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|-|-|-|
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| `0000` | `---` | `---` |
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| `0001` | `r-x` | `---` |
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| `0010` | `r--` | `---` |
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| `0011` | `rw-` | `---` |
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| `0100` | `---` | `r-x` |
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| `0101` | `r-x` | `r-x` |
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| `0110` | `r--` | `r-x` |
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| `0111` | `---` | `r-x` |
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| `1000` | `---` | `r--` |
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| `1001` | `--x` | `r--` |
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| `1010` | `r--` | `r--` |
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| `1011` | `rw-` | `r--` |
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| `1100` | `---` | `rw-` |
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| `1101` | `r-x` | `rw-` |
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| `1110` | `r--` | `rw-` |
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| `1111` | `rw-` | `rw-` |
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These four bits indicate the actual permissions when running in EL or GL mode.
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EL0 and EL1 have separate registers such that the permissions are decoupled.
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bit 1 in S3_6_C15_C1_0 / SPRR_CONFIG_EL1 enables SPRR and access to new system registers.
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S3_6_C15_1_5 is the permissions register for EL0 and S3_6_C15_1_6 is for EL1/GL1.
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```
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#define SYS_SPRR_CONFIG_EL1 sys_reg(3, 6, 15, 1, 0)
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#define SPRR_CONFIG_EN BIT(0)
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#define SPRR_CONFIG_LOCK_CONFIG BIT(1)
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#define SPRR_CONFIG_LOCK_PERM_EL0 BIT(4)
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#define SPRR_CONFIG_LOCK_PERM_EL1 BIT(5)
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#define SYS_SPRR_PERM_EL0 sys_reg(3, 6, 15, 1, 5)
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#define SYS_SPRR_PERM_EL1 sys_reg(3, 6, 15, 1, 6)
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```
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