0 HW:CPU debug registers

pipcet edited this page 2021-05-10 22:27:01 +00:00

The various CPU cores export entries in the ADT that hint at the existence of debug registers. The string "coresight" appears, and coresight register files are unlocked by writing 0xc5acce55 to offset 0xfb0, which is also what the Corellium CPU start code does. The lock status register is at 0x210030fb4 for CPU0.

CPU0's PC can be read at 0x210040090 (the usual offsets apply to the other cores), but the other registers don't appear to be making any obvious appearances.

Feature Support:

• M1 Series Feature Support
• M2 Series Feature Support
• M3 Series Feature Support

Project related:

• Glossary
• FAQ
• "When will Asahi Linux be done?"
• Project:References
• Recent Changes

Platform documentation:

• Apple Silicon Subsystems
• Apple Platform Security Crash Course
• Devices
• Codenames
• Display Controllers

For users:

• Broken Software
• Alternative Distros

For developers:

• Yaks in need of shaving (HELP WANTED!)
• Tethered Boot Setup (For Developers)
• m1n1:User Guide Boot loader
• Hypervisor
• U-Boot
• Devicetree bindings
• Open OS ecosystem on Apple Silicon Macs

Wiki for the Asahi Linux project: https://asahilinux.org/